litesata: remove unneeded clock constraint

diff --git a/misoclib/mem/litesata/example_designs/platforms/kc705.py b/misoclib/mem/litesata/example_designs/platforms/kc705.py
index c39b366d45b5813a037617f33482002ce03a7e3c..9a8cbdd5b4678bcf15bf08c17eb2e6bf4c9bf3ed 100644 (file)
--- a/misoclib/mem/litesata/example_designs/platforms/kc705.py
+++ b/misoclib/mem/litesata/example_designs/platforms/kc705.py
@@ -33,10 +33,6 @@ class Platform(SpecializedPlatform):
                                self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
                        except ConstraintError:
                                pass
-                       try:
-                               self.add_period_constraint(self.lookup_request("sata_host").refclk_p, 6.66)
-                       except ConstraintError:
-                               pass
                        self.add_platform_command("""
 create_clock -name sys_clk -period 6 [get_nets sys_clk]
 create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk]