ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
authorSylvain Munaut <tnt@246tNt.com>
Tue, 16 Jul 2019 21:57:15 +0000 (23:57 +0200)
committerSylvain Munaut <tnt@246tNt.com>
Tue, 16 Jul 2019 21:57:15 +0000 (23:57 +0200)
The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d
needed matching adaptation when converting and optimizing LUTs during
the relut process

Fixes #1187

(Diagnosis of the issue by @daveshah1 on IRC)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
techlibs/ice40/ice40_unlut.cc
techlibs/ice40/synth_ice40.cc

index d16e6e6a391e87eddd8e21c4a54c469f2fb344a1..f3f70ac1fb2ea4b4efd93d6d5a03c7cf072314b2 100644 (file)
@@ -56,10 +56,10 @@ static void run_ice40_unlut(Module *module)
                        cell->unsetParam("\\LUT_INIT");
 
                        cell->setPort("\\A", SigSpec({
-                               get_bit_or_zero(cell->getPort("\\I3")),
-                               get_bit_or_zero(cell->getPort("\\I2")),
+                               get_bit_or_zero(cell->getPort("\\I0")),
                                get_bit_or_zero(cell->getPort("\\I1")),
-                               get_bit_or_zero(cell->getPort("\\I0"))
+                               get_bit_or_zero(cell->getPort("\\I2")),
+                               get_bit_or_zero(cell->getPort("\\I3"))
                        }));
                        cell->setPort("\\Y", cell->getPort("\\O")[0]);
                        cell->unsetPort("\\I0");
index b3d30791a59ad6769e16dc2f5f026a767559a87b..78ac5ea13f09f95156f14a467fee445bfabfc2b9 100644 (file)
@@ -345,7 +345,7 @@ struct SynthIce40Pass : public ScriptPass
                        }
                        run("clean");
                        run("ice40_unlut");
-                       run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3");
+                       run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
                }
 
                if (check_label("map_cells"))