xilinx: Add some missing blackbox cells.

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 4162160bbe2afb5ed14be969c96da0f2bf0ac166..adaf7aee1e8abc93e10a2f13bbeeabccd05c4e02 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -2023,6 +2023,105 @@ module RAM64M8 (
     end
 endmodule
 
+module RAM32X16DR8 (
+  output       DOA,
+  output       DOB,
+  output       DOC,
+  output       DOD,
+  output       DOE,
+  output       DOF,
+  output       DOG,
+  output [1:0] DOH,
+  input  [5:0] ADDRA, ADDRB, ADDRC, ADDRD, ADDRE, ADDRF, ADDRG,
+  input  [4:0] ADDRH,
+  input  [1:0] DIA,
+  input  [1:0] DIB,
+  input  [1:0] DIC,
+  input  [1:0] DID,
+  input  [1:0] DIE,
+  input  [1:0] DIF,
+  input  [1:0] DIG,
+  input  [1:0] DIH,
+  (* clkbuf_sink *)
+  (* invertible_pin = "IS_WCLK_INVERTED" *)
+  input        WCLK,
+  input        WE
+);
+  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+  reg [63:0] mem_a, mem_b, mem_c, mem_d, mem_e, mem_f, mem_g, mem_h;
+  assign DOA = mem_a[ADDRA];
+  assign DOB = mem_b[ADDRB];
+  assign DOC = mem_c[ADDRC];
+  assign DOD = mem_d[ADDRD];
+  assign DOE = mem_e[ADDRE];
+  assign DOF = mem_f[ADDRF];
+  assign DOG = mem_g[ADDRG];
+  assign DOH = mem_h[2*ADDRH+:2];
+  wire clk = WCLK ^ IS_WCLK_INVERTED;
+  always @(posedge clk)
+    if (WE) begin
+      mem_a[2*ADDRH+:2] <= DIA;
+      mem_b[2*ADDRH+:2] <= DIB;
+      mem_c[2*ADDRH+:2] <= DIC;
+      mem_d[2*ADDRH+:2] <= DID;
+      mem_e[2*ADDRH+:2] <= DIE;
+      mem_f[2*ADDRH+:2] <= DIF;
+      mem_g[2*ADDRH+:2] <= DIG;
+      mem_h[2*ADDRH+:2] <= DIH;
+    end
+endmodule
+
+module RAM64X8SW (
+  output [7:0] O,
+  input [5:0] A,
+  input D,
+  (* clkbuf_sink *)
+  (* invertible_pin = "IS_WCLK_INVERTED" *)
+  input WCLK,
+  input WE,
+  input [2:0] WSEL
+);
+  parameter [63:0] INIT_A = 64'h0000000000000000;
+  parameter [63:0] INIT_B = 64'h0000000000000000;
+  parameter [63:0] INIT_C = 64'h0000000000000000;
+  parameter [63:0] INIT_D = 64'h0000000000000000;
+  parameter [63:0] INIT_E = 64'h0000000000000000;
+  parameter [63:0] INIT_F = 64'h0000000000000000;
+  parameter [63:0] INIT_G = 64'h0000000000000000;
+  parameter [63:0] INIT_H = 64'h0000000000000000;
+  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+  reg [63:0] mem_a = INIT_A;
+  reg [63:0] mem_b = INIT_B;
+  reg [63:0] mem_c = INIT_C;
+  reg [63:0] mem_d = INIT_D;
+  reg [63:0] mem_e = INIT_E;
+  reg [63:0] mem_f = INIT_F;
+  reg [63:0] mem_g = INIT_G;
+  reg [63:0] mem_h = INIT_H;
+  assign O[7] = mem_a[A];
+  assign O[6] = mem_b[A];
+  assign O[5] = mem_c[A];
+  assign O[4] = mem_d[A];
+  assign O[3] = mem_e[A];
+  assign O[2] = mem_f[A];
+  assign O[1] = mem_g[A];
+  assign O[0] = mem_h[A];
+  wire clk = WCLK ^ IS_WCLK_INVERTED;
+  always @(posedge clk)
+    if (WE) begin
+      case (WSEL)
+      3'b111: mem_a[A] <= D;
+      3'b110: mem_b[A] <= D;
+      3'b101: mem_c[A] <= D;
+      3'b100: mem_d[A] <= D;
+      3'b011: mem_e[A] <= D;
+      3'b010: mem_f[A] <= D;
+      3'b001: mem_g[A] <= D;
+      3'b000: mem_h[A] <= D;
+      endcase
+    end
+endmodule
+
 // ROM.
 
 module ROM16X1 (

diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index c7ffb94cf6d42f97dfa0a522c2c04d5f84501009..cb23b97872e7af0ec9f88b2f28edbac44fedc3fc 100644 (file)
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -57,6 +57,8 @@ CELLS = [
     # Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}),
     # Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
     # Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM32X16DR8', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM64X8SW', port_attrs={'WCLK': ['clkbuf_sink']}),
     # Cell('ROM16X1'),
     # Cell('ROM32X1'),
     # Cell('ROM64X1'),
@@ -243,12 +245,12 @@ CELLS = [
         'CLKDIVP': ['clkbuf_sink'],
     }),
     Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
-    Cell('PHASER_IN'),
-    Cell('PHASER_IN_PHY'),
-    Cell('PHASER_OUT'),
-    Cell('PHASER_OUT_PHY'),
-    Cell('PHASER_REF'),
-    Cell('PHY_CONTROL'),
+    Cell('PHASER_IN', keep=True),
+    Cell('PHASER_IN_PHY', keep=True),
+    Cell('PHASER_OUT', keep=True),
+    Cell('PHASER_OUT_PHY', keep=True),
+    Cell('PHASER_REF', keep=True),
+    Cell('PHY_CONTROL', keep=True),
     # Ultrascale.
     Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
     Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}),
@@ -262,7 +264,7 @@ CELLS = [
     }),
     Cell('OSERDESE3', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
     Cell('BITSLICE_CONTROL', keep=True),
-    Cell('RIU_OR'),
+    Cell('RIU_OR', keep=True),
     Cell('RX_BITSLICE'),
     Cell('RXTX_BITSLICE'),
     Cell('TX_BITSLICE'),
@@ -327,7 +329,7 @@ CELLS = [
     Cell('PULLUP'),
     # Misc.
     Cell('DCIRESET', keep=True),
-    Cell('HPIO_VREF'), # Ultrascale
+    Cell('HPIO_VREF', keep=True), # Ultrascale
 
     # Clock buffers (global).
     # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
@@ -456,6 +458,7 @@ CELLS = [
     Cell('FRAME_ECC_VIRTEX6'),
     Cell('FRAME_ECCE2'), # Series 7
     Cell('FRAME_ECCE3'), # Ultrascale
+    Cell('FRAME_ECCE4'), # Ultrascale+
     # AXSS command access.
     Cell('USR_ACCESS_VIRTEX4'),
     Cell('USR_ACCESS_VIRTEX5'),
@@ -470,10 +473,10 @@ CELLS = [
     Cell('EFUSE_USR'),
 
     # ADC.
-    Cell('SYSMON'), # Virtex 5/6
-    Cell('XADC'), # Series 7
-    Cell('SYSMONE1'), # Ultrascale
-    Cell('SYSMONE4'), # Ultrascale+
+    Cell('SYSMON', keep=True), # Virtex 5/6
+    Cell('XADC', keep=True), # Series 7
+    Cell('SYSMONE1', keep=True), # Ultrascale
+    Cell('SYSMONE4', keep=True), # Ultrascale+
 
     # Gigabit transceivers.
     # Spartan 6.
@@ -507,18 +510,30 @@ CELLS = [
     # Ultrascale.
     Cell('GTHE3_CHANNEL'),
     Cell('GTHE3_COMMON'),
-    Cell('GTHE4_CHANNEL'),
-    Cell('GTHE4_COMMON'),
     Cell('GTYE3_CHANNEL'),
     Cell('GTYE3_COMMON'),
-    Cell('GTYE4_CHANNEL'),
-    Cell('GTYE4_COMMON'),
     Cell('IBUFDS_GTE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
-    Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
     Cell('OBUFDS_GTE3', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
     Cell('OBUFDS_GTE3_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    # Ultrascale+.
+    Cell('GTHE4_CHANNEL'),
+    Cell('GTHE4_COMMON'),
+    Cell('GTYE4_CHANNEL'),
+    Cell('GTYE4_COMMON'),
+    Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
     Cell('OBUFDS_GTE4', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
     Cell('OBUFDS_GTE4_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    # Ultrascale+ GTM.
+    Cell('GTM_DUAL'), # not in the libraries guide
+    Cell('IBUFDS_GTM', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('OBUFDS_GTM', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('OBUFDS_GTM_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+
+    # High-speed ADC/DAC.
+    Cell('HSDAC'), # not in libraries guide
+    Cell('HSADC'), # not in libraries guide
+    Cell('RFDAC'), # not in libraries guide
+    Cell('RFADC'), # not in libraries guide
 
     # PCIE IP.
     Cell('PCIE_A1'), # Spartan 6
@@ -528,6 +543,7 @@ CELLS = [
     Cell('PCIE_3_0'), # Series 7
     Cell('PCIE_3_1'), # Ultrascale
     Cell('PCIE40E4'), # Ultrascale+
+    Cell('PCIE4CE4'), # Ultrascale+ v2 (not in the libraries guide)
 
     # Ethernet IP.
     Cell('EMAC'), # Virtex 4
@@ -536,17 +552,29 @@ CELLS = [
     Cell('CMAC'), # Ultrascale
     Cell('CMACE4'), # Ultrsacale+
 
+    # Hard memory controllers.
+    Cell('MCB'), # Spartan 6 Memory Controller Block
+    Cell('HBM_REF_CLK', keep=True), # not in liraries guide
+    # not sure how the following relate to the hw
+    Cell('HBM_SNGLBLI_INTF_APB', keep=True), # not in liraries guide
+    Cell('HBM_SNGLBLI_INTF_AXI', keep=True), # not in liraries guide
+    Cell('HBM_ONE_STACK_INTF', keep=True), # not in liraries guide
+    Cell('HBM_TWO_STACK_INTF', keep=True), # not in liraries guide
+
     # PowerPC.
     # TODO PPC405 (Virtex 2)
     Cell('PPC405_ADV'), # Virtex 4
     Cell('PPC440'), # Virtex 5
 
+    # ARM.
+    Cell('PS7', keep=True), # The Zynq 7000 ARM Processor System (not in libraries guide).
+    Cell('PS8', keep=True), # The Zynq Ultrascale+ ARM Processor System (not in libraries guide).
+
     # Misc hard IP.
-    Cell('MCB'), # Spartan 6 Memory Controller Block
-    Cell('PS7', keep=True), # The Zynq 7000 ARM Processor System.
-    Cell('PS8', keep=True), # The Zynq Ultrascale+ ARM Processor System.
     Cell('ILKN'), # Ultrascale Interlaken
     Cell('ILKNE4'), # Ultrascale+ Interlaken
+    Cell('VCU', keep=True), # Zynq MPSoC Video Codec Unit (not in libraries guide).
+    Cell('FE'), # Zynq RFSoC Forward Error Correction (not in libraries guide).
 ]
 
 
@@ -559,100 +587,101 @@ class State(Enum):
 
 def xtract_cell_decl(cell, dirs, outf):
     for dir in dirs:
-        fname = os.path.join(dir, cell.name + '.v')
-        try:
-            with open(fname) as f:
-                state = State.OUTSIDE
-                found = False
-                # Probably the most horrible Verilog "parser" ever written.
-                module_ports = []
-                invertible_ports = set()
-                for l in f:
-                    l = l.partition('//')[0]
-                    l = l.strip()
-                    if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)):
-                        if found:
-                            print('Multiple modules in {}.'.format(fname))
-                            sys.exit(1)
-                        elif state != State.OUTSIDE:
-                            print('Nested modules in {}.'.format(fname))
-                            sys.exit(1)
-                        found = True
-                        state = State.IN_MODULE
-                        if cell.keep:
-                            outf.write('(* keep *)\n')
-                        outf.write('module {} (...);\n'.format(cell.name))
-                    elif l.startswith('module '):
-                        if state != State.OUTSIDE:
-                            print('Nested modules in {}.'.format(fname))
-                            sys.exit(1)
-                        state = State.IN_OTHER_MODULE
-                    elif l.startswith('task '):
-                        if state == State.IN_MODULE:
-                            state = State.IN_TASK
-                    elif l.startswith('function '):
-                        if state == State.IN_MODULE:
-                            state = State.IN_FUNCTION
-                    elif l == 'endtask':
-                        if state == State.IN_TASK:
-                            state = State.IN_MODULE
-                    elif l == 'endfunction':
-                        if state == State.IN_FUNCTION:
+        for ext in ['.v', '.sv']:
+            fname = os.path.join(dir, cell.name + ext)
+            try:
+                with open(fname) as f:
+                    state = State.OUTSIDE
+                    found = False
+                    # Probably the most horrible Verilog "parser" ever written.
+                    module_ports = []
+                    invertible_ports = set()
+                    for l in f:
+                        l = l.partition('//')[0]
+                        l = l.strip()
+                        if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)):
+                            if found:
+                                print('Multiple modules in {}.'.format(fname))
+                                sys.exit(1)
+                            elif state != State.OUTSIDE:
+                                print('Nested modules in {}.'.format(fname))
+                                sys.exit(1)
+                            found = True
                             state = State.IN_MODULE
-                    elif l == 'endmodule':
-                        if state == State.IN_MODULE:
-                            for kind, rng, port in module_ports:
-                                for attr in cell.port_attrs.get(port, []):
-                                    outf.write('    (* {} *)\n'.format(attr))
-                                if port in invertible_ports:
-                                    outf.write('    (* invertible_pin = "IS_{}_INVERTED" *)\n'.format(port))
-                                if rng is None:
-                                    outf.write('    {} {};\n'.format(kind, port))
+                            if cell.keep:
+                                outf.write('(* keep *)\n')
+                            outf.write('module {} (...);\n'.format(cell.name))
+                        elif l.startswith('module '):
+                            if state != State.OUTSIDE:
+                                print('Nested modules in {}.'.format(fname))
+                                sys.exit(1)
+                            state = State.IN_OTHER_MODULE
+                        elif l.startswith('task '):
+                            if state == State.IN_MODULE:
+                                state = State.IN_TASK
+                        elif l.startswith('function '):
+                            if state == State.IN_MODULE:
+                                state = State.IN_FUNCTION
+                        elif l == 'endtask':
+                            if state == State.IN_TASK:
+                                state = State.IN_MODULE
+                        elif l == 'endfunction':
+                            if state == State.IN_FUNCTION:
+                                state = State.IN_MODULE
+                        elif l == 'endmodule':
+                            if state == State.IN_MODULE:
+                                for kind, rng, port in module_ports:
+                                    for attr in cell.port_attrs.get(port, []):
+                                        outf.write('    (* {} *)\n'.format(attr))
+                                    if port in invertible_ports:
+                                        outf.write('    (* invertible_pin = "IS_{}_INVERTED" *)\n'.format(port))
+                                    if rng is None:
+                                        outf.write('    {} {};\n'.format(kind, port))
+                                    else:
+                                        outf.write('    {} {} {};\n'.format(kind, rng, port))
+                                outf.write(l + '\n')
+                                outf.write('\n')
+                            elif state != State.IN_OTHER_MODULE:
+                                print('endmodule in weird place in {}.'.format(cell.name, fname))
+                                sys.exit(1)
+                            state = State.OUTSIDE
+                        elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
+                            if l.endswith((';', ',')):
+                                l = l[:-1]
+                            if ';' in l:
+                                print('Weird port line in {} [{}].'.format(fname, l))
+                                sys.exit(1)
+                            kind, _, ports = l.partition(' ')
+                            for port in ports.split(','):
+                                port = port.strip()
+                                if port.startswith('['):
+                                    rng, port = port.split()
                                 else:
-                                    outf.write('    {} {} {};\n'.format(kind, rng, port))
-                            outf.write(l + '\n')
-                            outf.write('\n')
-                        elif state != State.IN_OTHER_MODULE:
-                            print('endmodule in weird place in {}.'.format(cell.name, fname))
-                            sys.exit(1)
-                        state = State.OUTSIDE
-                    elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
-                        if l.endswith((';', ',')):
-                            l = l[:-1]
-                        if ';' in l:
-                            print('Weird port line in {} [{}].'.format(fname, l))
-                            sys.exit(1)
-                        kind, _, ports = l.partition(' ')
-                        for port in ports.split(','):
-                            port = port.strip()
-                            if port.startswith('['):
-                                rng, port = port.split()
-                            else:
-                                rng = None
-                            module_ports.append((kind, rng, port))
-                    elif l.startswith('parameter ') and state == State.IN_MODULE:
-                        if 'UNPLACED' in l:
-                            continue
-                        if l.endswith((';', ',')):
-                            l = l[:-1]
-                        while '  ' in l:
-                            l = l.replace('  ', ' ')
-                        if ';' in l:
-                            print('Weird parameter line in {} [{}].'.format(fname, l))
-                            sys.exit(1)
-                        outf.write('    {};\n'.format(l))
-                        match = re.search('IS_([a-zA-Z0-9_]+)_INVERTED', l)
-                        if match:
-                            invertible_ports.add(match[1])
-                if state != State.OUTSIDE:
-                    print('endmodule not found in {}.'.format(fname))
-                    sys.exit(1)
-                if not found:
-                    print('Cannot find module {} in {}.'.format(cell.name, fname))
-                    sys.exit(1)
-            return
-        except FileNotFoundError:
-            continue
+                                    rng = None
+                                module_ports.append((kind, rng, port))
+                        elif l.startswith('parameter ') and state == State.IN_MODULE:
+                            if 'UNPLACED' in l:
+                                continue
+                            if l.endswith((';', ',')):
+                                l = l[:-1]
+                            while '  ' in l:
+                                l = l.replace('  ', ' ')
+                            if ';' in l:
+                                print('Weird parameter line in {} [{}].'.format(fname, l))
+                                sys.exit(1)
+                            outf.write('    {};\n'.format(l))
+                            match = re.search('IS_([a-zA-Z0-9_]+)_INVERTED', l)
+                            if match:
+                                invertible_ports.add(match[1])
+                    if state != State.OUTSIDE:
+                        print('endmodule not found in {}.'.format(fname))
+                        sys.exit(1)
+                    if not found:
+                        print('Cannot find module {} in {}.'.format(cell.name, fname))
+                        sys.exit(1)
+                return
+            except FileNotFoundError:
+                continue
     print('Cannot find {}.'.format(cell.name))
     sys.exit(1)
 

diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 1fb340fc01dc398d6d730bce4f5dd5c71de54c03..1187101fda9e2d4e1d48582a71c423cb4c7119e9 100644 (file)
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -5994,6 +5994,7 @@ module OSERDESE2 (...);
     input TCE;
 endmodule
 
+(* keep *)
 module PHASER_IN (...);
     parameter integer CLKOUT_DIV = 4;
     parameter DQS_BIAS_MODE = "FALSE";
@@ -6030,6 +6031,7 @@ module PHASER_IN (...);
     input [5:0] COUNTERLOADVAL;
 endmodule
 
+(* keep *)
 module PHASER_IN_PHY (...);
     parameter BURST_MODE = "FALSE";
     parameter integer CLKOUT_DIV = 4;
@@ -6074,6 +6076,7 @@ module PHASER_IN_PHY (...);
     input [5:0] COUNTERLOADVAL;
 endmodule
 
+(* keep *)
 module PHASER_OUT (...);
     parameter integer CLKOUT_DIV = 4;
     parameter COARSE_BYPASS = "FALSE";
@@ -6115,6 +6118,7 @@ module PHASER_OUT (...);
     input [8:0] COUNTERLOADVAL;
 endmodule
 
+(* keep *)
 module PHASER_OUT_PHY (...);
     parameter integer CLKOUT_DIV = 4;
     parameter COARSE_BYPASS = "FALSE";
@@ -6161,6 +6165,7 @@ module PHASER_OUT_PHY (...);
     input [8:0] COUNTERLOADVAL;
 endmodule
 
+(* keep *)
 module PHASER_REF (...);
     parameter [0:0] IS_RST_INVERTED = 1'b0;
     parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
@@ -6172,6 +6177,7 @@ module PHASER_REF (...);
     input RST;
 endmodule
 
+(* keep *)
 module PHY_CONTROL (...);
     parameter integer AO_TOGGLE = 0;
     parameter [3:0] AO_WRLVL_EN = 4'b0000;
@@ -6466,6 +6472,7 @@ module BITSLICE_CONTROL (...);
     input [39:0] TX_BIT_CTRL_IN_TRI;
 endmodule
 
+(* keep *)
 module RIU_OR (...);
     parameter SIM_DEVICE = "ULTRASCALE";
     parameter real SIM_VERSION = 2.0;
@@ -7275,6 +7282,7 @@ module DCIRESET (...);
     input RST;
 endmodule
 
+(* keep *)
 module HPIO_VREF (...);
     parameter VREF_CNTR = "OFF";
     output VREF;
@@ -9232,6 +9240,18 @@ module FRAME_ECCE3 (...);
     input ICAPTOPCLK;
 endmodule
 
+module FRAME_ECCE4 (...);
+    output CRCERROR;
+    output ECCERRORNOTSINGLE;
+    output ECCERRORSINGLE;
+    output ENDOFFRAME;
+    output ENDOFSCAN;
+    output [26:0] FAR;
+    input [1:0] FARSEL;
+    input ICAPBOTCLK;
+    input ICAPTOPCLK;
+endmodule
+
 module USR_ACCESS_VIRTEX4 (...);
     output [31:0] DATA;
     output DATAVALID;
@@ -9297,6 +9317,7 @@ module EFUSE_USR (...);
     output [31:0] EFUSEUSR;
 endmodule
 
+(* keep *)
 module SYSMON (...);
     parameter [15:0] INIT_40 = 16'h0;
     parameter [15:0] INIT_41 = 16'h0;
@@ -9349,6 +9370,7 @@ module SYSMON (...);
     input [6:0] DADDR;
 endmodule
 
+(* keep *)
 module XADC (...);
     parameter [15:0] INIT_40 = 16'h0;
     parameter [15:0] INIT_41 = 16'h0;
@@ -9414,6 +9436,7 @@ module XADC (...);
     input [6:0] DADDR;
 endmodule
 
+(* keep *)
 module SYSMONE1 (...);
     parameter [15:0] INIT_40 = 16'h0;
     parameter [15:0] INIT_41 = 16'h0;
@@ -9522,6 +9545,7 @@ module SYSMONE1 (...);
     input VP;
 endmodule
 
+(* keep *)
 module SYSMONE4 (...);
     parameter [15:0] COMMON_N_SOURCE = 16'hFFFF;
     parameter [15:0] INIT_40 = 16'h0000;
@@ -15163,13 +15187,13 @@ module GTHE3_COMMON (...);
     input RCALENB;
 endmodule
 
-module GTHE4_CHANNEL (...);
+module GTYE3_CHANNEL (...);
     parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
     parameter [0:0] ACJTAG_MODE = 1'b0;
     parameter [0:0] ACJTAG_RESET = 1'b0;
     parameter [15:0] ADAPT_CFG0 = 16'h9200;
     parameter [15:0] ADAPT_CFG1 = 16'h801C;
-    parameter [15:0] ADAPT_CFG2 = 16'h0000;
+    parameter [15:0] ADAPT_CFG2 = 16'b0000000000000000;
     parameter ALIGN_COMMA_DOUBLE = "FALSE";
     parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
     parameter integer ALIGN_COMMA_WORD = 1;
@@ -15177,15 +15201,14 @@ module GTHE4_CHANNEL (...);
     parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
     parameter ALIGN_PCOMMA_DET = "TRUE";
     parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
+    parameter [0:0] AUTO_BW_SEL_BYPASS = 1'b0;
     parameter [0:0] A_RXOSCALRESET = 1'b0;
     parameter [0:0] A_RXPROGDIVRESET = 1'b0;
-    parameter [0:0] A_RXTERMINATION = 1'b1;
     parameter [4:0] A_TXDIFFCTRL = 5'b01100;
     parameter [0:0] A_TXPROGDIVRESET = 1'b0;
     parameter [0:0] CAPBYPASS_FORCE = 1'b0;
     parameter CBCC_DATA_SOURCE_SEL = "DECODED";
     parameter [0:0] CDR_SWAP_MODE_EN = 1'b0;
-    parameter [0:0] CFOK_PWRSVE_EN = 1'b1;
     parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
     parameter integer CHAN_BOND_MAX_SKEW = 7;
     parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
@@ -15200,7 +15223,7 @@ module GTHE4_CHANNEL (...);
     parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
     parameter CHAN_BOND_SEQ_2_USE = "FALSE";
     parameter integer CHAN_BOND_SEQ_LEN = 2;
-    parameter [15:0] CH_HSPMUX = 16'h2424;
+    parameter [15:0] CH_HSPMUX = 16'h0000;
     parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000;
     parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000;
     parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000;
@@ -15210,7 +15233,7 @@ module GTHE4_CHANNEL (...);
     parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000;
     parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000;
     parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000;
-    parameter [15:0] CKCAL_RSVD0 = 16'h4000;
+    parameter [15:0] CKCAL_RSVD0 = 16'h0000;
     parameter [15:0] CKCAL_RSVD1 = 16'h0000;
     parameter CLK_CORRECT_USE = "TRUE";
     parameter CLK_COR_KEEP_IDLE = "FALSE";
@@ -15230,13 +15253,14 @@ module GTHE4_CHANNEL (...);
     parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
     parameter CLK_COR_SEQ_2_USE = "FALSE";
     parameter integer CLK_COR_SEQ_LEN = 2;
-    parameter [15:0] CPLL_CFG0 = 16'h01FA;
-    parameter [15:0] CPLL_CFG1 = 16'h24A9;
-    parameter [15:0] CPLL_CFG2 = 16'h6807;
-    parameter [15:0] CPLL_CFG3 = 16'h0000;
+    parameter [15:0] CPLL_CFG0 = 16'h20F8;
+    parameter [15:0] CPLL_CFG1 = 16'hA494;
+    parameter [15:0] CPLL_CFG2 = 16'hF001;
+    parameter [5:0] CPLL_CFG3 = 6'h00;
     parameter integer CPLL_FBDIV = 4;
     parameter integer CPLL_FBDIV_45 = 4;
     parameter [15:0] CPLL_INIT_CFG0 = 16'h001E;
+    parameter [7:0] CPLL_INIT_CFG1 = 8'h00;
     parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
     parameter integer CPLL_REFCLK_DIV = 1;
     parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000;
@@ -15246,14 +15270,16 @@ module GTHE4_CHANNEL (...);
     parameter DEC_MCOMMA_DETECT = "TRUE";
     parameter DEC_PCOMMA_DETECT = "TRUE";
     parameter DEC_VALID_COMMA_ONLY = "TRUE";
-    parameter [0:0] DELAY_ELEC = 1'b0;
+    parameter [0:0] DFE_D_X_REL_POS = 1'b0;
+    parameter [0:0] DFE_VCM_COMP_EN = 1'b0;
     parameter [9:0] DMONITOR_CFG0 = 10'h000;
     parameter [7:0] DMONITOR_CFG1 = 8'h00;
     parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
     parameter [5:0] ES_CONTROL = 6'b000000;
     parameter ES_ERRDET_EN = "FALSE";
     parameter ES_EYE_SCAN_EN = "FALSE";
-    parameter [11:0] ES_HORZ_OFFSET = 12'h800;
+    parameter [11:0] ES_HORZ_OFFSET = 12'h000;
+    parameter [9:0] ES_PMA_CFG = 10'b0000000000;
     parameter [4:0] ES_PRESCALE = 5'b00000;
     parameter [15:0] ES_QUALIFIER0 = 16'h0000;
     parameter [15:0] ES_QUALIFIER1 = 16'h0000;
@@ -15285,19 +15311,32 @@ module GTHE4_CHANNEL (...);
     parameter [15:0] ES_SDATA_MASK7 = 16'h0000;
     parameter [15:0] ES_SDATA_MASK8 = 16'h0000;
     parameter [15:0] ES_SDATA_MASK9 = 16'h0000;
+    parameter [10:0] EVODD_PHI_CFG = 11'b00000000000;
     parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0;
     parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
     parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
     parameter FTS_LANE_DESKEW_EN = "FALSE";
     parameter [4:0] GEARBOX_MODE = 5'b00000;
+    parameter [0:0] GM_BIAS_SELECT = 1'b0;
     parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0;
     parameter [0:0] LOCAL_MASTER = 1'b0;
+    parameter [15:0] LOOP0_CFG = 16'h0000;
+    parameter [15:0] LOOP10_CFG = 16'h0000;
+    parameter [15:0] LOOP11_CFG = 16'h0000;
+    parameter [15:0] LOOP12_CFG = 16'h0000;
+    parameter [15:0] LOOP13_CFG = 16'h0000;
+    parameter [15:0] LOOP1_CFG = 16'h0000;
+    parameter [15:0] LOOP2_CFG = 16'h0000;
+    parameter [15:0] LOOP3_CFG = 16'h0000;
+    parameter [15:0] LOOP4_CFG = 16'h0000;
+    parameter [15:0] LOOP5_CFG = 16'h0000;
+    parameter [15:0] LOOP6_CFG = 16'h0000;
+    parameter [15:0] LOOP7_CFG = 16'h0000;
+    parameter [15:0] LOOP8_CFG = 16'h0000;
+    parameter [15:0] LOOP9_CFG = 16'h0000;
     parameter [2:0] LPBK_BIAS_CTRL = 3'b000;
     parameter [0:0] LPBK_EN_RCAL_B = 1'b0;
     parameter [3:0] LPBK_EXT_RCAL = 4'b0000;
-    parameter [2:0] LPBK_IND_CTRL0 = 3'b000;
-    parameter [2:0] LPBK_IND_CTRL1 = 3'b000;
-    parameter [2:0] LPBK_IND_CTRL2 = 3'b000;
     parameter [3:0] LPBK_RG_CTRL = 4'b0000;
     parameter [1:0] OOBDIVCTL = 2'b00;
     parameter [0:0] OOB_PWRUP = 1'b0;
@@ -15310,32 +15349,25 @@ module GTHE4_CHANNEL (...);
     parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000;
     parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0;
     parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0;
-    parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000;
-    parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000;
-    parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000;
-    parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100;
-    parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000;
     parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000;
-    parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0;
-    parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0;
-    parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0;
     parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000;
     parameter [15:0] PCIE_RXPMA_CFG = 16'h0000;
     parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000;
     parameter [15:0] PCIE_TXPMA_CFG = 16'h0000;
     parameter PCS_PCIE_EN = "FALSE";
     parameter [15:0] PCS_RSVD0 = 16'b0000000000000000;
+    parameter [2:0] PCS_RSVD1 = 3'b000;
     parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
     parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
     parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
+    parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0;
+    parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0;
+    parameter [15:0] PMA_RSV0 = 16'h0000;
+    parameter [15:0] PMA_RSV1 = 16'h0000;
     parameter integer PREIQ_FREQ_BST = 0;
     parameter [2:0] PROCESS_PAR = 3'b010;
     parameter [0:0] RATE_SW_USE_DRP = 1'b0;
-    parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0;
-    parameter [0:0] RCLK_SIPO_INV_EN = 1'b0;
     parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0;
-    parameter [2:0] RTX_BUF_CML_CTRL = 3'b010;
-    parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00;
     parameter [4:0] RXBUFRESET_TIME = 5'b00001;
     parameter RXBUF_ADDR_MODE = "FULL";
     parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
@@ -15350,48 +15382,37 @@ module GTHE4_CHANNEL (...);
     parameter integer RXBUF_THRESH_UNDFLW = 4;
     parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
     parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
-    parameter [15:0] RXCDR_CFG0 = 16'h0003;
-    parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003;
-    parameter [15:0] RXCDR_CFG1 = 16'h0000;
-    parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000;
-    parameter [15:0] RXCDR_CFG2 = 16'h0164;
-    parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164;
-    parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034;
-    parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034;
-    parameter [15:0] RXCDR_CFG3 = 16'h0024;
-    parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24;
-    parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024;
-    parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024;
-    parameter [15:0] RXCDR_CFG4 = 16'h5CF6;
-    parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6;
-    parameter [15:0] RXCDR_CFG5 = 16'hB46B;
-    parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B;
+    parameter [15:0] RXCDR_CFG0 = 16'h0000;
+    parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000;
+    parameter [15:0] RXCDR_CFG1 = 16'h0300;
+    parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0300;
+    parameter [15:0] RXCDR_CFG2 = 16'h0060;
+    parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0060;
+    parameter [15:0] RXCDR_CFG3 = 16'h0000;
+    parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000;
+    parameter [15:0] RXCDR_CFG4 = 16'h0002;
+    parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0002;
+    parameter [15:0] RXCDR_CFG5 = 16'h0000;
+    parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000;
     parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
     parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
-    parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040;
-    parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000;
+    parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0001;
+    parameter [15:0] RXCDR_LOCK_CFG1 = 16'h0000;
     parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000;
     parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000;
-    parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000;
     parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
-    parameter [15:0] RXCFOK_CFG0 = 16'h0000;
-    parameter [15:0] RXCFOK_CFG1 = 16'h0002;
+    parameter [1:0] RXCFOKDONE_SRC = 2'b00;
+    parameter [15:0] RXCFOK_CFG0 = 16'h3E00;
+    parameter [15:0] RXCFOK_CFG1 = 16'h0042;
     parameter [15:0] RXCFOK_CFG2 = 16'h002D;
-    parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000;
-    parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000;
-    parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000;
-    parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000;
-    parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000;
-    parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000;
-    parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000;
     parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
     parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000;
     parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022;
     parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100;
-    parameter [15:0] RXDFE_CFG0 = 16'h4000;
+    parameter [15:0] RXDFE_CFG0 = 16'h4C00;
     parameter [15:0] RXDFE_CFG1 = 16'h0000;
-    parameter [15:0] RXDFE_GC_CFG0 = 16'h0000;
-    parameter [15:0] RXDFE_GC_CFG1 = 16'h0000;
+    parameter [15:0] RXDFE_GC_CFG0 = 16'h1E00;
+    parameter [15:0] RXDFE_GC_CFG1 = 16'h1900;
     parameter [15:0] RXDFE_GC_CFG2 = 16'h0000;
     parameter [15:0] RXDFE_H2_CFG0 = 16'h0000;
     parameter [15:0] RXDFE_H2_CFG1 = 16'h0002;
@@ -15421,31 +15442,26 @@ module GTHE4_CHANNEL (...);
     parameter [15:0] RXDFE_HE_CFG1 = 16'h0002;
     parameter [15:0] RXDFE_HF_CFG0 = 16'h0000;
     parameter [15:0] RXDFE_HF_CFG1 = 16'h0002;
-    parameter [15:0] RXDFE_KH_CFG0 = 16'h0000;
-    parameter [15:0] RXDFE_KH_CFG1 = 16'h0000;
-    parameter [15:0] RXDFE_KH_CFG2 = 16'h0000;
-    parameter [15:0] RXDFE_KH_CFG3 = 16'h0000;
     parameter [15:0] RXDFE_OS_CFG0 = 16'h0000;
-    parameter [15:0] RXDFE_OS_CFG1 = 16'h0002;
+    parameter [15:0] RXDFE_OS_CFG1 = 16'h0200;
     parameter [0:0] RXDFE_PWR_SAVING = 1'b0;
     parameter [15:0] RXDFE_UT_CFG0 = 16'h0000;
     parameter [15:0] RXDFE_UT_CFG1 = 16'h0002;
-    parameter [15:0] RXDFE_UT_CFG2 = 16'h0000;
     parameter [15:0] RXDFE_VP_CFG0 = 16'h0000;
     parameter [15:0] RXDFE_VP_CFG1 = 16'h0022;
-    parameter [15:0] RXDLY_CFG = 16'h0010;
+    parameter [15:0] RXDLY_CFG = 16'h001F;
     parameter [15:0] RXDLY_LCFG = 16'h0030;
     parameter RXELECIDLE_CFG = "SIGCFG_4";
     parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4;
     parameter RXGEARBOX_EN = "FALSE";
     parameter [4:0] RXISCANRESET_TIME = 5'b00001;
     parameter [15:0] RXLPM_CFG = 16'h0000;
-    parameter [15:0] RXLPM_GC_CFG = 16'h1000;
+    parameter [15:0] RXLPM_GC_CFG = 16'h0200;
     parameter [15:0] RXLPM_KH_CFG0 = 16'h0000;
     parameter [15:0] RXLPM_KH_CFG1 = 16'h0002;
-    parameter [15:0] RXLPM_OS_CFG0 = 16'h0000;
+    parameter [15:0] RXLPM_OS_CFG0 = 16'h0400;
     parameter [15:0] RXLPM_OS_CFG1 = 16'h0000;
-    parameter [8:0] RXOOB_CFG = 9'b000110000;
+    parameter [8:0] RXOOB_CFG = 9'b000000110;
     parameter RXOOB_CLK_CFG = "PMA";
     parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
     parameter integer RXOUT_DIV = 4;
@@ -15456,9 +15472,9 @@ module GTHE4_CHANNEL (...);
     parameter [15:0] RXPHSLIP_CFG = 16'h9933;
     parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
     parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0;
-    parameter [15:0] RXPI_CFG0 = 16'h0002;
-    parameter [15:0] RXPI_CFG1 = 16'b0000000000000000;
+    parameter [15:0] RXPI_CFG = 16'h0100;
     parameter [0:0] RXPI_LPM = 1'b0;
+    parameter [15:0] RXPI_RSV0 = 16'h0000;
     parameter [1:0] RXPI_SEL_LC = 2'b00;
     parameter [1:0] RXPI_STARTCODE = 2'b00;
     parameter [0:0] RXPI_VREFSEL = 1'b0;
@@ -15466,14 +15482,13 @@ module GTHE4_CHANNEL (...);
     parameter [4:0] RXPMARESET_TIME = 5'b00001;
     parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
     parameter integer RXPRBS_LINKACQ_CNT = 15;
-    parameter [0:0] RXREFCLKDIV2_SEL = 1'b0;
     parameter integer RXSLIDE_AUTO_WAIT = 7;
     parameter RXSLIDE_MODE = "OFF";
     parameter [0:0] RXSYNC_MULTILANE = 1'b0;
     parameter [0:0] RXSYNC_OVRD = 1'b0;
     parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
     parameter [0:0] RX_AFE_CM_EN = 1'b0;
-    parameter [15:0] RX_BIAS_CFG0 = 16'h12B0;
+    parameter [15:0] RX_BIAS_CFG0 = 16'h1534;
     parameter [5:0] RX_BUFFER_CFG = 6'b000000;
     parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0;
     parameter integer RX_CLK25_DIV = 8;
@@ -15482,27 +15497,29 @@ module GTHE4_CHANNEL (...);
     parameter [3:0] RX_CM_BUF_CFG = 4'b1010;
     parameter [0:0] RX_CM_BUF_PD = 1'b0;
     parameter integer RX_CM_SEL = 3;
-    parameter integer RX_CM_TRIM = 12;
-    parameter [7:0] RX_CTLE3_LPF = 8'b00000000;
+    parameter integer RX_CM_TRIM = 10;
+    parameter [0:0] RX_CTLE1_KHKL = 1'b0;
+    parameter [0:0] RX_CTLE2_KHKL = 1'b0;
+    parameter [0:0] RX_CTLE3_AGC = 1'b0;
     parameter integer RX_DATA_WIDTH = 20;
     parameter [5:0] RX_DDI_SEL = 6'b000000;
     parameter RX_DEFER_RESET_BUF_EN = "TRUE";
-    parameter [2:0] RX_DEGEN_CTRL = 3'b011;
-    parameter integer RX_DFELPM_CFG0 = 0;
-    parameter [0:0] RX_DFELPM_CFG1 = 1'b1;
+    parameter [2:0] RX_DEGEN_CTRL = 3'b010;
+    parameter integer RX_DFELPM_CFG0 = 6;
+    parameter [0:0] RX_DFELPM_CFG1 = 1'b0;
     parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1;
     parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00;
     parameter integer RX_DFE_AGC_CFG1 = 4;
     parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1;
-    parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4;
+    parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2;
     parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01;
-    parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4;
+    parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010;
     parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
     parameter RX_DISPERR_SEQ_MATCH = "TRUE";
     parameter [0:0] RX_DIV2_MODE_B = 1'b0;
     parameter [4:0] RX_DIVRESET_TIME = 5'b00001;
     parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0;
-    parameter [0:0] RX_EN_HI_LR = 1'b1;
+    parameter [0:0] RX_EN_HI_LR = 1'b0;
     parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000;
     parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000;
     parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0;
@@ -15511,7 +15528,6 @@ module GTHE4_CHANNEL (...);
     parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0;
     parameter integer RX_INT_DATAWIDTH = 1;
     parameter [0:0] RX_PMA_POWER_SAVE = 1'b0;
-    parameter [15:0] RX_PMA_RSV0 = 16'h0000;
     parameter real RX_PROGDIV_CFG = 0.0;
     parameter [15:0] RX_PROGDIV_RATE = 16'h0001;
     parameter [3:0] RX_RESLOAD_CTRL = 4'b0000;
@@ -15519,32 +15535,34 @@ module GTHE4_CHANNEL (...);
     parameter [2:0] RX_SAMPLE_PERIOD = 3'b101;
     parameter integer RX_SIG_VALID_DLY = 11;
     parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0;
-    parameter [3:0] RX_SUM_IREF_TUNE = 4'b1001;
-    parameter [3:0] RX_SUM_RESLOAD_CTRL = 4'b0000;
-    parameter [3:0] RX_SUM_VCMTUNE = 4'b1010;
+    parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000;
+    parameter [3:0] RX_SUM_VCMTUNE = 4'b1000;
     parameter [0:0] RX_SUM_VCM_OVWR = 1'b0;
     parameter [2:0] RX_SUM_VREF_TUNE = 3'b100;
     parameter [1:0] RX_TUNE_AFE_OS = 2'b00;
     parameter [2:0] RX_VREG_CTRL = 3'b101;
     parameter [0:0] RX_VREG_PDB = 1'b1;
     parameter [1:0] RX_WIDEMODE_CDR = 2'b01;
-    parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01;
-    parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01;
     parameter RX_XCLK_SEL = "RXDES";
     parameter [0:0] RX_XMODE_SEL = 1'b0;
-    parameter [0:0] SAMPLE_CLK_PHASE = 1'b0;
-    parameter [0:0] SAS_12G_MODE = 1'b0;
+    parameter integer SAS_MAX_COM = 64;
+    parameter integer SAS_MIN_COM = 36;
     parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
     parameter [2:0] SATA_BURST_VAL = 3'b100;
     parameter SATA_CPLL_CFG = "VCO_3000MHZ";
     parameter [2:0] SATA_EIDLE_VAL = 3'b100;
+    parameter integer SATA_MAX_BURST = 8;
+    parameter integer SATA_MAX_INIT = 21;
+    parameter integer SATA_MAX_WAKE = 7;
+    parameter integer SATA_MIN_BURST = 4;
+    parameter integer SATA_MIN_INIT = 12;
+    parameter integer SATA_MIN_WAKE = 4;
     parameter SHOW_REALIGN_COMMA = "TRUE";
-    parameter SIM_DEVICE = "ULTRASCALE_PLUS";
     parameter SIM_MODE = "FAST";
     parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
     parameter SIM_RESET_SPEEDUP = "TRUE";
-    parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z";
-    parameter [0:0] SRSTMODE = 1'b0;
+    parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0;
+    parameter integer SIM_VERSION = 2;
     parameter [1:0] TAPDLY_SET_TX = 2'h0;
     parameter [3:0] TEMPERATURE_PAR = 4'b0010;
     parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
@@ -15554,20 +15572,18 @@ module GTHE4_CHANNEL (...);
     parameter [7:0] TST_RSV1 = 8'h00;
     parameter TXBUF_EN = "TRUE";
     parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
-    parameter [15:0] TXDLY_CFG = 16'h0010;
+    parameter [15:0] TXDLY_CFG = 16'h001F;
     parameter [15:0] TXDLY_LCFG = 16'h0030;
-    parameter [3:0] TXDRVBIAS_N = 4'b1010;
     parameter TXFIFO_ADDR_CFG = "LOW";
     parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4;
     parameter TXGEARBOX_EN = "FALSE";
     parameter integer TXOUT_DIV = 4;
     parameter [4:0] TXPCSRESET_TIME = 5'b00001;
-    parameter [15:0] TXPHDLY_CFG0 = 16'h6020;
-    parameter [15:0] TXPHDLY_CFG1 = 16'h0002;
+    parameter [15:0] TXPHDLY_CFG0 = 16'h2020;
+    parameter [15:0] TXPHDLY_CFG1 = 16'h0001;
     parameter [15:0] TXPH_CFG = 16'h0123;
     parameter [15:0] TXPH_CFG2 = 16'h0000;
     parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
-    parameter [15:0] TXPI_CFG = 16'h0000;
     parameter [1:0] TXPI_CFG0 = 2'b00;
     parameter [1:0] TXPI_CFG1 = 2'b00;
     parameter [1:0] TXPI_CFG2 = 2'b00;
@@ -15577,29 +15593,30 @@ module GTHE4_CHANNEL (...);
     parameter [0:0] TXPI_GRAY_SEL = 1'b0;
     parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
     parameter [0:0] TXPI_LPM = 1'b0;
-    parameter [0:0] TXPI_PPM = 1'b0;
     parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
     parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
+    parameter [15:0] TXPI_RSV0 = 16'h0000;
     parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
     parameter [0:0] TXPI_VREFSEL = 1'b0;
     parameter [4:0] TXPMARESET_TIME = 5'b00001;
-    parameter [0:0] TXREFCLKDIV2_SEL = 1'b0;
     parameter [0:0] TXSYNC_MULTILANE = 1'b0;
     parameter [0:0] TXSYNC_OVRD = 1'b0;
     parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
     parameter integer TX_CLK25_DIV = 8;
     parameter [0:0] TX_CLKMUX_EN = 1'b1;
+    parameter [0:0] TX_CLKREG_PDB = 1'b0;
+    parameter [2:0] TX_CLKREG_SET = 3'b000;
     parameter integer TX_DATA_WIDTH = 20;
-    parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000;
+    parameter [5:0] TX_DCD_CFG = 6'b000010;
+    parameter [0:0] TX_DCD_EN = 1'b0;
     parameter [5:0] TX_DEEMPH0 = 6'b000000;
     parameter [5:0] TX_DEEMPH1 = 6'b000000;
-    parameter [5:0] TX_DEEMPH2 = 6'b000000;
-    parameter [5:0] TX_DEEMPH3 = 6'b000000;
     parameter [4:0] TX_DIVRESET_TIME = 5'b00001;
     parameter TX_DRIVE_MODE = "DIRECT";
     parameter integer TX_DRVMUX_CTRL = 2;
     parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
     parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
+    parameter [0:0] TX_EML_PHI_TUNE = 1'b0;
     parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0;
     parameter [0:0] TX_FIFO_BYP_EN = 1'b0;
     parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0;
@@ -15616,75 +15633,44 @@ module GTHE4_CHANNEL (...);
     parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
     parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
     parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
+    parameter [2:0] TX_MODE_SEL = 3'b000;
     parameter [15:0] TX_PHICAL_CFG0 = 16'h0000;
-    parameter [15:0] TX_PHICAL_CFG1 = 16'h003F;
+    parameter [15:0] TX_PHICAL_CFG1 = 16'h7E00;
     parameter [15:0] TX_PHICAL_CFG2 = 16'h0000;
     parameter integer TX_PI_BIASSET = 0;
-    parameter [1:0] TX_PI_IBIAS_MID = 2'b00;
+    parameter [15:0] TX_PI_CFG0 = 16'h0000;
+    parameter [15:0] TX_PI_CFG1 = 16'h0000;
+    parameter [0:0] TX_PI_DIV2_MODE_B = 1'b0;
+    parameter [0:0] TX_PI_SEL_QPLL0 = 1'b0;
+    parameter [0:0] TX_PI_SEL_QPLL1 = 1'b0;
     parameter [0:0] TX_PMADATA_OPT = 1'b0;
     parameter [0:0] TX_PMA_POWER_SAVE = 1'b0;
-    parameter [15:0] TX_PMA_RSV0 = 16'h0008;
     parameter integer TX_PREDRV_CTRL = 2;
     parameter TX_PROGCLK_SEL = "POSTPI";
     parameter real TX_PROGDIV_CFG = 0.0;
     parameter [15:0] TX_PROGDIV_RATE = 16'h0001;
-    parameter [0:0] TX_QPI_STATUS_EN = 1'b0;
     parameter [13:0] TX_RXDETECT_CFG = 14'h0032;
-    parameter integer TX_RXDETECT_REF = 3;
+    parameter integer TX_RXDETECT_REF = 4;
     parameter [2:0] TX_SAMPLE_PERIOD = 3'b101;
     parameter [0:0] TX_SARC_LPBK_ENB = 1'b0;
-    parameter [1:0] TX_SW_MEAS = 2'b00;
-    parameter [2:0] TX_VREG_CTRL = 3'b000;
-    parameter [0:0] TX_VREG_PDB = 1'b0;
-    parameter [1:0] TX_VREG_VREFSEL = 2'b00;
     parameter TX_XCLK_SEL = "TXOUT";
-    parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0;
-    parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111;
-    parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011;
-    parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0;
-    parameter [0:0] USB_EXT_CNTL = 1'b1;
-    parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011;
-    parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011;
-    parameter [8:0] USB_LFPSPING_BURST = 9'b000000101;
-    parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001;
-    parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100;
-    parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101;
-    parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011;
-    parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011;
-    parameter [3:0] USB_LFPS_TPERIOD = 4'b0011;
-    parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1;
-    parameter [0:0] USB_MODE = 1'b0;
-    parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0;
-    parameter integer USB_PING_SATA_MAX_INIT = 21;
-    parameter integer USB_PING_SATA_MIN_INIT = 12;
-    parameter integer USB_POLL_SATA_MAX_BURST = 8;
-    parameter integer USB_POLL_SATA_MIN_BURST = 4;
-    parameter [0:0] USB_RAW_ELEC = 1'b0;
-    parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1;
-    parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1;
-    parameter integer USB_U1_SATA_MAX_WAKE = 7;
-    parameter integer USB_U1_SATA_MIN_WAKE = 4;
-    parameter integer USB_U2_SAS_MAX_COM = 64;
-    parameter integer USB_U2_SAS_MIN_COM = 36;
     parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
-    parameter [0:0] Y_ALL_MODE = 1'b0;
-    output BUFGTCE;
+    output [2:0] BUFGTCE;
     output [2:0] BUFGTCEMASK;
     output [8:0] BUFGTDIV;
-    output BUFGTRESET;
+    output [2:0] BUFGTRESET;
     output [2:0] BUFGTRSTMASK;
     output CPLLFBCLKLOST;
     output CPLLLOCK;
     output CPLLREFCLKLOST;
-    output [15:0] DMONITOROUT;
-    output DMONITOROUTCLK;
+    output [16:0] DMONITOROUT;
     output [15:0] DRPDO;
     output DRPRDY;
     output EYESCANDATAERROR;
-    output GTHTXN;
-    output GTHTXP;
     output GTPOWERGOOD;
     output GTREFCLKMONITOR;
+    output GTYTXN;
+    output GTYTXP;
     output PCIERATEGEN3;
     output PCIERATEIDLE;
     output [1:0] PCIERATEQPLLPD;
@@ -15695,8 +15681,7 @@ module GTHE4_CHANNEL (...);
     output PCIEUSERRATESTART;
     output [15:0] PCSRSVDOUT;
     output PHYSTATUS;
-    output [15:0] PINRSRVDAS;
-    output POWERPRESENT;
+    output [7:0] PINRSRVDAS;
     output RESETEXCEPTION;
     output [2:0] RXBUFSTATUS;
     output RXBYTEISALIGNED;
@@ -15724,10 +15709,7 @@ module GTHE4_CHANNEL (...);
     output RXELECIDLE;
     output [5:0] RXHEADER;
     output [1:0] RXHEADERVALID;
-    output RXLFPSTRESETDET;
-    output RXLFPSU2LPEXITDET;
-    output RXLFPSU3WAKEDET;
-    output [7:0] RXMONITOROUT;
+    output [6:0] RXMONITOROUT;
     output RXOSINTDONE;
     output RXOSINTSTARTED;
     output RXOSINTSTROBEDONE;
@@ -15741,8 +15723,6 @@ module GTHE4_CHANNEL (...);
     output RXPRBSERR;
     output RXPRBSLOCKED;
     output RXPRGDIVRESETDONE;
-    output RXQPISENN;
-    output RXQPISENP;
     output RXRATEDONE;
     output RXRECCLKOUT;
     output RXRESETDONE;
@@ -15766,8 +15746,6 @@ module GTHE4_CHANNEL (...);
     output TXPHINITDONE;
     output TXPMARESETDONE;
     output TXPRGDIVRESETDONE;
-    output TXQPISENN;
-    output TXQPISENP;
     output TXRATEDONE;
     output TXRESETDONE;
     output TXSYNCDONE;
@@ -15778,7 +15756,6 @@ module GTHE4_CHANNEL (...);
     input CFGRESET;
     input CLKRSVD0;
     input CLKRSVD1;
-    input CPLLFREQLOCK;
     input CPLLLOCKDETCLK;
     input CPLLLOCKEN;
     input CPLLPD;
@@ -15790,64 +15767,65 @@ module GTHE4_CHANNEL (...);
     input DRPCLK;
     input [15:0] DRPDI;
     input DRPEN;
-    input DRPRST;
     input DRPWE;
+    input ELPCALDVORWREN;
+    input ELPCALPAORWREN;
+    input EVODDPHICALDONE;
+    input EVODDPHICALSTART;
+    input EVODDPHIDRDEN;
+    input EVODDPHIDWREN;
+    input EVODDPHIXRDEN;
+    input EVODDPHIXWREN;
+    input EYESCANMODE;
     input EYESCANRESET;
     input EYESCANTRIGGER;
-    input FREQOS;
     input GTGREFCLK;
-    input GTHRXN;
-    input GTHRXP;
     input GTNORTHREFCLK0;
     input GTNORTHREFCLK1;
     input GTREFCLK0;
     input GTREFCLK1;
+    input GTRESETSEL;
     input [15:0] GTRSVD;
     input GTRXRESET;
-    input GTRXRESETSEL;
     input GTSOUTHREFCLK0;
     input GTSOUTHREFCLK1;
     input GTTXRESET;
-    input GTTXRESETSEL;
-    input INCPCTRL;
+    input GTYRXN;
+    input GTYRXP;
     input [2:0] LOOPBACK;
+    input [15:0] LOOPRSVD;
+    input LPBKRXTXSEREN;
+    input LPBKTXRXSEREN;
     input PCIEEQRXEQADAPTDONE;
     input PCIERSTIDLE;
     input PCIERSTTXSYNCSTART;
     input PCIEUSERRATEDONE;
     input [15:0] PCSRSVDIN;
+    input [4:0] PCSRSVDIN2;
+    input [4:0] PMARSVDIN;
     input QPLL0CLK;
-    input QPLL0FREQLOCK;
     input QPLL0REFCLK;
     input QPLL1CLK;
-    input QPLL1FREQLOCK;
     input QPLL1REFCLK;
     input RESETOVRD;
+    input RSTCLKENTX;
     input RX8B10BEN;
-    input RXAFECFOKEN;
     input RXBUFRESET;
     input RXCDRFREQRESET;
     input RXCDRHOLD;
     input RXCDROVRDEN;
     input RXCDRRESET;
+    input RXCDRRESETRSV;
     input RXCHBONDEN;
     input [4:0] RXCHBONDI;
     input [2:0] RXCHBONDLEVEL;
     input RXCHBONDMASTER;
     input RXCHBONDSLAVE;
     input RXCKCALRESET;
-    input [6:0] RXCKCALSTART;
     input RXCOMMADETEN;
-    input [1:0] RXDFEAGCCTRL;
+    input RXDCCFORCESTART;
     input RXDFEAGCHOLD;
     input RXDFEAGCOVRDEN;
-    input [3:0] RXDFECFOKFCNUM;
-    input RXDFECFOKFEN;
-    input RXDFECFOKFPULSE;
-    input RXDFECFOKHOLD;
-    input RXDFECFOKOVREN;
-    input RXDFEKHHOLD;
-    input RXDFEKHOVRDEN;
     input RXDFELFHOLD;
     input RXDFELFOVRDEN;
     input RXDFELPMRESET;
@@ -15883,13 +15861,13 @@ module GTHE4_CHANNEL (...);
     input RXDFEUTOVRDEN;
     input RXDFEVPHOLD;
     input RXDFEVPOVRDEN;
+    input RXDFEVSEN;
     input RXDFEXYDEN;
     input RXDLYBYPASS;
     input RXDLYEN;
     input RXDLYOVRDEN;
     input RXDLYSRESET;
     input [1:0] RXELECIDLEMODE;
-    input RXEQTRAINING;
     input RXGEARBOXSLIP;
     input RXLATCLK;
     input RXLPMEN;
@@ -15906,6 +15884,12 @@ module GTHE4_CHANNEL (...);
     input RXOOBRESET;
     input RXOSCALRESET;
     input RXOSHOLD;
+    input [3:0] RXOSINTCFG;
+    input RXOSINTEN;
+    input RXOSINTHOLD;
+    input RXOSINTOVRDEN;
+    input RXOSINTSTROBE;
+    input RXOSINTTESTOVRDEN;
     input RXOSOVRDEN;
     input [2:0] RXOUTCLKSEL;
     input RXPCOMMAALIGNEN;
@@ -15922,7 +15906,6 @@ module GTHE4_CHANNEL (...);
     input RXPRBSCNTRESET;
     input [3:0] RXPRBSSEL;
     input RXPROGDIVRESET;
-    input RXQPIEN;
     input [2:0] RXRATE;
     input RXRATEMODE;
     input RXSLIDE;
@@ -15932,7 +15915,6 @@ module GTHE4_CHANNEL (...);
     input RXSYNCIN;
     input RXSYNCMODE;
     input [1:0] RXSYSCLKSEL;
-    input RXTERMINATION;
     input RXUSERRDY;
     input RXUSRCLK;
     input RXUSRCLK2;
@@ -15940,6 +15922,7 @@ module GTHE4_CHANNEL (...);
     input [19:0] TSTIN;
     input [7:0] TX8B10BBYPASS;
     input TX8B10BEN;
+    input [2:0] TXBUFDIFFCTRL;
     input TXCOMINIT;
     input TXCOMSAS;
     input TXCOMWAKE;
@@ -15950,9 +15933,10 @@ module GTHE4_CHANNEL (...);
     input [7:0] TXDATAEXTENDRSVD;
     input TXDCCFORCESTART;
     input TXDCCRESET;
-    input [1:0] TXDEEMPH;
+    input TXDEEMPH;
     input TXDETECTRX;
     input [4:0] TXDIFFCTRL;
+    input TXDIFFPD;
     input TXDLYBYPASS;
     input TXDLYEN;
     input TXDLYHOLD;
@@ -15960,17 +15944,12 @@ module GTHE4_CHANNEL (...);
     input TXDLYSRESET;
     input TXDLYUPDOWN;
     input TXELECIDLE;
+    input TXELFORCESTART;
     input [5:0] TXHEADER;
     input TXINHIBIT;
     input TXLATCLK;
-    input TXLFPSTRESET;
-    input TXLFPSU2LPEXIT;
-    input TXLFPSU3WAKE;
     input [6:0] TXMAINCURSOR;
     input [2:0] TXMARGIN;
-    input TXMUXDCDEXHOLD;
-    input TXMUXDCDORWREN;
-    input TXONESZEROS;
     input [2:0] TXOUTCLKSEL;
     input TXPCSRESET;
     input [1:0] TXPD;
@@ -15996,8 +15975,6 @@ module GTHE4_CHANNEL (...);
     input [3:0] TXPRBSSEL;
     input [4:0] TXPRECURSOR;
     input TXPROGDIVRESET;
-    input TXQPIBIASEN;
-    input TXQPIWEAKPUP;
     input [2:0] TXRATE;
     input TXRATEMODE;
     input [6:0] TXSEQUENCE;
@@ -16011,34 +15988,28 @@ module GTHE4_CHANNEL (...);
     input TXUSRCLK2;
 endmodule
 
-module GTHE4_COMMON (...);
-    parameter [0:0] AEN_QPLL0_FBDIV = 1'b1;
-    parameter [0:0] AEN_QPLL1_FBDIV = 1'b1;
-    parameter [0:0] AEN_SDM0TOGGLE = 1'b0;
-    parameter [0:0] AEN_SDM1TOGGLE = 1'b0;
-    parameter [0:0] A_SDM0TOGGLE = 1'b0;
-    parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000;
-    parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000;
-    parameter [0:0] A_SDM1TOGGLE = 1'b0;
+module GTYE3_COMMON (...);
+    parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000;
+    parameter [8:0] A_SDM1DATA1_1 = 9'b000000000;
     parameter [15:0] BIAS_CFG0 = 16'h0000;
     parameter [15:0] BIAS_CFG1 = 16'h0000;
     parameter [15:0] BIAS_CFG2 = 16'h0000;
     parameter [15:0] BIAS_CFG3 = 16'h0000;
     parameter [15:0] BIAS_CFG4 = 16'h0000;
-    parameter [15:0] BIAS_CFG_RSVD = 16'h0000;
+    parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000;
     parameter [15:0] COMMON_CFG0 = 16'h0000;
     parameter [15:0] COMMON_CFG1 = 16'h0000;
-    parameter [15:0] POR_CFG = 16'h0000;
-    parameter [15:0] PPF0_CFG = 16'h0F00;
-    parameter [15:0] PPF1_CFG = 16'h0F00;
+    parameter [15:0] POR_CFG = 16'h0004;
+    parameter [15:0] PPF0_CFG = 16'h0FFF;
+    parameter [15:0] PPF1_CFG = 16'h0FFF;
     parameter QPLL0CLKOUT_RATE = "FULL";
-    parameter [15:0] QPLL0_CFG0 = 16'h391C;
+    parameter [15:0] QPLL0_CFG0 = 16'h301C;
     parameter [15:0] QPLL0_CFG1 = 16'h0000;
     parameter [15:0] QPLL0_CFG1_G3 = 16'h0020;
-    parameter [15:0] QPLL0_CFG2 = 16'h0F80;
-    parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80;
+    parameter [15:0] QPLL0_CFG2 = 16'h0780;
+    parameter [15:0] QPLL0_CFG2_G3 = 16'h0780;
     parameter [15:0] QPLL0_CFG3 = 16'h0120;
-    parameter [15:0] QPLL0_CFG4 = 16'h0002;
+    parameter [15:0] QPLL0_CFG4 = 16'h0021;
     parameter [9:0] QPLL0_CP = 10'b0000011111;
     parameter [9:0] QPLL0_CP_G3 = 10'b0000011111;
     parameter integer QPLL0_FBDIV = 66;
@@ -16047,22 +16018,20 @@ module GTHE4_COMMON (...);
     parameter [7:0] QPLL0_INIT_CFG1 = 8'h00;
     parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8;
     parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8;
-    parameter [9:0] QPLL0_LPF = 10'b1011111111;
+    parameter [9:0] QPLL0_LPF = 10'b1111111111;
     parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111;
-    parameter [0:0] QPLL0_PCI_EN = 1'b0;
-    parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0;
-    parameter integer QPLL0_REFCLK_DIV = 1;
+    parameter integer QPLL0_REFCLK_DIV = 2;
     parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040;
     parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000;
     parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000;
     parameter QPLL1CLKOUT_RATE = "FULL";
-    parameter [15:0] QPLL1_CFG0 = 16'h691C;
-    parameter [15:0] QPLL1_CFG1 = 16'h0020;
+    parameter [15:0] QPLL1_CFG0 = 16'h301C;
+    parameter [15:0] QPLL1_CFG1 = 16'h0000;
     parameter [15:0] QPLL1_CFG1_G3 = 16'h0020;
-    parameter [15:0] QPLL1_CFG2 = 16'h0F80;
-    parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80;
+    parameter [15:0] QPLL1_CFG2 = 16'h0780;
+    parameter [15:0] QPLL1_CFG2_G3 = 16'h0780;
     parameter [15:0] QPLL1_CFG3 = 16'h0120;
-    parameter [15:0] QPLL1_CFG4 = 16'h0002;
+    parameter [15:0] QPLL1_CFG4 = 16'h0021;
     parameter [9:0] QPLL1_CP = 10'b0000011111;
     parameter [9:0] QPLL1_CP_G3 = 10'b0000011111;
     parameter integer QPLL1_FBDIV = 66;
@@ -16071,12 +16040,10 @@ module GTHE4_COMMON (...);
     parameter [7:0] QPLL1_INIT_CFG1 = 8'h00;
     parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8;
     parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8;
-    parameter [9:0] QPLL1_LPF = 10'b1011111111;
+    parameter [9:0] QPLL1_LPF = 10'b1111111111;
     parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111;
-    parameter [0:0] QPLL1_PCI_EN = 1'b0;
-    parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0;
-    parameter integer QPLL1_REFCLK_DIV = 1;
-    parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000;
+    parameter integer QPLL1_REFCLK_DIV = 2;
+    parameter [15:0] QPLL1_SDM_CFG0 = 16'h0040;
     parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000;
     parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000;
     parameter [15:0] RSVD_ATTR0 = 16'h0000;
@@ -16085,15 +16052,15 @@ module GTHE4_COMMON (...);
     parameter [15:0] RSVD_ATTR3 = 16'h0000;
     parameter [1:0] RXRECCLKOUT0_SEL = 2'b00;
     parameter [1:0] RXRECCLKOUT1_SEL = 2'b00;
-    parameter [0:0] SARC_ENB = 1'b0;
+    parameter [0:0] SARC_EN = 1'b1;
     parameter [0:0] SARC_SEL = 1'b0;
     parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000;
     parameter [8:0] SDM0INITSEED0_1 = 9'b000000000;
     parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000;
     parameter [8:0] SDM1INITSEED0_1 = 9'b000000000;
-    parameter SIM_DEVICE = "ULTRASCALE_PLUS";
     parameter SIM_MODE = "FAST";
     parameter SIM_RESET_SPEEDUP = "TRUE";
+    parameter integer SIM_VERSION = 2;
     output [15:0] DRPDO;
     output DRPRDY;
     output [7:0] PMARSVDOUT0;
@@ -16112,20 +16079,18 @@ module GTHE4_COMMON (...);
     output [7:0] QPLLDMONITOR1;
     output REFCLKOUTMONITOR0;
     output REFCLKOUTMONITOR1;
-    output [1:0] RXRECCLK0SEL;
-    output [1:0] RXRECCLK1SEL;
+    output [1:0] RXRECCLK0_SEL;
+    output [1:0] RXRECCLK1_SEL;
     output [3:0] SDM0FINALOUT;
     output [14:0] SDM0TESTDATA;
     output [3:0] SDM1FINALOUT;
     output [14:0] SDM1TESTDATA;
-    output [9:0] TCONGPO;
-    output TCONRSVDOUT0;
     input BGBYPASSB;
     input BGMONITORENB;
     input BGPDB;
     input [4:0] BGRCALOVRD;
     input BGRCALOVRDENB;
-    input [15:0] DRPADDR;
+    input [9:0] DRPADDR;
     input DRPCLK;
     input [15:0] DRPDI;
     input DRPEN;
@@ -16144,21 +16109,15 @@ module GTHE4_COMMON (...);
     input GTSOUTHREFCLK01;
     input GTSOUTHREFCLK10;
     input GTSOUTHREFCLK11;
-    input [2:0] PCIERATEQPLL0;
-    input [2:0] PCIERATEQPLL1;
     input [7:0] PMARSVD0;
     input [7:0] PMARSVD1;
     input QPLL0CLKRSVD0;
-    input QPLL0CLKRSVD1;
-    input [7:0] QPLL0FBDIV;
     input QPLL0LOCKDETCLK;
     input QPLL0LOCKEN;
     input QPLL0PD;
     input [2:0] QPLL0REFCLKSEL;
     input QPLL0RESET;
     input QPLL1CLKRSVD0;
-    input QPLL1CLKRSVD1;
-    input [7:0] QPLL1FBDIV;
     input QPLL1LOCKDETCLK;
     input QPLL1LOCKEN;
     input QPLL1PD;
@@ -16171,25 +16130,55 @@ module GTHE4_COMMON (...);
     input RCALENB;
     input [24:0] SDM0DATA;
     input SDM0RESET;
-    input SDM0TOGGLE;
     input [1:0] SDM0WIDTH;
     input [24:0] SDM1DATA;
     input SDM1RESET;
-    input SDM1TOGGLE;
     input [1:0] SDM1WIDTH;
-    input [9:0] TCONGPI;
-    input TCONPOWERUP;
-    input [1:0] TCONRESET;
-    input [1:0] TCONRSVDIN1;
 endmodule
 
-module GTYE3_CHANNEL (...);
+module IBUFDS_GTE3 (...);
+    parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
+    parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00;
+    parameter [1:0] REFCLK_ICNTL_RX = 2'b00;
+    output O;
+    output ODIV2;
+    input CEB;
+    (* iopad_external_pin *)
+    input I;
+    (* iopad_external_pin *)
+    input IB;
+endmodule
+
+module OBUFDS_GTE3 (...);
+    parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
+    parameter [4:0] REFCLK_ICNTL_TX = 5'b00000;
+    (* iopad_external_pin *)
+    output O;
+    (* iopad_external_pin *)
+    output OB;
+    input CEB;
+    input I;
+endmodule
+
+module OBUFDS_GTE3_ADV (...);
+    parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
+    parameter [4:0] REFCLK_ICNTL_TX = 5'b00000;
+    (* iopad_external_pin *)
+    output O;
+    (* iopad_external_pin *)
+    output OB;
+    input CEB;
+    input [3:0] I;
+    input [1:0] RXRECCLK_SEL;
+endmodule
+
+module GTHE4_CHANNEL (...);
     parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
     parameter [0:0] ACJTAG_MODE = 1'b0;
     parameter [0:0] ACJTAG_RESET = 1'b0;
     parameter [15:0] ADAPT_CFG0 = 16'h9200;
     parameter [15:0] ADAPT_CFG1 = 16'h801C;
-    parameter [15:0] ADAPT_CFG2 = 16'b0000000000000000;
+    parameter [15:0] ADAPT_CFG2 = 16'h0000;
     parameter ALIGN_COMMA_DOUBLE = "FALSE";
     parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
     parameter integer ALIGN_COMMA_WORD = 1;
@@ -16197,14 +16186,15 @@ module GTYE3_CHANNEL (...);
     parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
     parameter ALIGN_PCOMMA_DET = "TRUE";
     parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
-    parameter [0:0] AUTO_BW_SEL_BYPASS = 1'b0;
     parameter [0:0] A_RXOSCALRESET = 1'b0;
     parameter [0:0] A_RXPROGDIVRESET = 1'b0;
+    parameter [0:0] A_RXTERMINATION = 1'b1;
     parameter [4:0] A_TXDIFFCTRL = 5'b01100;
     parameter [0:0] A_TXPROGDIVRESET = 1'b0;
     parameter [0:0] CAPBYPASS_FORCE = 1'b0;
     parameter CBCC_DATA_SOURCE_SEL = "DECODED";
     parameter [0:0] CDR_SWAP_MODE_EN = 1'b0;
+    parameter [0:0] CFOK_PWRSVE_EN = 1'b1;
     parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
     parameter integer CHAN_BOND_MAX_SKEW = 7;
     parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
@@ -16219,7 +16209,7 @@ module GTYE3_CHANNEL (...);
     parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
     parameter CHAN_BOND_SEQ_2_USE = "FALSE";
     parameter integer CHAN_BOND_SEQ_LEN = 2;
-    parameter [15:0] CH_HSPMUX = 16'h0000;
+    parameter [15:0] CH_HSPMUX = 16'h2424;
     parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000;
     parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000;
     parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000;
@@ -16229,7 +16219,7 @@ module GTYE3_CHANNEL (...);
     parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000;
     parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000;
     parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000;
-    parameter [15:0] CKCAL_RSVD0 = 16'h0000;
+    parameter [15:0] CKCAL_RSVD0 = 16'h4000;
     parameter [15:0] CKCAL_RSVD1 = 16'h0000;
     parameter CLK_CORRECT_USE = "TRUE";
     parameter CLK_COR_KEEP_IDLE = "FALSE";
@@ -16249,14 +16239,13 @@ module GTYE3_CHANNEL (...);
     parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
     parameter CLK_COR_SEQ_2_USE = "FALSE";
     parameter integer CLK_COR_SEQ_LEN = 2;
-    parameter [15:0] CPLL_CFG0 = 16'h20F8;
-    parameter [15:0] CPLL_CFG1 = 16'hA494;
-    parameter [15:0] CPLL_CFG2 = 16'hF001;
-    parameter [5:0] CPLL_CFG3 = 6'h00;
+    parameter [15:0] CPLL_CFG0 = 16'h01FA;
+    parameter [15:0] CPLL_CFG1 = 16'h24A9;
+    parameter [15:0] CPLL_CFG2 = 16'h6807;
+    parameter [15:0] CPLL_CFG3 = 16'h0000;
     parameter integer CPLL_FBDIV = 4;
     parameter integer CPLL_FBDIV_45 = 4;
     parameter [15:0] CPLL_INIT_CFG0 = 16'h001E;
-    parameter [7:0] CPLL_INIT_CFG1 = 8'h00;
     parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
     parameter integer CPLL_REFCLK_DIV = 1;
     parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000;
@@ -16266,16 +16255,14 @@ module GTYE3_CHANNEL (...);
     parameter DEC_MCOMMA_DETECT = "TRUE";
     parameter DEC_PCOMMA_DETECT = "TRUE";
     parameter DEC_VALID_COMMA_ONLY = "TRUE";
-    parameter [0:0] DFE_D_X_REL_POS = 1'b0;
-    parameter [0:0] DFE_VCM_COMP_EN = 1'b0;
+    parameter [0:0] DELAY_ELEC = 1'b0;
     parameter [9:0] DMONITOR_CFG0 = 10'h000;
     parameter [7:0] DMONITOR_CFG1 = 8'h00;
     parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
     parameter [5:0] ES_CONTROL = 6'b000000;
     parameter ES_ERRDET_EN = "FALSE";
     parameter ES_EYE_SCAN_EN = "FALSE";
-    parameter [11:0] ES_HORZ_OFFSET = 12'h000;
-    parameter [9:0] ES_PMA_CFG = 10'b0000000000;
+    parameter [11:0] ES_HORZ_OFFSET = 12'h800;
     parameter [4:0] ES_PRESCALE = 5'b00000;
     parameter [15:0] ES_QUALIFIER0 = 16'h0000;
     parameter [15:0] ES_QUALIFIER1 = 16'h0000;
@@ -16307,32 +16294,19 @@ module GTYE3_CHANNEL (...);
     parameter [15:0] ES_SDATA_MASK7 = 16'h0000;
     parameter [15:0] ES_SDATA_MASK8 = 16'h0000;
     parameter [15:0] ES_SDATA_MASK9 = 16'h0000;
-    parameter [10:0] EVODD_PHI_CFG = 11'b00000000000;
     parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0;
     parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
     parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
     parameter FTS_LANE_DESKEW_EN = "FALSE";
     parameter [4:0] GEARBOX_MODE = 5'b00000;
-    parameter [0:0] GM_BIAS_SELECT = 1'b0;
     parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0;
     parameter [0:0] LOCAL_MASTER = 1'b0;
-    parameter [15:0] LOOP0_CFG = 16'h0000;
-    parameter [15:0] LOOP10_CFG = 16'h0000;
-    parameter [15:0] LOOP11_CFG = 16'h0000;
-    parameter [15:0] LOOP12_CFG = 16'h0000;
-    parameter [15:0] LOOP13_CFG = 16'h0000;
-    parameter [15:0] LOOP1_CFG = 16'h0000;
-    parameter [15:0] LOOP2_CFG = 16'h0000;
-    parameter [15:0] LOOP3_CFG = 16'h0000;
-    parameter [15:0] LOOP4_CFG = 16'h0000;
-    parameter [15:0] LOOP5_CFG = 16'h0000;
-    parameter [15:0] LOOP6_CFG = 16'h0000;
-    parameter [15:0] LOOP7_CFG = 16'h0000;
-    parameter [15:0] LOOP8_CFG = 16'h0000;
-    parameter [15:0] LOOP9_CFG = 16'h0000;
     parameter [2:0] LPBK_BIAS_CTRL = 3'b000;
     parameter [0:0] LPBK_EN_RCAL_B = 1'b0;
     parameter [3:0] LPBK_EXT_RCAL = 4'b0000;
+    parameter [2:0] LPBK_IND_CTRL0 = 3'b000;
+    parameter [2:0] LPBK_IND_CTRL1 = 3'b000;
+    parameter [2:0] LPBK_IND_CTRL2 = 3'b000;
     parameter [3:0] LPBK_RG_CTRL = 4'b0000;
     parameter [1:0] OOBDIVCTL = 2'b00;
     parameter [0:0] OOB_PWRUP = 1'b0;
@@ -16345,25 +16319,32 @@ module GTYE3_CHANNEL (...);
     parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000;
     parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0;
     parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0;
+    parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000;
+    parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000;
+    parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000;
+    parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100;
+    parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000;
     parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000;
-    parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000;
+    parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0;
+    parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0;
+    parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0;
+    parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000;
     parameter [15:0] PCIE_RXPMA_CFG = 16'h0000;
     parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000;
     parameter [15:0] PCIE_TXPMA_CFG = 16'h0000;
     parameter PCS_PCIE_EN = "FALSE";
     parameter [15:0] PCS_RSVD0 = 16'b0000000000000000;
-    parameter [2:0] PCS_RSVD1 = 3'b000;
     parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
     parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
     parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
-    parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0;
-    parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0;
-    parameter [15:0] PMA_RSV0 = 16'h0000;
-    parameter [15:0] PMA_RSV1 = 16'h0000;
     parameter integer PREIQ_FREQ_BST = 0;
     parameter [2:0] PROCESS_PAR = 3'b010;
     parameter [0:0] RATE_SW_USE_DRP = 1'b0;
+    parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0;
+    parameter [0:0] RCLK_SIPO_INV_EN = 1'b0;
     parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0;
+    parameter [2:0] RTX_BUF_CML_CTRL = 3'b010;
+    parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00;
     parameter [4:0] RXBUFRESET_TIME = 5'b00001;
     parameter RXBUF_ADDR_MODE = "FULL";
     parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
@@ -16378,37 +16359,48 @@ module GTYE3_CHANNEL (...);
     parameter integer RXBUF_THRESH_UNDFLW = 4;
     parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
     parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
-    parameter [15:0] RXCDR_CFG0 = 16'h0000;
-    parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000;
-    parameter [15:0] RXCDR_CFG1 = 16'h0300;
-    parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0300;
-    parameter [15:0] RXCDR_CFG2 = 16'h0060;
-    parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0060;
-    parameter [15:0] RXCDR_CFG3 = 16'h0000;
-    parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000;
-    parameter [15:0] RXCDR_CFG4 = 16'h0002;
-    parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0002;
-    parameter [15:0] RXCDR_CFG5 = 16'h0000;
-    parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000;
+    parameter [15:0] RXCDR_CFG0 = 16'h0003;
+    parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003;
+    parameter [15:0] RXCDR_CFG1 = 16'h0000;
+    parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000;
+    parameter [15:0] RXCDR_CFG2 = 16'h0164;
+    parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164;
+    parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034;
+    parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034;
+    parameter [15:0] RXCDR_CFG3 = 16'h0024;
+    parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24;
+    parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024;
+    parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024;
+    parameter [15:0] RXCDR_CFG4 = 16'h5CF6;
+    parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6;
+    parameter [15:0] RXCDR_CFG5 = 16'hB46B;
+    parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B;
     parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
     parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
-    parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0001;
-    parameter [15:0] RXCDR_LOCK_CFG1 = 16'h0000;
+    parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040;
+    parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000;
     parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000;
     parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000;
+    parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000;
     parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
-    parameter [1:0] RXCFOKDONE_SRC = 2'b00;
-    parameter [15:0] RXCFOK_CFG0 = 16'h3E00;
-    parameter [15:0] RXCFOK_CFG1 = 16'h0042;
+    parameter [15:0] RXCFOK_CFG0 = 16'h0000;
+    parameter [15:0] RXCFOK_CFG1 = 16'h0002;
     parameter [15:0] RXCFOK_CFG2 = 16'h002D;
+    parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000;
+    parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000;
+    parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000;
+    parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000;
+    parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000;
+    parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000;
+    parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000;
     parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
     parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000;
     parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022;
     parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100;
-    parameter [15:0] RXDFE_CFG0 = 16'h4C00;
+    parameter [15:0] RXDFE_CFG0 = 16'h4000;
     parameter [15:0] RXDFE_CFG1 = 16'h0000;
-    parameter [15:0] RXDFE_GC_CFG0 = 16'h1E00;
-    parameter [15:0] RXDFE_GC_CFG1 = 16'h1900;
+    parameter [15:0] RXDFE_GC_CFG0 = 16'h0000;
+    parameter [15:0] RXDFE_GC_CFG1 = 16'h0000;
     parameter [15:0] RXDFE_GC_CFG2 = 16'h0000;
     parameter [15:0] RXDFE_H2_CFG0 = 16'h0000;
     parameter [15:0] RXDFE_H2_CFG1 = 16'h0002;
@@ -16438,26 +16430,31 @@ module GTYE3_CHANNEL (...);
     parameter [15:0] RXDFE_HE_CFG1 = 16'h0002;
     parameter [15:0] RXDFE_HF_CFG0 = 16'h0000;
     parameter [15:0] RXDFE_HF_CFG1 = 16'h0002;
+    parameter [15:0] RXDFE_KH_CFG0 = 16'h0000;
+    parameter [15:0] RXDFE_KH_CFG1 = 16'h0000;
+    parameter [15:0] RXDFE_KH_CFG2 = 16'h0000;
+    parameter [15:0] RXDFE_KH_CFG3 = 16'h0000;
     parameter [15:0] RXDFE_OS_CFG0 = 16'h0000;
-    parameter [15:0] RXDFE_OS_CFG1 = 16'h0200;
+    parameter [15:0] RXDFE_OS_CFG1 = 16'h0002;
     parameter [0:0] RXDFE_PWR_SAVING = 1'b0;
     parameter [15:0] RXDFE_UT_CFG0 = 16'h0000;
     parameter [15:0] RXDFE_UT_CFG1 = 16'h0002;
+    parameter [15:0] RXDFE_UT_CFG2 = 16'h0000;
     parameter [15:0] RXDFE_VP_CFG0 = 16'h0000;
     parameter [15:0] RXDFE_VP_CFG1 = 16'h0022;
-    parameter [15:0] RXDLY_CFG = 16'h001F;
+    parameter [15:0] RXDLY_CFG = 16'h0010;
     parameter [15:0] RXDLY_LCFG = 16'h0030;
     parameter RXELECIDLE_CFG = "SIGCFG_4";
     parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4;
     parameter RXGEARBOX_EN = "FALSE";
     parameter [4:0] RXISCANRESET_TIME = 5'b00001;
     parameter [15:0] RXLPM_CFG = 16'h0000;
-    parameter [15:0] RXLPM_GC_CFG = 16'h0200;
+    parameter [15:0] RXLPM_GC_CFG = 16'h1000;
     parameter [15:0] RXLPM_KH_CFG0 = 16'h0000;
     parameter [15:0] RXLPM_KH_CFG1 = 16'h0002;
-    parameter [15:0] RXLPM_OS_CFG0 = 16'h0400;
+    parameter [15:0] RXLPM_OS_CFG0 = 16'h0000;
     parameter [15:0] RXLPM_OS_CFG1 = 16'h0000;
-    parameter [8:0] RXOOB_CFG = 9'b000000110;
+    parameter [8:0] RXOOB_CFG = 9'b000110000;
     parameter RXOOB_CLK_CFG = "PMA";
     parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
     parameter integer RXOUT_DIV = 4;
@@ -16468,9 +16465,9 @@ module GTYE3_CHANNEL (...);
     parameter [15:0] RXPHSLIP_CFG = 16'h9933;
     parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
     parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0;
-    parameter [15:0] RXPI_CFG = 16'h0100;
+    parameter [15:0] RXPI_CFG0 = 16'h0002;
+    parameter [15:0] RXPI_CFG1 = 16'b0000000000000000;
     parameter [0:0] RXPI_LPM = 1'b0;
-    parameter [15:0] RXPI_RSV0 = 16'h0000;
     parameter [1:0] RXPI_SEL_LC = 2'b00;
     parameter [1:0] RXPI_STARTCODE = 2'b00;
     parameter [0:0] RXPI_VREFSEL = 1'b0;
@@ -16478,13 +16475,14 @@ module GTYE3_CHANNEL (...);
     parameter [4:0] RXPMARESET_TIME = 5'b00001;
     parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
     parameter integer RXPRBS_LINKACQ_CNT = 15;
+    parameter [0:0] RXREFCLKDIV2_SEL = 1'b0;
     parameter integer RXSLIDE_AUTO_WAIT = 7;
     parameter RXSLIDE_MODE = "OFF";
     parameter [0:0] RXSYNC_MULTILANE = 1'b0;
     parameter [0:0] RXSYNC_OVRD = 1'b0;
     parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
     parameter [0:0] RX_AFE_CM_EN = 1'b0;
-    parameter [15:0] RX_BIAS_CFG0 = 16'h1534;
+    parameter [15:0] RX_BIAS_CFG0 = 16'h12B0;
     parameter [5:0] RX_BUFFER_CFG = 6'b000000;
     parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0;
     parameter integer RX_CLK25_DIV = 8;
@@ -16493,29 +16491,27 @@ module GTYE3_CHANNEL (...);
     parameter [3:0] RX_CM_BUF_CFG = 4'b1010;
     parameter [0:0] RX_CM_BUF_PD = 1'b0;
     parameter integer RX_CM_SEL = 3;
-    parameter integer RX_CM_TRIM = 10;
-    parameter [0:0] RX_CTLE1_KHKL = 1'b0;
-    parameter [0:0] RX_CTLE2_KHKL = 1'b0;
-    parameter [0:0] RX_CTLE3_AGC = 1'b0;
+    parameter integer RX_CM_TRIM = 12;
+    parameter [7:0] RX_CTLE3_LPF = 8'b00000000;
     parameter integer RX_DATA_WIDTH = 20;
     parameter [5:0] RX_DDI_SEL = 6'b000000;
     parameter RX_DEFER_RESET_BUF_EN = "TRUE";
-    parameter [2:0] RX_DEGEN_CTRL = 3'b010;
-    parameter integer RX_DFELPM_CFG0 = 6;
-    parameter [0:0] RX_DFELPM_CFG1 = 1'b0;
+    parameter [2:0] RX_DEGEN_CTRL = 3'b011;
+    parameter integer RX_DFELPM_CFG0 = 0;
+    parameter [0:0] RX_DFELPM_CFG1 = 1'b1;
     parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1;
     parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00;
     parameter integer RX_DFE_AGC_CFG1 = 4;
     parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1;
-    parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2;
+    parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4;
     parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01;
-    parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010;
+    parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4;
     parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
     parameter RX_DISPERR_SEQ_MATCH = "TRUE";
     parameter [0:0] RX_DIV2_MODE_B = 1'b0;
     parameter [4:0] RX_DIVRESET_TIME = 5'b00001;
     parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0;
-    parameter [0:0] RX_EN_HI_LR = 1'b0;
+    parameter [0:0] RX_EN_HI_LR = 1'b1;
     parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000;
     parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000;
     parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0;
@@ -16524,6 +16520,7 @@ module GTYE3_CHANNEL (...);
     parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0;
     parameter integer RX_INT_DATAWIDTH = 1;
     parameter [0:0] RX_PMA_POWER_SAVE = 1'b0;
+    parameter [15:0] RX_PMA_RSV0 = 16'h0000;
     parameter real RX_PROGDIV_CFG = 0.0;
     parameter [15:0] RX_PROGDIV_RATE = 16'h0001;
     parameter [3:0] RX_RESLOAD_CTRL = 4'b0000;
@@ -16531,34 +16528,32 @@ module GTYE3_CHANNEL (...);
     parameter [2:0] RX_SAMPLE_PERIOD = 3'b101;
     parameter integer RX_SIG_VALID_DLY = 11;
     parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0;
-    parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000;
-    parameter [3:0] RX_SUM_VCMTUNE = 4'b1000;
+    parameter [3:0] RX_SUM_IREF_TUNE = 4'b1001;
+    parameter [3:0] RX_SUM_RESLOAD_CTRL = 4'b0000;
+    parameter [3:0] RX_SUM_VCMTUNE = 4'b1010;
     parameter [0:0] RX_SUM_VCM_OVWR = 1'b0;
     parameter [2:0] RX_SUM_VREF_TUNE = 3'b100;
     parameter [1:0] RX_TUNE_AFE_OS = 2'b00;
     parameter [2:0] RX_VREG_CTRL = 3'b101;
     parameter [0:0] RX_VREG_PDB = 1'b1;
     parameter [1:0] RX_WIDEMODE_CDR = 2'b01;
+    parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01;
+    parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01;
     parameter RX_XCLK_SEL = "RXDES";
     parameter [0:0] RX_XMODE_SEL = 1'b0;
-    parameter integer SAS_MAX_COM = 64;
-    parameter integer SAS_MIN_COM = 36;
+    parameter [0:0] SAMPLE_CLK_PHASE = 1'b0;
+    parameter [0:0] SAS_12G_MODE = 1'b0;
     parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
     parameter [2:0] SATA_BURST_VAL = 3'b100;
     parameter SATA_CPLL_CFG = "VCO_3000MHZ";
     parameter [2:0] SATA_EIDLE_VAL = 3'b100;
-    parameter integer SATA_MAX_BURST = 8;
-    parameter integer SATA_MAX_INIT = 21;
-    parameter integer SATA_MAX_WAKE = 7;
-    parameter integer SATA_MIN_BURST = 4;
-    parameter integer SATA_MIN_INIT = 12;
-    parameter integer SATA_MIN_WAKE = 4;
     parameter SHOW_REALIGN_COMMA = "TRUE";
+    parameter SIM_DEVICE = "ULTRASCALE_PLUS";
     parameter SIM_MODE = "FAST";
     parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
     parameter SIM_RESET_SPEEDUP = "TRUE";
-    parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0;
-    parameter integer SIM_VERSION = 2;
+    parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z";
+    parameter [0:0] SRSTMODE = 1'b0;
     parameter [1:0] TAPDLY_SET_TX = 2'h0;
     parameter [3:0] TEMPERATURE_PAR = 4'b0010;
     parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
@@ -16568,18 +16563,20 @@ module GTYE3_CHANNEL (...);
     parameter [7:0] TST_RSV1 = 8'h00;
     parameter TXBUF_EN = "TRUE";
     parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
-    parameter [15:0] TXDLY_CFG = 16'h001F;
+    parameter [15:0] TXDLY_CFG = 16'h0010;
     parameter [15:0] TXDLY_LCFG = 16'h0030;
+    parameter [3:0] TXDRVBIAS_N = 4'b1010;
     parameter TXFIFO_ADDR_CFG = "LOW";
     parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4;
     parameter TXGEARBOX_EN = "FALSE";
     parameter integer TXOUT_DIV = 4;
     parameter [4:0] TXPCSRESET_TIME = 5'b00001;
-    parameter [15:0] TXPHDLY_CFG0 = 16'h2020;
-    parameter [15:0] TXPHDLY_CFG1 = 16'h0001;
+    parameter [15:0] TXPHDLY_CFG0 = 16'h6020;
+    parameter [15:0] TXPHDLY_CFG1 = 16'h0002;
     parameter [15:0] TXPH_CFG = 16'h0123;
     parameter [15:0] TXPH_CFG2 = 16'h0000;
     parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
+    parameter [15:0] TXPI_CFG = 16'h0000;
     parameter [1:0] TXPI_CFG0 = 2'b00;
     parameter [1:0] TXPI_CFG1 = 2'b00;
     parameter [1:0] TXPI_CFG2 = 2'b00;
@@ -16589,30 +16586,29 @@ module GTYE3_CHANNEL (...);
     parameter [0:0] TXPI_GRAY_SEL = 1'b0;
     parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
     parameter [0:0] TXPI_LPM = 1'b0;
+    parameter [0:0] TXPI_PPM = 1'b0;
     parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
     parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
-    parameter [15:0] TXPI_RSV0 = 16'h0000;
     parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
     parameter [0:0] TXPI_VREFSEL = 1'b0;
     parameter [4:0] TXPMARESET_TIME = 5'b00001;
+    parameter [0:0] TXREFCLKDIV2_SEL = 1'b0;
     parameter [0:0] TXSYNC_MULTILANE = 1'b0;
     parameter [0:0] TXSYNC_OVRD = 1'b0;
     parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
     parameter integer TX_CLK25_DIV = 8;
     parameter [0:0] TX_CLKMUX_EN = 1'b1;
-    parameter [0:0] TX_CLKREG_PDB = 1'b0;
-    parameter [2:0] TX_CLKREG_SET = 3'b000;
     parameter integer TX_DATA_WIDTH = 20;
-    parameter [5:0] TX_DCD_CFG = 6'b000010;
-    parameter [0:0] TX_DCD_EN = 1'b0;
+    parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000;
     parameter [5:0] TX_DEEMPH0 = 6'b000000;
     parameter [5:0] TX_DEEMPH1 = 6'b000000;
+    parameter [5:0] TX_DEEMPH2 = 6'b000000;
+    parameter [5:0] TX_DEEMPH3 = 6'b000000;
     parameter [4:0] TX_DIVRESET_TIME = 5'b00001;
     parameter TX_DRIVE_MODE = "DIRECT";
     parameter integer TX_DRVMUX_CTRL = 2;
     parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
     parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
-    parameter [0:0] TX_EML_PHI_TUNE = 1'b0;
     parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0;
     parameter [0:0] TX_FIFO_BYP_EN = 1'b0;
     parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0;
@@ -16629,44 +16625,75 @@ module GTYE3_CHANNEL (...);
     parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
     parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
     parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
-    parameter [2:0] TX_MODE_SEL = 3'b000;
     parameter [15:0] TX_PHICAL_CFG0 = 16'h0000;
-    parameter [15:0] TX_PHICAL_CFG1 = 16'h7E00;
+    parameter [15:0] TX_PHICAL_CFG1 = 16'h003F;
     parameter [15:0] TX_PHICAL_CFG2 = 16'h0000;
     parameter integer TX_PI_BIASSET = 0;
-    parameter [15:0] TX_PI_CFG0 = 16'h0000;
-    parameter [15:0] TX_PI_CFG1 = 16'h0000;
-    parameter [0:0] TX_PI_DIV2_MODE_B = 1'b0;
-    parameter [0:0] TX_PI_SEL_QPLL0 = 1'b0;
-    parameter [0:0] TX_PI_SEL_QPLL1 = 1'b0;
+    parameter [1:0] TX_PI_IBIAS_MID = 2'b00;
     parameter [0:0] TX_PMADATA_OPT = 1'b0;
     parameter [0:0] TX_PMA_POWER_SAVE = 1'b0;
+    parameter [15:0] TX_PMA_RSV0 = 16'h0008;
     parameter integer TX_PREDRV_CTRL = 2;
     parameter TX_PROGCLK_SEL = "POSTPI";
     parameter real TX_PROGDIV_CFG = 0.0;
     parameter [15:0] TX_PROGDIV_RATE = 16'h0001;
+    parameter [0:0] TX_QPI_STATUS_EN = 1'b0;
     parameter [13:0] TX_RXDETECT_CFG = 14'h0032;
-    parameter integer TX_RXDETECT_REF = 4;
+    parameter integer TX_RXDETECT_REF = 3;
     parameter [2:0] TX_SAMPLE_PERIOD = 3'b101;
     parameter [0:0] TX_SARC_LPBK_ENB = 1'b0;
+    parameter [1:0] TX_SW_MEAS = 2'b00;
+    parameter [2:0] TX_VREG_CTRL = 3'b000;
+    parameter [0:0] TX_VREG_PDB = 1'b0;
+    parameter [1:0] TX_VREG_VREFSEL = 2'b00;
     parameter TX_XCLK_SEL = "TXOUT";
+    parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0;
+    parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111;
+    parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011;
+    parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0;
+    parameter [0:0] USB_EXT_CNTL = 1'b1;
+    parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011;
+    parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011;
+    parameter [8:0] USB_LFPSPING_BURST = 9'b000000101;
+    parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001;
+    parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100;
+    parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101;
+    parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011;
+    parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011;
+    parameter [3:0] USB_LFPS_TPERIOD = 4'b0011;
+    parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1;
+    parameter [0:0] USB_MODE = 1'b0;
+    parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0;
+    parameter integer USB_PING_SATA_MAX_INIT = 21;
+    parameter integer USB_PING_SATA_MIN_INIT = 12;
+    parameter integer USB_POLL_SATA_MAX_BURST = 8;
+    parameter integer USB_POLL_SATA_MIN_BURST = 4;
+    parameter [0:0] USB_RAW_ELEC = 1'b0;
+    parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1;
+    parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1;
+    parameter integer USB_U1_SATA_MAX_WAKE = 7;
+    parameter integer USB_U1_SATA_MIN_WAKE = 4;
+    parameter integer USB_U2_SAS_MAX_COM = 64;
+    parameter integer USB_U2_SAS_MIN_COM = 36;
     parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
-    output [2:0] BUFGTCE;
+    parameter [0:0] Y_ALL_MODE = 1'b0;
+    output BUFGTCE;
     output [2:0] BUFGTCEMASK;
     output [8:0] BUFGTDIV;
-    output [2:0] BUFGTRESET;
+    output BUFGTRESET;
     output [2:0] BUFGTRSTMASK;
     output CPLLFBCLKLOST;
     output CPLLLOCK;
     output CPLLREFCLKLOST;
-    output [16:0] DMONITOROUT;
+    output [15:0] DMONITOROUT;
+    output DMONITOROUTCLK;
     output [15:0] DRPDO;
     output DRPRDY;
     output EYESCANDATAERROR;
+    output GTHTXN;
+    output GTHTXP;
     output GTPOWERGOOD;
     output GTREFCLKMONITOR;
-    output GTYTXN;
-    output GTYTXP;
     output PCIERATEGEN3;
     output PCIERATEIDLE;
     output [1:0] PCIERATEQPLLPD;
@@ -16677,7 +16704,8 @@ module GTYE3_CHANNEL (...);
     output PCIEUSERRATESTART;
     output [15:0] PCSRSVDOUT;
     output PHYSTATUS;
-    output [7:0] PINRSRVDAS;
+    output [15:0] PINRSRVDAS;
+    output POWERPRESENT;
     output RESETEXCEPTION;
     output [2:0] RXBUFSTATUS;
     output RXBYTEISALIGNED;
@@ -16705,7 +16733,10 @@ module GTYE3_CHANNEL (...);
     output RXELECIDLE;
     output [5:0] RXHEADER;
     output [1:0] RXHEADERVALID;
-    output [6:0] RXMONITOROUT;
+    output RXLFPSTRESETDET;
+    output RXLFPSU2LPEXITDET;
+    output RXLFPSU3WAKEDET;
+    output [7:0] RXMONITOROUT;
     output RXOSINTDONE;
     output RXOSINTSTARTED;
     output RXOSINTSTROBEDONE;
@@ -16719,6 +16750,8 @@ module GTYE3_CHANNEL (...);
     output RXPRBSERR;
     output RXPRBSLOCKED;
     output RXPRGDIVRESETDONE;
+    output RXQPISENN;
+    output RXQPISENP;
     output RXRATEDONE;
     output RXRECCLKOUT;
     output RXRESETDONE;
@@ -16742,6 +16775,8 @@ module GTYE3_CHANNEL (...);
     output TXPHINITDONE;
     output TXPMARESETDONE;
     output TXPRGDIVRESETDONE;
+    output TXQPISENN;
+    output TXQPISENP;
     output TXRATEDONE;
     output TXRESETDONE;
     output TXSYNCDONE;
@@ -16752,6 +16787,7 @@ module GTYE3_CHANNEL (...);
     input CFGRESET;
     input CLKRSVD0;
     input CLKRSVD1;
+    input CPLLFREQLOCK;
     input CPLLLOCKDETCLK;
     input CPLLLOCKEN;
     input CPLLPD;
@@ -16763,65 +16799,64 @@ module GTYE3_CHANNEL (...);
     input DRPCLK;
     input [15:0] DRPDI;
     input DRPEN;
+    input DRPRST;
     input DRPWE;
-    input ELPCALDVORWREN;
-    input ELPCALPAORWREN;
-    input EVODDPHICALDONE;
-    input EVODDPHICALSTART;
-    input EVODDPHIDRDEN;
-    input EVODDPHIDWREN;
-    input EVODDPHIXRDEN;
-    input EVODDPHIXWREN;
-    input EYESCANMODE;
     input EYESCANRESET;
     input EYESCANTRIGGER;
+    input FREQOS;
     input GTGREFCLK;
+    input GTHRXN;
+    input GTHRXP;
     input GTNORTHREFCLK0;
     input GTNORTHREFCLK1;
     input GTREFCLK0;
     input GTREFCLK1;
-    input GTRESETSEL;
     input [15:0] GTRSVD;
     input GTRXRESET;
+    input GTRXRESETSEL;
     input GTSOUTHREFCLK0;
     input GTSOUTHREFCLK1;
     input GTTXRESET;
-    input GTYRXN;
-    input GTYRXP;
+    input GTTXRESETSEL;
+    input INCPCTRL;
     input [2:0] LOOPBACK;
-    input [15:0] LOOPRSVD;
-    input LPBKRXTXSEREN;
-    input LPBKTXRXSEREN;
     input PCIEEQRXEQADAPTDONE;
     input PCIERSTIDLE;
     input PCIERSTTXSYNCSTART;
     input PCIEUSERRATEDONE;
     input [15:0] PCSRSVDIN;
-    input [4:0] PCSRSVDIN2;
-    input [4:0] PMARSVDIN;
     input QPLL0CLK;
+    input QPLL0FREQLOCK;
     input QPLL0REFCLK;
     input QPLL1CLK;
+    input QPLL1FREQLOCK;
     input QPLL1REFCLK;
     input RESETOVRD;
-    input RSTCLKENTX;
     input RX8B10BEN;
+    input RXAFECFOKEN;
     input RXBUFRESET;
     input RXCDRFREQRESET;
     input RXCDRHOLD;
     input RXCDROVRDEN;
     input RXCDRRESET;
-    input RXCDRRESETRSV;
     input RXCHBONDEN;
     input [4:0] RXCHBONDI;
     input [2:0] RXCHBONDLEVEL;
     input RXCHBONDMASTER;
     input RXCHBONDSLAVE;
     input RXCKCALRESET;
+    input [6:0] RXCKCALSTART;
     input RXCOMMADETEN;
-    input RXDCCFORCESTART;
+    input [1:0] RXDFEAGCCTRL;
     input RXDFEAGCHOLD;
     input RXDFEAGCOVRDEN;
+    input [3:0] RXDFECFOKFCNUM;
+    input RXDFECFOKFEN;
+    input RXDFECFOKFPULSE;
+    input RXDFECFOKHOLD;
+    input RXDFECFOKOVREN;
+    input RXDFEKHHOLD;
+    input RXDFEKHOVRDEN;
     input RXDFELFHOLD;
     input RXDFELFOVRDEN;
     input RXDFELPMRESET;
@@ -16857,13 +16892,13 @@ module GTYE3_CHANNEL (...);
     input RXDFEUTOVRDEN;
     input RXDFEVPHOLD;
     input RXDFEVPOVRDEN;
-    input RXDFEVSEN;
     input RXDFEXYDEN;
     input RXDLYBYPASS;
     input RXDLYEN;
     input RXDLYOVRDEN;
     input RXDLYSRESET;
     input [1:0] RXELECIDLEMODE;
+    input RXEQTRAINING;
     input RXGEARBOXSLIP;
     input RXLATCLK;
     input RXLPMEN;
@@ -16880,12 +16915,6 @@ module GTYE3_CHANNEL (...);
     input RXOOBRESET;
     input RXOSCALRESET;
     input RXOSHOLD;
-    input [3:0] RXOSINTCFG;
-    input RXOSINTEN;
-    input RXOSINTHOLD;
-    input RXOSINTOVRDEN;
-    input RXOSINTSTROBE;
-    input RXOSINTTESTOVRDEN;
     input RXOSOVRDEN;
     input [2:0] RXOUTCLKSEL;
     input RXPCOMMAALIGNEN;
@@ -16902,6 +16931,7 @@ module GTYE3_CHANNEL (...);
     input RXPRBSCNTRESET;
     input [3:0] RXPRBSSEL;
     input RXPROGDIVRESET;
+    input RXQPIEN;
     input [2:0] RXRATE;
     input RXRATEMODE;
     input RXSLIDE;
@@ -16911,6 +16941,7 @@ module GTYE3_CHANNEL (...);
     input RXSYNCIN;
     input RXSYNCMODE;
     input [1:0] RXSYSCLKSEL;
+    input RXTERMINATION;
     input RXUSERRDY;
     input RXUSRCLK;
     input RXUSRCLK2;
@@ -16918,7 +16949,6 @@ module GTYE3_CHANNEL (...);
     input [19:0] TSTIN;
     input [7:0] TX8B10BBYPASS;
     input TX8B10BEN;
-    input [2:0] TXBUFDIFFCTRL;
     input TXCOMINIT;
     input TXCOMSAS;
     input TXCOMWAKE;
@@ -16929,10 +16959,9 @@ module GTYE3_CHANNEL (...);
     input [7:0] TXDATAEXTENDRSVD;
     input TXDCCFORCESTART;
     input TXDCCRESET;
-    input TXDEEMPH;
+    input [1:0] TXDEEMPH;
     input TXDETECTRX;
     input [4:0] TXDIFFCTRL;
-    input TXDIFFPD;
     input TXDLYBYPASS;
     input TXDLYEN;
     input TXDLYHOLD;
@@ -16940,12 +16969,17 @@ module GTYE3_CHANNEL (...);
     input TXDLYSRESET;
     input TXDLYUPDOWN;
     input TXELECIDLE;
-    input TXELFORCESTART;
     input [5:0] TXHEADER;
     input TXINHIBIT;
     input TXLATCLK;
+    input TXLFPSTRESET;
+    input TXLFPSU2LPEXIT;
+    input TXLFPSU3WAKE;
     input [6:0] TXMAINCURSOR;
     input [2:0] TXMARGIN;
+    input TXMUXDCDEXHOLD;
+    input TXMUXDCDORWREN;
+    input TXONESZEROS;
     input [2:0] TXOUTCLKSEL;
     input TXPCSRESET;
     input [1:0] TXPD;
@@ -16971,6 +17005,8 @@ module GTYE3_CHANNEL (...);
     input [3:0] TXPRBSSEL;
     input [4:0] TXPRECURSOR;
     input TXPROGDIVRESET;
+    input TXQPIBIASEN;
+    input TXQPIWEAKPUP;
     input [2:0] TXRATE;
     input TXRATEMODE;
     input [6:0] TXSEQUENCE;
@@ -16984,28 +17020,34 @@ module GTYE3_CHANNEL (...);
     input TXUSRCLK2;
 endmodule
 
-module GTYE3_COMMON (...);
-    parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000;
-    parameter [8:0] A_SDM1DATA1_1 = 9'b000000000;
+module GTHE4_COMMON (...);
+    parameter [0:0] AEN_QPLL0_FBDIV = 1'b1;
+    parameter [0:0] AEN_QPLL1_FBDIV = 1'b1;
+    parameter [0:0] AEN_SDM0TOGGLE = 1'b0;
+    parameter [0:0] AEN_SDM1TOGGLE = 1'b0;
+    parameter [0:0] A_SDM0TOGGLE = 1'b0;
+    parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000;
+    parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000;
+    parameter [0:0] A_SDM1TOGGLE = 1'b0;
     parameter [15:0] BIAS_CFG0 = 16'h0000;
     parameter [15:0] BIAS_CFG1 = 16'h0000;
     parameter [15:0] BIAS_CFG2 = 16'h0000;
     parameter [15:0] BIAS_CFG3 = 16'h0000;
     parameter [15:0] BIAS_CFG4 = 16'h0000;
-    parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000;
+    parameter [15:0] BIAS_CFG_RSVD = 16'h0000;
     parameter [15:0] COMMON_CFG0 = 16'h0000;
     parameter [15:0] COMMON_CFG1 = 16'h0000;
-    parameter [15:0] POR_CFG = 16'h0004;
-    parameter [15:0] PPF0_CFG = 16'h0FFF;
-    parameter [15:0] PPF1_CFG = 16'h0FFF;
+    parameter [15:0] POR_CFG = 16'h0000;
+    parameter [15:0] PPF0_CFG = 16'h0F00;
+    parameter [15:0] PPF1_CFG = 16'h0F00;
     parameter QPLL0CLKOUT_RATE = "FULL";
-    parameter [15:0] QPLL0_CFG0 = 16'h301C;
+    parameter [15:0] QPLL0_CFG0 = 16'h391C;
     parameter [15:0] QPLL0_CFG1 = 16'h0000;
     parameter [15:0] QPLL0_CFG1_G3 = 16'h0020;
-    parameter [15:0] QPLL0_CFG2 = 16'h0780;
-    parameter [15:0] QPLL0_CFG2_G3 = 16'h0780;
+    parameter [15:0] QPLL0_CFG2 = 16'h0F80;
+    parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80;
     parameter [15:0] QPLL0_CFG3 = 16'h0120;
-    parameter [15:0] QPLL0_CFG4 = 16'h0021;
+    parameter [15:0] QPLL0_CFG4 = 16'h0002;
     parameter [9:0] QPLL0_CP = 10'b0000011111;
     parameter [9:0] QPLL0_CP_G3 = 10'b0000011111;
     parameter integer QPLL0_FBDIV = 66;
@@ -17014,20 +17056,22 @@ module GTYE3_COMMON (...);
     parameter [7:0] QPLL0_INIT_CFG1 = 8'h00;
     parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8;
     parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8;
-    parameter [9:0] QPLL0_LPF = 10'b1111111111;
+    parameter [9:0] QPLL0_LPF = 10'b1011111111;
     parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111;
-    parameter integer QPLL0_REFCLK_DIV = 2;
+    parameter [0:0] QPLL0_PCI_EN = 1'b0;
+    parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0;
+    parameter integer QPLL0_REFCLK_DIV = 1;
     parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040;
     parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000;
     parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000;
     parameter QPLL1CLKOUT_RATE = "FULL";
-    parameter [15:0] QPLL1_CFG0 = 16'h301C;
-    parameter [15:0] QPLL1_CFG1 = 16'h0000;
+    parameter [15:0] QPLL1_CFG0 = 16'h691C;
+    parameter [15:0] QPLL1_CFG1 = 16'h0020;
     parameter [15:0] QPLL1_CFG1_G3 = 16'h0020;
-    parameter [15:0] QPLL1_CFG2 = 16'h0780;
-    parameter [15:0] QPLL1_CFG2_G3 = 16'h0780;
+    parameter [15:0] QPLL1_CFG2 = 16'h0F80;
+    parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80;
     parameter [15:0] QPLL1_CFG3 = 16'h0120;
-    parameter [15:0] QPLL1_CFG4 = 16'h0021;
+    parameter [15:0] QPLL1_CFG4 = 16'h0002;
     parameter [9:0] QPLL1_CP = 10'b0000011111;
     parameter [9:0] QPLL1_CP_G3 = 10'b0000011111;
     parameter integer QPLL1_FBDIV = 66;
@@ -17036,10 +17080,12 @@ module GTYE3_COMMON (...);
     parameter [7:0] QPLL1_INIT_CFG1 = 8'h00;
     parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8;
     parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8;
-    parameter [9:0] QPLL1_LPF = 10'b1111111111;
+    parameter [9:0] QPLL1_LPF = 10'b1011111111;
     parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111;
-    parameter integer QPLL1_REFCLK_DIV = 2;
-    parameter [15:0] QPLL1_SDM_CFG0 = 16'h0040;
+    parameter [0:0] QPLL1_PCI_EN = 1'b0;
+    parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0;
+    parameter integer QPLL1_REFCLK_DIV = 1;
+    parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000;
     parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000;
     parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000;
     parameter [15:0] RSVD_ATTR0 = 16'h0000;
@@ -17048,15 +17094,15 @@ module GTYE3_COMMON (...);
     parameter [15:0] RSVD_ATTR3 = 16'h0000;
     parameter [1:0] RXRECCLKOUT0_SEL = 2'b00;
     parameter [1:0] RXRECCLKOUT1_SEL = 2'b00;
-    parameter [0:0] SARC_EN = 1'b1;
+    parameter [0:0] SARC_ENB = 1'b0;
     parameter [0:0] SARC_SEL = 1'b0;
     parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000;
     parameter [8:0] SDM0INITSEED0_1 = 9'b000000000;
     parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000;
     parameter [8:0] SDM1INITSEED0_1 = 9'b000000000;
+    parameter SIM_DEVICE = "ULTRASCALE_PLUS";
     parameter SIM_MODE = "FAST";
     parameter SIM_RESET_SPEEDUP = "TRUE";
-    parameter integer SIM_VERSION = 2;
     output [15:0] DRPDO;
     output DRPRDY;
     output [7:0] PMARSVDOUT0;
@@ -17075,18 +17121,20 @@ module GTYE3_COMMON (...);
     output [7:0] QPLLDMONITOR1;
     output REFCLKOUTMONITOR0;
     output REFCLKOUTMONITOR1;
-    output [1:0] RXRECCLK0_SEL;
-    output [1:0] RXRECCLK1_SEL;
+    output [1:0] RXRECCLK0SEL;
+    output [1:0] RXRECCLK1SEL;
     output [3:0] SDM0FINALOUT;
     output [14:0] SDM0TESTDATA;
     output [3:0] SDM1FINALOUT;
     output [14:0] SDM1TESTDATA;
+    output [9:0] TCONGPO;
+    output TCONRSVDOUT0;
     input BGBYPASSB;
     input BGMONITORENB;
     input BGPDB;
     input [4:0] BGRCALOVRD;
     input BGRCALOVRDENB;
-    input [9:0] DRPADDR;
+    input [15:0] DRPADDR;
     input DRPCLK;
     input [15:0] DRPDI;
     input DRPEN;
@@ -17105,15 +17153,21 @@ module GTYE3_COMMON (...);
     input GTSOUTHREFCLK01;
     input GTSOUTHREFCLK10;
     input GTSOUTHREFCLK11;
+    input [2:0] PCIERATEQPLL0;
+    input [2:0] PCIERATEQPLL1;
     input [7:0] PMARSVD0;
     input [7:0] PMARSVD1;
     input QPLL0CLKRSVD0;
+    input QPLL0CLKRSVD1;
+    input [7:0] QPLL0FBDIV;
     input QPLL0LOCKDETCLK;
     input QPLL0LOCKEN;
     input QPLL0PD;
     input [2:0] QPLL0REFCLKSEL;
     input QPLL0RESET;
     input QPLL1CLKRSVD0;
+    input QPLL1CLKRSVD1;
+    input [7:0] QPLL1FBDIV;
     input QPLL1LOCKDETCLK;
     input QPLL1LOCKEN;
     input QPLL1PD;
@@ -17126,10 +17180,16 @@ module GTYE3_COMMON (...);
     input RCALENB;
     input [24:0] SDM0DATA;
     input SDM0RESET;
+    input SDM0TOGGLE;
     input [1:0] SDM0WIDTH;
     input [24:0] SDM1DATA;
     input SDM1RESET;
+    input SDM1TOGGLE;
     input [1:0] SDM1WIDTH;
+    input [9:0] TCONGPI;
+    input TCONPOWERUP;
+    input [1:0] TCONRESET;
+    input [1:0] TCONRSVDIN1;
 endmodule
 
 module GTYE4_CHANNEL (...);
@@ -18154,19 +18214,6 @@ module GTYE4_COMMON (...);
     input UBMDMTDI;
 endmodule
 
-module IBUFDS_GTE3 (...);
-    parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
-    parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00;
-    parameter [1:0] REFCLK_ICNTL_RX = 2'b00;
-    output O;
-    output ODIV2;
-    input CEB;
-    (* iopad_external_pin *)
-    input I;
-    (* iopad_external_pin *)
-    input IB;
-endmodule
-
 module IBUFDS_GTE4 (...);
     parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
     parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00;
@@ -18180,7 +18227,7 @@ module IBUFDS_GTE4 (...);
     input IB;
 endmodule
 
-module OBUFDS_GTE3 (...);
+module OBUFDS_GTE4 (...);
     parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
     parameter [4:0] REFCLK_ICNTL_TX = 5'b00000;
     (* iopad_external_pin *)
@@ -18191,7 +18238,7 @@ module OBUFDS_GTE3 (...);
     input I;
 endmodule
 
-module OBUFDS_GTE3_ADV (...);
+module OBUFDS_GTE4_ADV (...);
     parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
     parameter [4:0] REFCLK_ICNTL_TX = 5'b00000;
     (* iopad_external_pin *)
@@ -18203,9 +18250,669 @@ module OBUFDS_GTE3_ADV (...);
     input [1:0] RXRECCLK_SEL;
 endmodule
 
-module OBUFDS_GTE4 (...);
+module GTM_DUAL (...);
+    parameter [15:0] A_CFG = 16'b0000100001000000;
+    parameter [15:0] A_SDM_DATA_CFG0 = 16'b0000000011010000;
+    parameter [15:0] A_SDM_DATA_CFG1 = 16'b0000000011010000;
+    parameter [15:0] BIAS_CFG0 = 16'b0000000000000000;
+    parameter [15:0] BIAS_CFG1 = 16'b0000000000000000;
+    parameter [15:0] BIAS_CFG2 = 16'b0001000000000000;
+    parameter [15:0] BIAS_CFG3 = 16'b0000000000000001;
+    parameter [15:0] BIAS_CFG4 = 16'b0000000000000000;
+    parameter [15:0] BIAS_CFG5 = 16'b0000000000000000;
+    parameter [15:0] BIAS_CFG6 = 16'b0000000010000000;
+    parameter [15:0] BIAS_CFG7 = 16'b0000000000000000;
+    parameter [15:0] CH0_A_CH_CFG0 = 16'b0000000000000011;
+    parameter [15:0] CH0_A_CH_CFG1 = 16'b0000000000000000;
+    parameter [15:0] CH0_A_CH_CFG2 = 16'b0111101111110000;
+    parameter [15:0] CH0_A_CH_CFG3 = 16'b0000000000000000;
+    parameter [15:0] CH0_A_CH_CFG4 = 16'b0000000000000000;
+    parameter [15:0] CH0_A_CH_CFG5 = 16'b0000000000000000;
+    parameter [15:0] CH0_A_CH_CFG6 = 16'b0000000000000000;
+    parameter [15:0] CH0_RST_LP_CFG0 = 16'b0001000000010000;
+    parameter [15:0] CH0_RST_LP_CFG1 = 16'b0011001000010000;
+    parameter [15:0] CH0_RST_LP_CFG2 = 16'b0110010100000100;
+    parameter [15:0] CH0_RST_LP_CFG3 = 16'b0011001000010000;
+    parameter [15:0] CH0_RST_LP_CFG4 = 16'b0000000001000100;
+    parameter [15:0] CH0_RST_LP_ID_CFG0 = 16'b0011000001110000;
+    parameter [15:0] CH0_RST_LP_ID_CFG1 = 16'b0001000000010000;
+    parameter [15:0] CH0_RST_TIME_CFG0 = 16'b0000010000100001;
+    parameter [15:0] CH0_RST_TIME_CFG1 = 16'b0000010000100001;
+    parameter [15:0] CH0_RST_TIME_CFG2 = 16'b0000010000100001;
+    parameter [15:0] CH0_RST_TIME_CFG3 = 16'b0000010000100000;
+    parameter [15:0] CH0_RST_TIME_CFG4 = 16'b0000010000100001;
+    parameter [15:0] CH0_RST_TIME_CFG5 = 16'b0000000000000001;
+    parameter [15:0] CH0_RST_TIME_CFG6 = 16'b0000000000100001;
+    parameter [15:0] CH0_RX_ADC_CFG0 = 16'b0011010010001111;
+    parameter [15:0] CH0_RX_ADC_CFG1 = 16'b0011111001010101;
+    parameter [15:0] CH0_RX_ANA_CFG0 = 16'b1000000000011101;
+    parameter [15:0] CH0_RX_ANA_CFG1 = 16'b1110100010000000;
+    parameter [15:0] CH0_RX_ANA_CFG2 = 16'b0000000010001010;
+    parameter [15:0] CH0_RX_APT_CFG0A = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG0B = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG10A = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG10B = 16'b0000000001010000;
+    parameter [15:0] CH0_RX_APT_CFG11A = 16'b0000000001000000;
+    parameter [15:0] CH0_RX_APT_CFG11B = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG12A = 16'b0000000001010000;
+    parameter [15:0] CH0_RX_APT_CFG12B = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG13A = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG13B = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG14A = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG14B = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG15A = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG15B = 16'b0000100000000000;
+    parameter [15:0] CH0_RX_APT_CFG16A = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG16B = 16'b0010000000000000;
+    parameter [15:0] CH0_RX_APT_CFG17A = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG17B = 16'b0001000001000000;
+    parameter [15:0] CH0_RX_APT_CFG18A = 16'b0000100000100000;
+    parameter [15:0] CH0_RX_APT_CFG18B = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG19A = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG19B = 16'b0000100000000000;
+    parameter [15:0] CH0_RX_APT_CFG1A = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG1B = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG20A = 16'b1110000000100000;
+    parameter [15:0] CH0_RX_APT_CFG20B = 16'b0000000001000000;
+    parameter [15:0] CH0_RX_APT_CFG21A = 16'b0001000000000100;
+    parameter [15:0] CH0_RX_APT_CFG21B = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG22A = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG22B = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG23A = 16'b0000100000000000;
+    parameter [15:0] CH0_RX_APT_CFG23B = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG24A = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG24B = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG25A = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG25B = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG26A = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG26B = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG27A = 16'b0100000000000000;
+    parameter [15:0] CH0_RX_APT_CFG27B = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG28A = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG28B = 16'b1000000000000000;
+    parameter [15:0] CH0_RX_APT_CFG2A = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG2B = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG3A = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG3B = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG4A = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG4B = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG5A = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG5B = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG6A = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG6B = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG7A = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG7B = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG8A = 16'b0000100000000000;
+    parameter [15:0] CH0_RX_APT_CFG8B = 16'b0000100000000000;
+    parameter [15:0] CH0_RX_APT_CFG9A = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CFG9B = 16'b0000000001110000;
+    parameter [15:0] CH0_RX_APT_CTRL_CFG2 = 16'b0000000000000100;
+    parameter [15:0] CH0_RX_APT_CTRL_CFG3 = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_CAL_CFG0A = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_CAL_CFG0B = 16'b0011001100110000;
+    parameter [15:0] CH0_RX_CAL_CFG1A = 16'b1110111011100001;
+    parameter [15:0] CH0_RX_CAL_CFG1B = 16'b1111111100000100;
+    parameter [15:0] CH0_RX_CAL_CFG2A = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_CAL_CFG2B = 16'b0011000000000000;
+    parameter [15:0] CH0_RX_CDR_CFG0A = 16'b0000000000000011;
+    parameter [15:0] CH0_RX_CDR_CFG0B = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_CDR_CFG1A = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_CDR_CFG1B = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_CDR_CFG2A = 16'b1001000101100100;
+    parameter [15:0] CH0_RX_CDR_CFG2B = 16'b0000000100100100;
+    parameter [15:0] CH0_RX_CDR_CFG3A = 16'b0101110011110110;
+    parameter [15:0] CH0_RX_CDR_CFG3B = 16'b0000000000001011;
+    parameter [15:0] CH0_RX_CDR_CFG4A = 16'b0000000000000110;
+    parameter [15:0] CH0_RX_CDR_CFG4B = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_CLKGN_CFG0 = 16'b1100000000000000;
+    parameter [15:0] CH0_RX_CLKGN_CFG1 = 16'b0000000110000000;
+    parameter [15:0] CH0_RX_CTLE_CFG0 = 16'b0011010010001000;
+    parameter [15:0] CH0_RX_CTLE_CFG1 = 16'b0010000000100010;
+    parameter [15:0] CH0_RX_CTLE_CFG2 = 16'b0000101000000000;
+    parameter [15:0] CH0_RX_CTLE_CFG3 = 16'b1111001001000000;
+    parameter [15:0] CH0_RX_DSP_CFG = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_MON_CFG = 16'b0000000000000000;
+    parameter [15:0] CH0_RX_PAD_CFG0 = 16'b0001111000000000;
+    parameter [15:0] CH0_RX_PAD_CFG1 = 16'b0001100000001010;
+    parameter [15:0] CH0_RX_PCS_CFG0 = 16'b0000000100000000;
+    parameter [15:0] CH0_RX_PCS_CFG1 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_ANA_CFG0 = 16'b0000001010101111;
+    parameter [15:0] CH0_TX_ANA_CFG1 = 16'b0000000100000000;
+    parameter [15:0] CH0_TX_ANA_CFG2 = 16'b1000000000010100;
+    parameter [15:0] CH0_TX_ANA_CFG3 = 16'b0000101000100010;
+    parameter [15:0] CH0_TX_ANA_CFG4 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_CAL_CFG0 = 16'b0000000000100000;
+    parameter [15:0] CH0_TX_CAL_CFG1 = 16'b0000000001000000;
+    parameter [15:0] CH0_TX_DRV_CFG0 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_DRV_CFG1 = 16'b0000000000100111;
+    parameter [15:0] CH0_TX_DRV_CFG2 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_DRV_CFG3 = 16'b0110110000000000;
+    parameter [15:0] CH0_TX_DRV_CFG4 = 16'b0000000011000101;
+    parameter [15:0] CH0_TX_DRV_CFG5 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_LPBK_CFG0 = 16'b0000000000000011;
+    parameter [15:0] CH0_TX_LPBK_CFG1 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG0 = 16'b0000000101100000;
+    parameter [15:0] CH0_TX_PCS_CFG1 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG10 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG11 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG12 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG13 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG14 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG15 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG16 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG17 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG2 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG3 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG4 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG5 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG6 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG7 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG8 = 16'b0000000000000000;
+    parameter [15:0] CH0_TX_PCS_CFG9 = 16'b0000000000000000;
+    parameter [15:0] CH1_A_CH_CFG0 = 16'b0000000000000011;
+    parameter [15:0] CH1_A_CH_CFG1 = 16'b0000000000000000;
+    parameter [15:0] CH1_A_CH_CFG2 = 16'b0111101111110000;
+    parameter [15:0] CH1_A_CH_CFG3 = 16'b0000000000000000;
+    parameter [15:0] CH1_A_CH_CFG4 = 16'b0000000000000000;
+    parameter [15:0] CH1_A_CH_CFG5 = 16'b0000000000000000;
+    parameter [15:0] CH1_A_CH_CFG6 = 16'b0000000000000000;
+    parameter [15:0] CH1_RST_LP_CFG0 = 16'b0001000000010000;
+    parameter [15:0] CH1_RST_LP_CFG1 = 16'b0011001000010000;
+    parameter [15:0] CH1_RST_LP_CFG2 = 16'b0110010100000100;
+    parameter [15:0] CH1_RST_LP_CFG3 = 16'b0011001000010000;
+    parameter [15:0] CH1_RST_LP_CFG4 = 16'b0000000001000100;
+    parameter [15:0] CH1_RST_LP_ID_CFG0 = 16'b0011000001110000;
+    parameter [15:0] CH1_RST_LP_ID_CFG1 = 16'b0001000000010000;
+    parameter [15:0] CH1_RST_TIME_CFG0 = 16'b0000010000100001;
+    parameter [15:0] CH1_RST_TIME_CFG1 = 16'b0000010000100001;
+    parameter [15:0] CH1_RST_TIME_CFG2 = 16'b0000010000100001;
+    parameter [15:0] CH1_RST_TIME_CFG3 = 16'b0000010000100000;
+    parameter [15:0] CH1_RST_TIME_CFG4 = 16'b0000010000100001;
+    parameter [15:0] CH1_RST_TIME_CFG5 = 16'b0000000000000001;
+    parameter [15:0] CH1_RST_TIME_CFG6 = 16'b0000000000100001;
+    parameter [15:0] CH1_RX_ADC_CFG0 = 16'b0011010010001111;
+    parameter [15:0] CH1_RX_ADC_CFG1 = 16'b0011111001010101;
+    parameter [15:0] CH1_RX_ANA_CFG0 = 16'b1000000000011101;
+    parameter [15:0] CH1_RX_ANA_CFG1 = 16'b1110100010000000;
+    parameter [15:0] CH1_RX_ANA_CFG2 = 16'b0000000010001010;
+    parameter [15:0] CH1_RX_APT_CFG0A = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG0B = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG10A = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG10B = 16'b0000000001010000;
+    parameter [15:0] CH1_RX_APT_CFG11A = 16'b0000000001000000;
+    parameter [15:0] CH1_RX_APT_CFG11B = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG12A = 16'b0000000001010000;
+    parameter [15:0] CH1_RX_APT_CFG12B = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG13A = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG13B = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG14A = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG14B = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG15A = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG15B = 16'b0000100000000000;
+    parameter [15:0] CH1_RX_APT_CFG16A = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG16B = 16'b0010000000000000;
+    parameter [15:0] CH1_RX_APT_CFG17A = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG17B = 16'b0001000001000000;
+    parameter [15:0] CH1_RX_APT_CFG18A = 16'b0000100000100000;
+    parameter [15:0] CH1_RX_APT_CFG18B = 16'b0000100010000000;
+    parameter [15:0] CH1_RX_APT_CFG19A = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG19B = 16'b0000100000000000;
+    parameter [15:0] CH1_RX_APT_CFG1A = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG1B = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG20A = 16'b1110000000100000;
+    parameter [15:0] CH1_RX_APT_CFG20B = 16'b0000000001000000;
+    parameter [15:0] CH1_RX_APT_CFG21A = 16'b0001000000000100;
+    parameter [15:0] CH1_RX_APT_CFG21B = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG22A = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG22B = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG23A = 16'b0000100000000000;
+    parameter [15:0] CH1_RX_APT_CFG23B = 16'b0000100000000000;
+    parameter [15:0] CH1_RX_APT_CFG24A = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG24B = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG25A = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG25B = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG26A = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG26B = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG27A = 16'b0100000000000000;
+    parameter [15:0] CH1_RX_APT_CFG27B = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG28A = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG28B = 16'b1000000000000000;
+    parameter [15:0] CH1_RX_APT_CFG2A = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG2B = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG3A = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG3B = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG4A = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG4B = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG5A = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG5B = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG6A = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG6B = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG7A = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG7B = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG8A = 16'b0000100000000000;
+    parameter [15:0] CH1_RX_APT_CFG8B = 16'b0000100000000000;
+    parameter [15:0] CH1_RX_APT_CFG9A = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CFG9B = 16'b0000000001110000;
+    parameter [15:0] CH1_RX_APT_CTRL_CFG2 = 16'b0000000000000100;
+    parameter [15:0] CH1_RX_APT_CTRL_CFG3 = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_CAL_CFG0A = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_CAL_CFG0B = 16'b0011001100110000;
+    parameter [15:0] CH1_RX_CAL_CFG1A = 16'b1110111011100001;
+    parameter [15:0] CH1_RX_CAL_CFG1B = 16'b1111111100000100;
+    parameter [15:0] CH1_RX_CAL_CFG2A = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_CAL_CFG2B = 16'b0011000000000000;
+    parameter [15:0] CH1_RX_CDR_CFG0A = 16'b0000000000000011;
+    parameter [15:0] CH1_RX_CDR_CFG0B = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_CDR_CFG1A = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_CDR_CFG1B = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_CDR_CFG2A = 16'b1001000101100100;
+    parameter [15:0] CH1_RX_CDR_CFG2B = 16'b0000000100100100;
+    parameter [15:0] CH1_RX_CDR_CFG3A = 16'b0101110011110110;
+    parameter [15:0] CH1_RX_CDR_CFG3B = 16'b0000000000001011;
+    parameter [15:0] CH1_RX_CDR_CFG4A = 16'b0000000000000110;
+    parameter [15:0] CH1_RX_CDR_CFG4B = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_CLKGN_CFG0 = 16'b1100000000000000;
+    parameter [15:0] CH1_RX_CLKGN_CFG1 = 16'b0000000110000000;
+    parameter [15:0] CH1_RX_CTLE_CFG0 = 16'b0011010010001000;
+    parameter [15:0] CH1_RX_CTLE_CFG1 = 16'b0010000000100010;
+    parameter [15:0] CH1_RX_CTLE_CFG2 = 16'b0000101000000000;
+    parameter [15:0] CH1_RX_CTLE_CFG3 = 16'b1111001001000000;
+    parameter [15:0] CH1_RX_DSP_CFG = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_MON_CFG = 16'b0000000000000000;
+    parameter [15:0] CH1_RX_PAD_CFG0 = 16'b0001111000000000;
+    parameter [15:0] CH1_RX_PAD_CFG1 = 16'b0001100000001010;
+    parameter [15:0] CH1_RX_PCS_CFG0 = 16'b0000000100000000;
+    parameter [15:0] CH1_RX_PCS_CFG1 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_ANA_CFG0 = 16'b0000001010101111;
+    parameter [15:0] CH1_TX_ANA_CFG1 = 16'b0000000100000000;
+    parameter [15:0] CH1_TX_ANA_CFG2 = 16'b1000000000010100;
+    parameter [15:0] CH1_TX_ANA_CFG3 = 16'b0000101000100010;
+    parameter [15:0] CH1_TX_ANA_CFG4 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_CAL_CFG0 = 16'b0000000000100000;
+    parameter [15:0] CH1_TX_CAL_CFG1 = 16'b0000000001000000;
+    parameter [15:0] CH1_TX_DRV_CFG0 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_DRV_CFG1 = 16'b0000000000100111;
+    parameter [15:0] CH1_TX_DRV_CFG2 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_DRV_CFG3 = 16'b0110110000000000;
+    parameter [15:0] CH1_TX_DRV_CFG4 = 16'b0000000011000101;
+    parameter [15:0] CH1_TX_DRV_CFG5 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_LPBK_CFG0 = 16'b0000000000000011;
+    parameter [15:0] CH1_TX_LPBK_CFG1 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG0 = 16'b0000000101100000;
+    parameter [15:0] CH1_TX_PCS_CFG1 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG10 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG11 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG12 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG13 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG14 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG15 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG16 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG17 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG2 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG3 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG4 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG5 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG6 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG7 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG8 = 16'b0000000000000000;
+    parameter [15:0] CH1_TX_PCS_CFG9 = 16'b0000000000000000;
+    parameter real DATARATE = 10.000;
+    parameter [15:0] DRPEN_CFG = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG0 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG1 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG10 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG11 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG12 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG13 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG14 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG15 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG16 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG17 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG18 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG19 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG2 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG20 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG21 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG22 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG23 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG24 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG25 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG26 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG27 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG3 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG4 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG5 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG6 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG7 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG8 = 16'b0000000000000000;
+    parameter [15:0] FEC_CFG9 = 16'b0000000000000000;
+    parameter FEC_MODE = "BYPASS";
+    parameter real INS_LOSS_NYQ = 20.000;
+    parameter integer INTERFACE_WIDTH = 64;
+    parameter MODULATION_MODE = "NRZ";
+    parameter [15:0] PLL_CFG0 = 16'b0001100111110000;
+    parameter [15:0] PLL_CFG1 = 16'b0000111101110000;
+    parameter [15:0] PLL_CFG2 = 16'b1000000111101000;
+    parameter [15:0] PLL_CFG3 = 16'b0100000000000000;
+    parameter [15:0] PLL_CFG4 = 16'b0111111111101010;
+    parameter [15:0] PLL_CFG5 = 16'b0100101100111000;
+    parameter [15:0] PLL_CFG6 = 16'b0000000000100101;
+    parameter [15:0] PLL_CRS_CTRL_CFG0 = 16'b0000101100100000;
+    parameter [15:0] PLL_CRS_CTRL_CFG1 = 16'b1100010111010100;
+    parameter [0:0] PLL_IPS_PIN_EN = 1'b1;
+    parameter integer PLL_IPS_REFCLK_SEL = 0;
+    parameter [0:0] RCALSAP_TESTEN = 1'b0;
+    parameter [0:0] RCAL_APROBE = 1'b0;
+    parameter [15:0] RST_CFG = 16'b0000000000000010;
+    parameter [15:0] RST_PLL_CFG0 = 16'b0111011000010100;
+    parameter [15:0] SAP_CFG0 = 16'b0000000000000000;
+    parameter [15:0] SDM_CFG0 = 16'b0001100001000000;
+    parameter [15:0] SDM_CFG1 = 16'b0000000000000000;
+    parameter [15:0] SDM_CFG2 = 16'b0000000000000000;
+    parameter [15:0] SDM_SEED_CFG0 = 16'b0000000000000000;
+    parameter [15:0] SDM_SEED_CFG1 = 16'b0000000000000000;
+    parameter SIM_DEVICE = "ULTRASCALE_PLUS_ES1";
+    parameter SIM_RESET_SPEEDUP = "TRUE";
+    parameter integer TX_AMPLITUDE_SWING = 250;
+    output [27:0] CH0_AXISTDATA;
+    output CH0_AXISTLAST;
+    output CH0_AXISTVALID;
+    output [31:0] CH0_DMONITOROUT;
+    output CH0_DMONITOROUTCLK;
+    output CH0_GTMTXN;
+    output CH0_GTMTXP;
+    output [15:0] CH0_PCSRSVDOUT;
+    output [15:0] CH0_PMARSVDOUT;
+    output CH0_RESETEXCEPTION;
+    output [2:0] CH0_RXBUFSTATUS;
+    output [255:0] CH0_RXDATA;
+    output [3:0] CH0_RXDATAFLAGS;
+    output CH0_RXDATAISAM;
+    output CH0_RXDATASTART;
+    output CH0_RXOUTCLK;
+    output CH0_RXPMARESETDONE;
+    output CH0_RXPRBSERR;
+    output CH0_RXPRBSLOCKED;
+    output CH0_RXPRGDIVRESETDONE;
+    output CH0_RXPROGDIVCLK;
+    output CH0_RXRESETDONE;
+    output [1:0] CH0_TXBUFSTATUS;
+    output CH0_TXOUTCLK;
+    output CH0_TXPMARESETDONE;
+    output CH0_TXPRGDIVRESETDONE;
+    output CH0_TXPROGDIVCLK;
+    output CH0_TXRESETDONE;
+    output [27:0] CH1_AXISTDATA;
+    output CH1_AXISTLAST;
+    output CH1_AXISTVALID;
+    output [31:0] CH1_DMONITOROUT;
+    output CH1_DMONITOROUTCLK;
+    output CH1_GTMTXN;
+    output CH1_GTMTXP;
+    output [15:0] CH1_PCSRSVDOUT;
+    output [15:0] CH1_PMARSVDOUT;
+    output CH1_RESETEXCEPTION;
+    output [2:0] CH1_RXBUFSTATUS;
+    output [255:0] CH1_RXDATA;
+    output [3:0] CH1_RXDATAFLAGS;
+    output CH1_RXDATAISAM;
+    output CH1_RXDATASTART;
+    output CH1_RXOUTCLK;
+    output CH1_RXPMARESETDONE;
+    output CH1_RXPRBSERR;
+    output CH1_RXPRBSLOCKED;
+    output CH1_RXPRGDIVRESETDONE;
+    output CH1_RXPROGDIVCLK;
+    output CH1_RXRESETDONE;
+    output [1:0] CH1_TXBUFSTATUS;
+    output CH1_TXOUTCLK;
+    output CH1_TXPMARESETDONE;
+    output CH1_TXPRGDIVRESETDONE;
+    output CH1_TXPROGDIVCLK;
+    output CH1_TXRESETDONE;
+    output CLKTESTSIG2PAD;
+    output DMONITOROUTPLLCLK;
+    output [15:0] DRPDO;
+    output DRPRDY;
+    output FECRX0ALIGNED;
+    output FECRX0CORRCWINC;
+    output FECRX0CWINC;
+    output FECRX0UNCORRCWINC;
+    output FECRX1ALIGNED;
+    output FECRX1CORRCWINC;
+    output FECRX1CWINC;
+    output FECRX1UNCORRCWINC;
+    output [7:0] FECRXLN0BITERR0TO1INC;
+    output [7:0] FECRXLN0BITERR1TO0INC;
+    output [14:0] FECRXLN0DLY;
+    output [3:0] FECRXLN0ERRCNTINC;
+    output [1:0] FECRXLN0MAPPING;
+    output [7:0] FECRXLN1BITERR0TO1INC;
+    output [7:0] FECRXLN1BITERR1TO0INC;
+    output [14:0] FECRXLN1DLY;
+    output [3:0] FECRXLN1ERRCNTINC;
+    output [1:0] FECRXLN1MAPPING;
+    output [7:0] FECRXLN2BITERR0TO1INC;
+    output [7:0] FECRXLN2BITERR1TO0INC;
+    output [14:0] FECRXLN2DLY;
+    output [3:0] FECRXLN2ERRCNTINC;
+    output [1:0] FECRXLN2MAPPING;
+    output [7:0] FECRXLN3BITERR0TO1INC;
+    output [7:0] FECRXLN3BITERR1TO0INC;
+    output [14:0] FECRXLN3DLY;
+    output [3:0] FECRXLN3ERRCNTINC;
+    output [1:0] FECRXLN3MAPPING;
+    output FECTRXLN0LOCK;
+    output FECTRXLN1LOCK;
+    output FECTRXLN2LOCK;
+    output FECTRXLN3LOCK;
+    output GTPOWERGOOD;
+    output PLLFBCLKLOST;
+    output PLLLOCK;
+    output PLLREFCLKLOST;
+    output PLLREFCLKMONITOR;
+    output PLLRESETDONE;
+    output [15:0] PLLRSVDOUT;
+    output RCALCMP;
+    output [4:0] RCALOUT;
+    output RXRECCLK0;
+    output RXRECCLK1;
+    input BGBYPASSB;
+    input BGMONITORENB;
+    input BGPDB;
+    input [4:0] BGRCALOVRD;
+    input BGRCALOVRDENB;
+    input CH0_AXISEN;
+    input CH0_AXISRST;
+    input CH0_AXISTRDY;
+    input CH0_CFGRESET;
+    input CH0_DMONFIFORESET;
+    input CH0_DMONITORCLK;
+    input CH0_GTMRXN;
+    input CH0_GTMRXP;
+    input CH0_GTRXRESET;
+    input CH0_GTTXRESET;
+    input [2:0] CH0_LOOPBACK;
+    input [15:0] CH0_PCSRSVDIN;
+    input [15:0] CH0_PMARSVDIN;
+    input CH0_RESETOVRD;
+    input CH0_RXADAPTRESET;
+    input CH0_RXADCCALRESET;
+    input CH0_RXADCCLKGENRESET;
+    input CH0_RXBUFRESET;
+    input CH0_RXCDRFREQOS;
+    input CH0_RXCDRFRRESET;
+    input CH0_RXCDRHOLD;
+    input CH0_RXCDRINCPCTRL;
+    input CH0_RXCDROVRDEN;
+    input CH0_RXCDRPHRESET;
+    input CH0_RXDFERESET;
+    input CH0_RXDSPRESET;
+    input CH0_RXEQTRAINING;
+    input CH0_RXEYESCANRESET;
+    input CH0_RXFECRESET;
+    input [2:0] CH0_RXOUTCLKSEL;
+    input CH0_RXPCSRESET;
+    input [3:0] CH0_RXPCSRESETMASK;
+    input CH0_RXPMARESET;
+    input [7:0] CH0_RXPMARESETMASK;
+    input CH0_RXPOLARITY;
+    input CH0_RXPRBSCNTSTOP;
+    input CH0_RXPRBSCSCNTRST;
+    input [3:0] CH0_RXPRBSPTN;
+    input CH0_RXPROGDIVRESET;
+    input CH0_RXQPRBSEN;
+    input [1:0] CH0_RXRESETMODE;
+    input CH0_RXSPCSEQADV;
+    input CH0_RXUSRCLK;
+    input CH0_RXUSRCLK2;
+    input CH0_RXUSRRDY;
+    input CH0_RXUSRSTART;
+    input CH0_RXUSRSTOP;
+    input CH0_TXCKALRESET;
+    input [5:0] CH0_TXCTLFIRDAT;
+    input [255:0] CH0_TXDATA;
+    input CH0_TXDATASTART;
+    input [4:0] CH0_TXDRVAMP;
+    input [5:0] CH0_TXEMPMAIN;
+    input [4:0] CH0_TXEMPPOST;
+    input [4:0] CH0_TXEMPPRE;
+    input [3:0] CH0_TXEMPPRE2;
+    input CH0_TXFECRESET;
+    input CH0_TXINHIBIT;
+    input CH0_TXMUXDCDEXHOLD;
+    input CH0_TXMUXDCDORWREN;
+    input [2:0] CH0_TXOUTCLKSEL;
+    input CH0_TXPCSRESET;
+    input [1:0] CH0_TXPCSRESETMASK;
+    input CH0_TXPMARESET;
+    input [1:0] CH0_TXPMARESETMASK;
+    input CH0_TXPOLARITY;
+    input CH0_TXPRBSINERR;
+    input [3:0] CH0_TXPRBSPTN;
+    input CH0_TXPROGDIVRESET;
+    input CH0_TXQPRBSEN;
+    input [1:0] CH0_TXRESETMODE;
+    input CH0_TXSPCSEQADV;
+    input CH0_TXUSRCLK;
+    input CH0_TXUSRCLK2;
+    input CH0_TXUSRRDY;
+    input CH1_AXISEN;
+    input CH1_AXISRST;
+    input CH1_AXISTRDY;
+    input CH1_CFGRESET;
+    input CH1_DMONFIFORESET;
+    input CH1_DMONITORCLK;
+    input CH1_GTMRXN;
+    input CH1_GTMRXP;
+    input CH1_GTRXRESET;
+    input CH1_GTTXRESET;
+    input [2:0] CH1_LOOPBACK;
+    input [15:0] CH1_PCSRSVDIN;
+    input [15:0] CH1_PMARSVDIN;
+    input CH1_RESETOVRD;
+    input CH1_RXADAPTRESET;
+    input CH1_RXADCCALRESET;
+    input CH1_RXADCCLKGENRESET;
+    input CH1_RXBUFRESET;
+    input CH1_RXCDRFREQOS;
+    input CH1_RXCDRFRRESET;
+    input CH1_RXCDRHOLD;
+    input CH1_RXCDRINCPCTRL;
+    input CH1_RXCDROVRDEN;
+    input CH1_RXCDRPHRESET;
+    input CH1_RXDFERESET;
+    input CH1_RXDSPRESET;
+    input CH1_RXEQTRAINING;
+    input CH1_RXEYESCANRESET;
+    input CH1_RXFECRESET;
+    input [2:0] CH1_RXOUTCLKSEL;
+    input CH1_RXPCSRESET;
+    input [3:0] CH1_RXPCSRESETMASK;
+    input CH1_RXPMARESET;
+    input [7:0] CH1_RXPMARESETMASK;
+    input CH1_RXPOLARITY;
+    input CH1_RXPRBSCNTSTOP;
+    input CH1_RXPRBSCSCNTRST;
+    input [3:0] CH1_RXPRBSPTN;
+    input CH1_RXPROGDIVRESET;
+    input CH1_RXQPRBSEN;
+    input [1:0] CH1_RXRESETMODE;
+    input CH1_RXSPCSEQADV;
+    input CH1_RXUSRCLK;
+    input CH1_RXUSRCLK2;
+    input CH1_RXUSRRDY;
+    input CH1_RXUSRSTART;
+    input CH1_RXUSRSTOP;
+    input CH1_TXCKALRESET;
+    input [5:0] CH1_TXCTLFIRDAT;
+    input [255:0] CH1_TXDATA;
+    input CH1_TXDATASTART;
+    input [4:0] CH1_TXDRVAMP;
+    input [5:0] CH1_TXEMPMAIN;
+    input [4:0] CH1_TXEMPPOST;
+    input [4:0] CH1_TXEMPPRE;
+    input [3:0] CH1_TXEMPPRE2;
+    input CH1_TXFECRESET;
+    input CH1_TXINHIBIT;
+    input CH1_TXMUXDCDEXHOLD;
+    input CH1_TXMUXDCDORWREN;
+    input [2:0] CH1_TXOUTCLKSEL;
+    input CH1_TXPCSRESET;
+    input [1:0] CH1_TXPCSRESETMASK;
+    input CH1_TXPMARESET;
+    input [1:0] CH1_TXPMARESETMASK;
+    input CH1_TXPOLARITY;
+    input CH1_TXPRBSINERR;
+    input [3:0] CH1_TXPRBSPTN;
+    input CH1_TXPROGDIVRESET;
+    input CH1_TXQPRBSEN;
+    input [1:0] CH1_TXRESETMODE;
+    input CH1_TXSPCSEQADV;
+    input CH1_TXUSRCLK;
+    input CH1_TXUSRCLK2;
+    input CH1_TXUSRRDY;
+    input [10:0] DRPADDR;
+    input DRPCLK;
+    input [15:0] DRPDI;
+    input DRPEN;
+    input DRPRST;
+    input DRPWE;
+    input FECCTRLRX0BITSLIPFS;
+    input FECCTRLRX1BITSLIPFS;
+    input GTGREFCLK2PLL;
+    input GTNORTHREFCLK;
+    input GTREFCLK;
+    input GTSOUTHREFCLK;
+    input [7:0] PLLFBDIV;
+    input PLLMONCLK;
+    input PLLPD;
+    input [2:0] PLLREFCLKSEL;
+    input PLLRESET;
+    input PLLRESETBYPASSMODE;
+    input [1:0] PLLRESETMASK;
+    input [15:0] PLLRSVDIN;
+    input RCALENB;
+    input [25:0] SDMDATA;
+    input SDMTOGGLE;
+endmodule
+
+module IBUFDS_GTM (...);
     parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
-    parameter [4:0] REFCLK_ICNTL_TX = 5'b00000;
+    parameter integer REFCLK_HROW_CK_SEL = 0;
+    parameter integer REFCLK_ICNTL_RX = 0;
+    output O;
+    output ODIV2;
+    input CEB;
+    (* iopad_external_pin *)
+    input I;
+    (* iopad_external_pin *)
+    input IB;
+endmodule
+
+module OBUFDS_GTM (...);
+    parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
+    parameter integer REFCLK_ICNTL_TX = 0;
     (* iopad_external_pin *)
     output O;
     (* iopad_external_pin *)
@@ -18214,16 +18921,259 @@ module OBUFDS_GTE4 (...);
     input I;
 endmodule
 
-module OBUFDS_GTE4_ADV (...);
+module OBUFDS_GTM_ADV (...);
     parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
-    parameter [4:0] REFCLK_ICNTL_TX = 5'b00000;
+    parameter integer REFCLK_ICNTL_TX = 0;
+    parameter [1:0] RXRECCLK_SEL = 2'b00;
     (* iopad_external_pin *)
     output O;
     (* iopad_external_pin *)
     output OB;
     input CEB;
     input [3:0] I;
-    input [1:0] RXRECCLK_SEL;
+endmodule
+
+module HSDAC (...);
+    parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+    parameter integer XPA_CFG0 = 0;
+    parameter integer XPA_CFG1 = 0;
+    parameter integer XPA_NUM_DACS = 0;
+    parameter integer XPA_NUM_DUCS = 0;
+    parameter XPA_PLL_USED = "No";
+    parameter integer XPA_SAMPLE_RATE_MSPS = 0;
+    output CLK_DAC;
+    output [15:0] DOUT;
+    output DRDY;
+    output PLL_DMON_OUT;
+    output PLL_REFCLK_OUT;
+    output [15:0] STATUS_COMMON;
+    output [15:0] STATUS_DAC0;
+    output [15:0] STATUS_DAC1;
+    output [15:0] STATUS_DAC2;
+    output [15:0] STATUS_DAC3;
+    output SYSREF_OUT_NORTH;
+    output SYSREF_OUT_SOUTH;
+    output VOUT0_N;
+    output VOUT0_P;
+    output VOUT1_N;
+    output VOUT1_P;
+    output VOUT2_N;
+    output VOUT2_P;
+    output VOUT3_N;
+    output VOUT3_P;
+    input CLK_FIFO_LM;
+    input [15:0] CONTROL_COMMON;
+    input [15:0] CONTROL_DAC0;
+    input [15:0] CONTROL_DAC1;
+    input [15:0] CONTROL_DAC2;
+    input [15:0] CONTROL_DAC3;
+    input DAC_CLK_N;
+    input DAC_CLK_P;
+    input [11:0] DADDR;
+    input [255:0] DATA_DAC0;
+    input [255:0] DATA_DAC1;
+    input [255:0] DATA_DAC2;
+    input [255:0] DATA_DAC3;
+    input DCLK;
+    input DEN;
+    input [15:0] DI;
+    input DWE;
+    input FABRIC_CLK;
+    input PLL_MONCLK;
+    input PLL_REFCLK_IN;
+    input SYSREF_IN_NORTH;
+    input SYSREF_IN_SOUTH;
+    input SYSREF_N;
+    input SYSREF_P;
+endmodule
+
+module HSADC (...);
+    parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+    parameter integer XPA_CFG0 = 0;
+    parameter integer XPA_CFG1 = 0;
+    parameter XPA_NUM_ADCS = "0";
+    parameter integer XPA_NUM_DDCS = 0;
+    parameter XPA_PLL_USED = "No";
+    parameter integer XPA_SAMPLE_RATE_MSPS = 0;
+    output CLK_ADC;
+    output [127:0] DATA_ADC0;
+    output [127:0] DATA_ADC1;
+    output [127:0] DATA_ADC2;
+    output [127:0] DATA_ADC3;
+    output [15:0] DOUT;
+    output DRDY;
+    output PLL_DMON_OUT;
+    output PLL_REFCLK_OUT;
+    output [15:0] STATUS_ADC0;
+    output [15:0] STATUS_ADC1;
+    output [15:0] STATUS_ADC2;
+    output [15:0] STATUS_ADC3;
+    output [15:0] STATUS_COMMON;
+    output SYSREF_OUT_NORTH;
+    output SYSREF_OUT_SOUTH;
+    input ADC_CLK_N;
+    input ADC_CLK_P;
+    input CLK_FIFO_LM;
+    input [15:0] CONTROL_ADC0;
+    input [15:0] CONTROL_ADC1;
+    input [15:0] CONTROL_ADC2;
+    input [15:0] CONTROL_ADC3;
+    input [15:0] CONTROL_COMMON;
+    input [11:0] DADDR;
+    input DCLK;
+    input DEN;
+    input [15:0] DI;
+    input DWE;
+    input FABRIC_CLK;
+    input PLL_MONCLK;
+    input PLL_REFCLK_IN;
+    input SYSREF_IN_NORTH;
+    input SYSREF_IN_SOUTH;
+    input SYSREF_N;
+    input SYSREF_P;
+    input VIN0_N;
+    input VIN0_P;
+    input VIN1_N;
+    input VIN1_P;
+    input VIN2_N;
+    input VIN2_P;
+    input VIN3_N;
+    input VIN3_P;
+    input VIN_I01_N;
+    input VIN_I01_P;
+    input VIN_I23_N;
+    input VIN_I23_P;
+endmodule
+
+module RFDAC (...);
+    parameter integer OPT_CLK_DIST = 0;
+    parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+    parameter integer XPA_ACTIVE_DUTYCYCLE = 100;
+    parameter integer XPA_CFG0 = 0;
+    parameter integer XPA_CFG1 = 0;
+    parameter integer XPA_CFG2 = 0;
+    parameter integer XPA_NUM_DACS = 0;
+    parameter integer XPA_NUM_DUCS = 0;
+    parameter XPA_PLL_USED = "EXTERNAL";
+    parameter integer XPA_SAMPLE_RATE_MSPS = 0;
+    output CLK_DAC;
+    output CLK_DIST_OUT_NORTH;
+    output CLK_DIST_OUT_SOUTH;
+    output [15:0] DOUT;
+    output DRDY;
+    output PLL_DMON_OUT;
+    output PLL_REFCLK_OUT;
+    output [23:0] STATUS_COMMON;
+    output [23:0] STATUS_DAC0;
+    output [23:0] STATUS_DAC1;
+    output [23:0] STATUS_DAC2;
+    output [23:0] STATUS_DAC3;
+    output SYSREF_OUT_NORTH;
+    output SYSREF_OUT_SOUTH;
+    output T1_ALLOWED_SOUTH;
+    output VOUT0_N;
+    output VOUT0_P;
+    output VOUT1_N;
+    output VOUT1_P;
+    output VOUT2_N;
+    output VOUT2_P;
+    output VOUT3_N;
+    output VOUT3_P;
+    input CLK_DIST_IN_NORTH;
+    input CLK_DIST_IN_SOUTH;
+    input CLK_FIFO_LM;
+    input [15:0] CONTROL_COMMON;
+    input [15:0] CONTROL_DAC0;
+    input [15:0] CONTROL_DAC1;
+    input [15:0] CONTROL_DAC2;
+    input [15:0] CONTROL_DAC3;
+    input DAC_CLK_N;
+    input DAC_CLK_P;
+    input [11:0] DADDR;
+    input [255:0] DATA_DAC0;
+    input [255:0] DATA_DAC1;
+    input [255:0] DATA_DAC2;
+    input [255:0] DATA_DAC3;
+    input DCLK;
+    input DEN;
+    input [15:0] DI;
+    input DWE;
+    input FABRIC_CLK;
+    input PLL_MONCLK;
+    input PLL_REFCLK_IN;
+    input SYSREF_IN_NORTH;
+    input SYSREF_IN_SOUTH;
+    input SYSREF_N;
+    input SYSREF_P;
+    input T1_ALLOWED_NORTH;
+endmodule
+
+module RFADC (...);
+    parameter integer OPT_ANALOG = 0;
+    parameter integer OPT_CLK_DIST = 0;
+    parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+    parameter integer XPA_ACTIVE_DUTYCYCLE = 100;
+    parameter integer XPA_CFG0 = 0;
+    parameter integer XPA_CFG1 = 0;
+    parameter integer XPA_CFG2 = 0;
+    parameter XPA_NUM_ADCS = "0";
+    parameter integer XPA_NUM_DDCS = 0;
+    parameter XPA_PLL_USED = "EXTERNAL";
+    parameter integer XPA_SAMPLE_RATE_MSPS = 0;
+    output CLK_ADC;
+    output CLK_DIST_OUT_NORTH;
+    output CLK_DIST_OUT_SOUTH;
+    output [191:0] DATA_ADC0;
+    output [191:0] DATA_ADC1;
+    output [191:0] DATA_ADC2;
+    output [191:0] DATA_ADC3;
+    output [15:0] DOUT;
+    output DRDY;
+    output PLL_DMON_OUT;
+    output PLL_REFCLK_OUT;
+    output [23:0] STATUS_ADC0;
+    output [23:0] STATUS_ADC1;
+    output [23:0] STATUS_ADC2;
+    output [23:0] STATUS_ADC3;
+    output [23:0] STATUS_COMMON;
+    output SYSREF_OUT_NORTH;
+    output SYSREF_OUT_SOUTH;
+    output T1_ALLOWED_SOUTH;
+    input ADC_CLK_N;
+    input ADC_CLK_P;
+    input CLK_DIST_IN_NORTH;
+    input CLK_DIST_IN_SOUTH;
+    input CLK_FIFO_LM;
+    input [15:0] CONTROL_ADC0;
+    input [15:0] CONTROL_ADC1;
+    input [15:0] CONTROL_ADC2;
+    input [15:0] CONTROL_ADC3;
+    input [15:0] CONTROL_COMMON;
+    input [11:0] DADDR;
+    input DCLK;
+    input DEN;
+    input [15:0] DI;
+    input DWE;
+    input FABRIC_CLK;
+    input PLL_MONCLK;
+    input PLL_REFCLK_IN;
+    input SYSREF_IN_NORTH;
+    input SYSREF_IN_SOUTH;
+    input SYSREF_N;
+    input SYSREF_P;
+    input T1_ALLOWED_NORTH;
+    input VIN0_N;
+    input VIN0_P;
+    input VIN1_N;
+    input VIN1_P;
+    input VIN2_N;
+    input VIN2_P;
+    input VIN3_N;
+    input VIN3_P;
+    input VIN_I01_N;
+    input VIN_I01_P;
+    input VIN_I23_N;
+    input VIN_I23_P;
 endmodule
 
 module PCIE_A1 (...);
@@ -23603,2093 +24553,2804 @@ module PCIE40E4 (...);
     input [31:0] USERSPAREIN;
 endmodule
 
-module EMAC (...);
-    parameter EMAC0_MODE = "RGMII";
-    parameter EMAC1_MODE = "RGMII";
-    output DCRHOSTDONEIR;
-    output EMAC0CLIENTANINTERRUPT;
-    output EMAC0CLIENTRXBADFRAME;
-    output EMAC0CLIENTRXCLIENTCLKOUT;
-    output EMAC0CLIENTRXDVLD;
-    output EMAC0CLIENTRXDVLDMSW;
-    output EMAC0CLIENTRXDVREG6;
-    output EMAC0CLIENTRXFRAMEDROP;
-    output EMAC0CLIENTRXGOODFRAME;
-    output EMAC0CLIENTRXSTATSBYTEVLD;
-    output EMAC0CLIENTRXSTATSVLD;
-    output EMAC0CLIENTTXACK;
-    output EMAC0CLIENTTXCLIENTCLKOUT;
-    output EMAC0CLIENTTXCOLLISION;
-    output EMAC0CLIENTTXGMIIMIICLKOUT;
-    output EMAC0CLIENTTXRETRANSMIT;
-    output EMAC0CLIENTTXSTATS;
-    output EMAC0CLIENTTXSTATSBYTEVLD;
-    output EMAC0CLIENTTXSTATSVLD;
-    output EMAC0PHYENCOMMAALIGN;
-    output EMAC0PHYLOOPBACKMSB;
-    output EMAC0PHYMCLKOUT;
-    output EMAC0PHYMDOUT;
-    output EMAC0PHYMDTRI;
-    output EMAC0PHYMGTRXRESET;
-    output EMAC0PHYMGTTXRESET;
-    output EMAC0PHYPOWERDOWN;
-    output EMAC0PHYSYNCACQSTATUS;
-    output EMAC0PHYTXCHARDISPMODE;
-    output EMAC0PHYTXCHARDISPVAL;
-    output EMAC0PHYTXCHARISK;
-    output EMAC0PHYTXCLK;
-    output EMAC0PHYTXEN;
-    output EMAC0PHYTXER;
-    output EMAC1CLIENTANINTERRUPT;
-    output EMAC1CLIENTRXBADFRAME;
-    output EMAC1CLIENTRXCLIENTCLKOUT;
-    output EMAC1CLIENTRXDVLD;
-    output EMAC1CLIENTRXDVLDMSW;
-    output EMAC1CLIENTRXDVREG6;
-    output EMAC1CLIENTRXFRAMEDROP;
-    output EMAC1CLIENTRXGOODFRAME;
-    output EMAC1CLIENTRXSTATSBYTEVLD;
-    output EMAC1CLIENTRXSTATSVLD;
-    output EMAC1CLIENTTXACK;
-    output EMAC1CLIENTTXCLIENTCLKOUT;
-    output EMAC1CLIENTTXCOLLISION;
-    output EMAC1CLIENTTXGMIIMIICLKOUT;
-    output EMAC1CLIENTTXRETRANSMIT;
-    output EMAC1CLIENTTXSTATS;
-    output EMAC1CLIENTTXSTATSBYTEVLD;
-    output EMAC1CLIENTTXSTATSVLD;
-    output EMAC1PHYENCOMMAALIGN;
-    output EMAC1PHYLOOPBACKMSB;
-    output EMAC1PHYMCLKOUT;
-    output EMAC1PHYMDOUT;
-    output EMAC1PHYMDTRI;
-    output EMAC1PHYMGTRXRESET;
-    output EMAC1PHYMGTTXRESET;
-    output EMAC1PHYPOWERDOWN;
-    output EMAC1PHYSYNCACQSTATUS;
-    output EMAC1PHYTXCHARDISPMODE;
-    output EMAC1PHYTXCHARDISPVAL;
-    output EMAC1PHYTXCHARISK;
-    output EMAC1PHYTXCLK;
-    output EMAC1PHYTXEN;
-    output EMAC1PHYTXER;
-    output EMACDCRACK;
-    output HOSTMIIMRDY;
-    output [0:31] EMACDCRDBUS;
-    output [15:0] EMAC0CLIENTRXD;
-    output [15:0] EMAC1CLIENTRXD;
-    output [31:0] HOSTRDDATA;
-    output [6:0] EMAC0CLIENTRXSTATS;
-    output [6:0] EMAC1CLIENTRXSTATS;
-    output [7:0] EMAC0PHYTXD;
-    output [7:0] EMAC1PHYTXD;
-    input CLIENTEMAC0DCMLOCKED;
-    input CLIENTEMAC0PAUSEREQ;
-    input CLIENTEMAC0RXCLIENTCLKIN;
-    input CLIENTEMAC0TXCLIENTCLKIN;
-    input CLIENTEMAC0TXDVLD;
-    input CLIENTEMAC0TXDVLDMSW;
-    input CLIENTEMAC0TXFIRSTBYTE;
-    input CLIENTEMAC0TXGMIIMIICLKIN;
-    input CLIENTEMAC0TXUNDERRUN;
-    input CLIENTEMAC1DCMLOCKED;
-    input CLIENTEMAC1PAUSEREQ;
-    input CLIENTEMAC1RXCLIENTCLKIN;
-    input CLIENTEMAC1TXCLIENTCLKIN;
-    input CLIENTEMAC1TXDVLD;
-    input CLIENTEMAC1TXDVLDMSW;
-    input CLIENTEMAC1TXFIRSTBYTE;
-    input CLIENTEMAC1TXGMIIMIICLKIN;
-    input CLIENTEMAC1TXUNDERRUN;
-    input DCREMACCLK;
-    input DCREMACENABLE;
-    input DCREMACREAD;
-    input DCREMACWRITE;
-    input HOSTCLK;
-    input HOSTEMAC1SEL;
-    input HOSTMIIMSEL;
-    input HOSTREQ;
-    input PHYEMAC0COL;
-    input PHYEMAC0CRS;
-    input PHYEMAC0GTXCLK;
-    input PHYEMAC0MCLKIN;
-    input PHYEMAC0MDIN;
-    input PHYEMAC0MIITXCLK;
-    input PHYEMAC0RXBUFERR;
-    input PHYEMAC0RXCHARISCOMMA;
-    input PHYEMAC0RXCHARISK;
-    input PHYEMAC0RXCHECKINGCRC;
-    input PHYEMAC0RXCLK;
-    input PHYEMAC0RXCOMMADET;
-    input PHYEMAC0RXDISPERR;
-    input PHYEMAC0RXDV;
-    input PHYEMAC0RXER;
-    input PHYEMAC0RXNOTINTABLE;
-    input PHYEMAC0RXRUNDISP;
-    input PHYEMAC0SIGNALDET;
-    input PHYEMAC0TXBUFERR;
-    input PHYEMAC1COL;
-    input PHYEMAC1CRS;
-    input PHYEMAC1GTXCLK;
-    input PHYEMAC1MCLKIN;
-    input PHYEMAC1MDIN;
-    input PHYEMAC1MIITXCLK;
-    input PHYEMAC1RXBUFERR;
-    input PHYEMAC1RXCHARISCOMMA;
-    input PHYEMAC1RXCHARISK;
-    input PHYEMAC1RXCHECKINGCRC;
-    input PHYEMAC1RXCLK;
-    input PHYEMAC1RXCOMMADET;
-    input PHYEMAC1RXDISPERR;
-    input PHYEMAC1RXDV;
-    input PHYEMAC1RXER;
-    input PHYEMAC1RXNOTINTABLE;
-    input PHYEMAC1RXRUNDISP;
-    input PHYEMAC1SIGNALDET;
-    input PHYEMAC1TXBUFERR;
-    input RESET;
-    input [0:31] DCREMACDBUS;
-    input [15:0] CLIENTEMAC0PAUSEVAL;
-    input [15:0] CLIENTEMAC0TXD;
-    input [15:0] CLIENTEMAC1PAUSEVAL;
-    input [15:0] CLIENTEMAC1TXD;
-    input [1:0] HOSTOPCODE;
-    input [1:0] PHYEMAC0RXBUFSTATUS;
-    input [1:0] PHYEMAC0RXLOSSOFSYNC;
-    input [1:0] PHYEMAC1RXBUFSTATUS;
-    input [1:0] PHYEMAC1RXLOSSOFSYNC;
-    input [2:0] PHYEMAC0RXCLKCORCNT;
-    input [2:0] PHYEMAC1RXCLKCORCNT;
-    input [31:0] HOSTWRDATA;
-    input [47:0] TIEEMAC0UNICASTADDR;
-    input [47:0] TIEEMAC1UNICASTADDR;
-    input [4:0] PHYEMAC0PHYAD;
-    input [4:0] PHYEMAC1PHYAD;
-    input [79:0] TIEEMAC0CONFIGVEC;
-    input [79:0] TIEEMAC1CONFIGVEC;
-    input [7:0] CLIENTEMAC0TXIFGDELAY;
-    input [7:0] CLIENTEMAC1TXIFGDELAY;
-    input [7:0] PHYEMAC0RXD;
-    input [7:0] PHYEMAC1RXD;
-    input [8:9] DCREMACABUS;
-    input [9:0] HOSTADDR;
-endmodule
-
-module TEMAC (...);
-    parameter EMAC0_1000BASEX_ENABLE = "FALSE";
-    parameter EMAC0_ADDRFILTER_ENABLE = "FALSE";
-    parameter EMAC0_BYTEPHY = "FALSE";
-    parameter EMAC0_CONFIGVEC_79 = "FALSE";
-    parameter EMAC0_GTLOOPBACK = "FALSE";
-    parameter EMAC0_HOST_ENABLE = "FALSE";
-    parameter EMAC0_LTCHECK_DISABLE = "FALSE";
-    parameter EMAC0_MDIO_ENABLE = "FALSE";
-    parameter EMAC0_PHYINITAUTONEG_ENABLE = "FALSE";
-    parameter EMAC0_PHYISOLATE = "FALSE";
-    parameter EMAC0_PHYLOOPBACKMSB = "FALSE";
-    parameter EMAC0_PHYPOWERDOWN = "FALSE";
-    parameter EMAC0_PHYRESET = "FALSE";
-    parameter EMAC0_RGMII_ENABLE = "FALSE";
-    parameter EMAC0_RX16BITCLIENT_ENABLE = "FALSE";
-    parameter EMAC0_RXFLOWCTRL_ENABLE = "FALSE";
-    parameter EMAC0_RXHALFDUPLEX = "FALSE";
-    parameter EMAC0_RXINBANDFCS_ENABLE = "FALSE";
-    parameter EMAC0_RXJUMBOFRAME_ENABLE = "FALSE";
-    parameter EMAC0_RXRESET = "FALSE";
-    parameter EMAC0_RXVLAN_ENABLE = "FALSE";
-    parameter EMAC0_RX_ENABLE = "FALSE";
-    parameter EMAC0_SGMII_ENABLE = "FALSE";
-    parameter EMAC0_SPEED_LSB = "FALSE";
-    parameter EMAC0_SPEED_MSB = "FALSE";
-    parameter EMAC0_TX16BITCLIENT_ENABLE = "FALSE";
-    parameter EMAC0_TXFLOWCTRL_ENABLE = "FALSE";
-    parameter EMAC0_TXHALFDUPLEX = "FALSE";
-    parameter EMAC0_TXIFGADJUST_ENABLE = "FALSE";
-    parameter EMAC0_TXINBANDFCS_ENABLE = "FALSE";
-    parameter EMAC0_TXJUMBOFRAME_ENABLE = "FALSE";
-    parameter EMAC0_TXRESET = "FALSE";
-    parameter EMAC0_TXVLAN_ENABLE = "FALSE";
-    parameter EMAC0_TX_ENABLE = "FALSE";
-    parameter EMAC0_UNIDIRECTION_ENABLE = "FALSE";
-    parameter EMAC0_USECLKEN = "FALSE";
-    parameter EMAC1_1000BASEX_ENABLE = "FALSE";
-    parameter EMAC1_ADDRFILTER_ENABLE = "FALSE";
-    parameter EMAC1_BYTEPHY = "FALSE";
-    parameter EMAC1_CONFIGVEC_79 = "FALSE";
-    parameter EMAC1_GTLOOPBACK = "FALSE";
-    parameter EMAC1_HOST_ENABLE = "FALSE";
-    parameter EMAC1_LTCHECK_DISABLE = "FALSE";
-    parameter EMAC1_MDIO_ENABLE = "FALSE";
-    parameter EMAC1_PHYINITAUTONEG_ENABLE = "FALSE";
-    parameter EMAC1_PHYISOLATE = "FALSE";
-    parameter EMAC1_PHYLOOPBACKMSB = "FALSE";
-    parameter EMAC1_PHYPOWERDOWN = "FALSE";
-    parameter EMAC1_PHYRESET = "FALSE";
-    parameter EMAC1_RGMII_ENABLE = "FALSE";
-    parameter EMAC1_RX16BITCLIENT_ENABLE = "FALSE";
-    parameter EMAC1_RXFLOWCTRL_ENABLE = "FALSE";
-    parameter EMAC1_RXHALFDUPLEX = "FALSE";
-    parameter EMAC1_RXINBANDFCS_ENABLE = "FALSE";
-    parameter EMAC1_RXJUMBOFRAME_ENABLE = "FALSE";
-    parameter EMAC1_RXRESET = "FALSE";
-    parameter EMAC1_RXVLAN_ENABLE = "FALSE";
-    parameter EMAC1_RX_ENABLE = "FALSE";
-    parameter EMAC1_SGMII_ENABLE = "FALSE";
-    parameter EMAC1_SPEED_LSB = "FALSE";
-    parameter EMAC1_SPEED_MSB = "FALSE";
-    parameter EMAC1_TX16BITCLIENT_ENABLE = "FALSE";
-    parameter EMAC1_TXFLOWCTRL_ENABLE = "FALSE";
-    parameter EMAC1_TXHALFDUPLEX = "FALSE";
-    parameter EMAC1_TXIFGADJUST_ENABLE = "FALSE";
-    parameter EMAC1_TXINBANDFCS_ENABLE = "FALSE";
-    parameter EMAC1_TXJUMBOFRAME_ENABLE = "FALSE";
-    parameter EMAC1_TXRESET = "FALSE";
-    parameter EMAC1_TXVLAN_ENABLE = "FALSE";
-    parameter EMAC1_TX_ENABLE = "FALSE";
-    parameter EMAC1_UNIDIRECTION_ENABLE = "FALSE";
-    parameter EMAC1_USECLKEN = "FALSE";
-    parameter [0:7] EMAC0_DCRBASEADDR = 8'h00;
-    parameter [0:7] EMAC1_DCRBASEADDR = 8'h00;
-    parameter [47:0] EMAC0_PAUSEADDR = 48'h000000000000;
-    parameter [47:0] EMAC0_UNICASTADDR = 48'h000000000000;
-    parameter [47:0] EMAC1_PAUSEADDR = 48'h000000000000;
-    parameter [47:0] EMAC1_UNICASTADDR = 48'h000000000000;
-    parameter [8:0] EMAC0_LINKTIMERVAL = 9'h000;
-    parameter [8:0] EMAC1_LINKTIMERVAL = 9'h000;
-    output DCRHOSTDONEIR;
-    output EMAC0CLIENTANINTERRUPT;
-    output EMAC0CLIENTRXBADFRAME;
-    output EMAC0CLIENTRXCLIENTCLKOUT;
-    output EMAC0CLIENTRXDVLD;
-    output EMAC0CLIENTRXDVLDMSW;
-    output EMAC0CLIENTRXFRAMEDROP;
-    output EMAC0CLIENTRXGOODFRAME;
-    output EMAC0CLIENTRXSTATSBYTEVLD;
-    output EMAC0CLIENTRXSTATSVLD;
-    output EMAC0CLIENTTXACK;
-    output EMAC0CLIENTTXCLIENTCLKOUT;
-    output EMAC0CLIENTTXCOLLISION;
-    output EMAC0CLIENTTXRETRANSMIT;
-    output EMAC0CLIENTTXSTATS;
-    output EMAC0CLIENTTXSTATSBYTEVLD;
-    output EMAC0CLIENTTXSTATSVLD;
-    output EMAC0PHYENCOMMAALIGN;
-    output EMAC0PHYLOOPBACKMSB;
-    output EMAC0PHYMCLKOUT;
-    output EMAC0PHYMDOUT;
-    output EMAC0PHYMDTRI;
-    output EMAC0PHYMGTRXRESET;
-    output EMAC0PHYMGTTXRESET;
-    output EMAC0PHYPOWERDOWN;
-    output EMAC0PHYSYNCACQSTATUS;
-    output EMAC0PHYTXCHARDISPMODE;
-    output EMAC0PHYTXCHARDISPVAL;
-    output EMAC0PHYTXCHARISK;
-    output EMAC0PHYTXCLK;
-    output EMAC0PHYTXEN;
-    output EMAC0PHYTXER;
-    output EMAC0PHYTXGMIIMIICLKOUT;
-    output EMAC0SPEEDIS10100;
-    output EMAC1CLIENTANINTERRUPT;
-    output EMAC1CLIENTRXBADFRAME;
-    output EMAC1CLIENTRXCLIENTCLKOUT;
-    output EMAC1CLIENTRXDVLD;
-    output EMAC1CLIENTRXDVLDMSW;
-    output EMAC1CLIENTRXFRAMEDROP;
-    output EMAC1CLIENTRXGOODFRAME;
-    output EMAC1CLIENTRXSTATSBYTEVLD;
-    output EMAC1CLIENTRXSTATSVLD;
-    output EMAC1CLIENTTXACK;
-    output EMAC1CLIENTTXCLIENTCLKOUT;
-    output EMAC1CLIENTTXCOLLISION;
-    output EMAC1CLIENTTXRETRANSMIT;
-    output EMAC1CLIENTTXSTATS;
-    output EMAC1CLIENTTXSTATSBYTEVLD;
-    output EMAC1CLIENTTXSTATSVLD;
-    output EMAC1PHYENCOMMAALIGN;
-    output EMAC1PHYLOOPBACKMSB;
-    output EMAC1PHYMCLKOUT;
-    output EMAC1PHYMDOUT;
-    output EMAC1PHYMDTRI;
-    output EMAC1PHYMGTRXRESET;
-    output EMAC1PHYMGTTXRESET;
-    output EMAC1PHYPOWERDOWN;
-    output EMAC1PHYSYNCACQSTATUS;
-    output EMAC1PHYTXCHARDISPMODE;
-    output EMAC1PHYTXCHARDISPVAL;
-    output EMAC1PHYTXCHARISK;
-    output EMAC1PHYTXCLK;
-    output EMAC1PHYTXEN;
-    output EMAC1PHYTXER;
-    output EMAC1PHYTXGMIIMIICLKOUT;
-    output EMAC1SPEEDIS10100;
-    output EMACDCRACK;
-    output HOSTMIIMRDY;
-    output [0:31] EMACDCRDBUS;
-    output [15:0] EMAC0CLIENTRXD;
-    output [15:0] EMAC1CLIENTRXD;
-    output [31:0] HOSTRDDATA;
-    output [6:0] EMAC0CLIENTRXSTATS;
-    output [6:0] EMAC1CLIENTRXSTATS;
-    output [7:0] EMAC0PHYTXD;
-    output [7:0] EMAC1PHYTXD;
-    input CLIENTEMAC0DCMLOCKED;
-    input CLIENTEMAC0PAUSEREQ;
-    input CLIENTEMAC0RXCLIENTCLKIN;
-    input CLIENTEMAC0TXCLIENTCLKIN;
-    input CLIENTEMAC0TXDVLD;
-    input CLIENTEMAC0TXDVLDMSW;
-    input CLIENTEMAC0TXFIRSTBYTE;
-    input CLIENTEMAC0TXUNDERRUN;
-    input CLIENTEMAC1DCMLOCKED;
-    input CLIENTEMAC1PAUSEREQ;
-    input CLIENTEMAC1RXCLIENTCLKIN;
-    input CLIENTEMAC1TXCLIENTCLKIN;
-    input CLIENTEMAC1TXDVLD;
-    input CLIENTEMAC1TXDVLDMSW;
-    input CLIENTEMAC1TXFIRSTBYTE;
-    input CLIENTEMAC1TXUNDERRUN;
-    input DCREMACCLK;
-    input DCREMACENABLE;
-    input DCREMACREAD;
-    input DCREMACWRITE;
-    input HOSTCLK;
-    input HOSTEMAC1SEL;
-    input HOSTMIIMSEL;
-    input HOSTREQ;
-    input PHYEMAC0COL;
-    input PHYEMAC0CRS;
-    input PHYEMAC0GTXCLK;
-    input PHYEMAC0MCLKIN;
-    input PHYEMAC0MDIN;
-    input PHYEMAC0MIITXCLK;
-    input PHYEMAC0RXBUFERR;
-    input PHYEMAC0RXCHARISCOMMA;
-    input PHYEMAC0RXCHARISK;
-    input PHYEMAC0RXCHECKINGCRC;
-    input PHYEMAC0RXCLK;
-    input PHYEMAC0RXCOMMADET;
-    input PHYEMAC0RXDISPERR;
-    input PHYEMAC0RXDV;
-    input PHYEMAC0RXER;
-    input PHYEMAC0RXNOTINTABLE;
-    input PHYEMAC0RXRUNDISP;
-    input PHYEMAC0SIGNALDET;
-    input PHYEMAC0TXBUFERR;
-    input PHYEMAC0TXGMIIMIICLKIN;
-    input PHYEMAC1COL;
-    input PHYEMAC1CRS;
-    input PHYEMAC1GTXCLK;
-    input PHYEMAC1MCLKIN;
-    input PHYEMAC1MDIN;
-    input PHYEMAC1MIITXCLK;
-    input PHYEMAC1RXBUFERR;
-    input PHYEMAC1RXCHARISCOMMA;
-    input PHYEMAC1RXCHARISK;
-    input PHYEMAC1RXCHECKINGCRC;
-    input PHYEMAC1RXCLK;
-    input PHYEMAC1RXCOMMADET;
-    input PHYEMAC1RXDISPERR;
-    input PHYEMAC1RXDV;
-    input PHYEMAC1RXER;
-    input PHYEMAC1RXNOTINTABLE;
-    input PHYEMAC1RXRUNDISP;
-    input PHYEMAC1SIGNALDET;
-    input PHYEMAC1TXBUFERR;
-    input PHYEMAC1TXGMIIMIICLKIN;
-    input RESET;
-    input [0:31] DCREMACDBUS;
-    input [0:9] DCREMACABUS;
-    input [15:0] CLIENTEMAC0PAUSEVAL;
-    input [15:0] CLIENTEMAC0TXD;
-    input [15:0] CLIENTEMAC1PAUSEVAL;
-    input [15:0] CLIENTEMAC1TXD;
-    input [1:0] HOSTOPCODE;
-    input [1:0] PHYEMAC0RXBUFSTATUS;
-    input [1:0] PHYEMAC0RXLOSSOFSYNC;
-    input [1:0] PHYEMAC1RXBUFSTATUS;
-    input [1:0] PHYEMAC1RXLOSSOFSYNC;
-    input [2:0] PHYEMAC0RXCLKCORCNT;
-    input [2:0] PHYEMAC1RXCLKCORCNT;
-    input [31:0] HOSTWRDATA;
-    input [4:0] PHYEMAC0PHYAD;
-    input [4:0] PHYEMAC1PHYAD;
-    input [7:0] CLIENTEMAC0TXIFGDELAY;
-    input [7:0] CLIENTEMAC1TXIFGDELAY;
-    input [7:0] PHYEMAC0RXD;
-    input [7:0] PHYEMAC1RXD;
-    input [9:0] HOSTADDR;
-endmodule
-
-module TEMAC_SINGLE (...);
-    parameter EMAC_1000BASEX_ENABLE = "FALSE";
-    parameter EMAC_ADDRFILTER_ENABLE = "FALSE";
-    parameter EMAC_BYTEPHY = "FALSE";
-    parameter EMAC_CTRLLENCHECK_DISABLE = "FALSE";
-    parameter [0:7] EMAC_DCRBASEADDR = 8'h00;
-    parameter EMAC_GTLOOPBACK = "FALSE";
-    parameter EMAC_HOST_ENABLE = "FALSE";
-    parameter [8:0] EMAC_LINKTIMERVAL = 9'h000;
-    parameter EMAC_LTCHECK_DISABLE = "FALSE";
-    parameter EMAC_MDIO_ENABLE = "FALSE";
-    parameter EMAC_MDIO_IGNORE_PHYADZERO = "FALSE";
-    parameter [47:0] EMAC_PAUSEADDR = 48'h000000000000;
-    parameter EMAC_PHYINITAUTONEG_ENABLE = "FALSE";
-    parameter EMAC_PHYISOLATE = "FALSE";
-    parameter EMAC_PHYLOOPBACKMSB = "FALSE";
-    parameter EMAC_PHYPOWERDOWN = "FALSE";
-    parameter EMAC_PHYRESET = "FALSE";
-    parameter EMAC_RGMII_ENABLE = "FALSE";
-    parameter EMAC_RX16BITCLIENT_ENABLE = "FALSE";
-    parameter EMAC_RXFLOWCTRL_ENABLE = "FALSE";
-    parameter EMAC_RXHALFDUPLEX = "FALSE";
-    parameter EMAC_RXINBANDFCS_ENABLE = "FALSE";
-    parameter EMAC_RXJUMBOFRAME_ENABLE = "FALSE";
-    parameter EMAC_RXRESET = "FALSE";
-    parameter EMAC_RXVLAN_ENABLE = "FALSE";
-    parameter EMAC_RX_ENABLE = "TRUE";
-    parameter EMAC_SGMII_ENABLE = "FALSE";
-    parameter EMAC_SPEED_LSB = "FALSE";
-    parameter EMAC_SPEED_MSB = "FALSE";
-    parameter EMAC_TX16BITCLIENT_ENABLE = "FALSE";
-    parameter EMAC_TXFLOWCTRL_ENABLE = "FALSE";
-    parameter EMAC_TXHALFDUPLEX = "FALSE";
-    parameter EMAC_TXIFGADJUST_ENABLE = "FALSE";
-    parameter EMAC_TXINBANDFCS_ENABLE = "FALSE";
-    parameter EMAC_TXJUMBOFRAME_ENABLE = "FALSE";
-    parameter EMAC_TXRESET = "FALSE";
-    parameter EMAC_TXVLAN_ENABLE = "FALSE";
-    parameter EMAC_TX_ENABLE = "TRUE";
-    parameter [47:0] EMAC_UNICASTADDR = 48'h000000000000;
-    parameter EMAC_UNIDIRECTION_ENABLE = "FALSE";
-    parameter EMAC_USECLKEN = "FALSE";
-    parameter SIM_VERSION = "1.0";
-    output DCRHOSTDONEIR;
-    output EMACCLIENTANINTERRUPT;
-    output EMACCLIENTRXBADFRAME;
-    output EMACCLIENTRXCLIENTCLKOUT;
-    output EMACCLIENTRXDVLD;
-    output EMACCLIENTRXDVLDMSW;
-    output EMACCLIENTRXFRAMEDROP;
-    output EMACCLIENTRXGOODFRAME;
-    output EMACCLIENTRXSTATSBYTEVLD;
-    output EMACCLIENTRXSTATSVLD;
-    output EMACCLIENTTXACK;
-    output EMACCLIENTTXCLIENTCLKOUT;
-    output EMACCLIENTTXCOLLISION;
-    output EMACCLIENTTXRETRANSMIT;
-    output EMACCLIENTTXSTATS;
-    output EMACCLIENTTXSTATSBYTEVLD;
-    output EMACCLIENTTXSTATSVLD;
-    output EMACDCRACK;
-    output EMACPHYENCOMMAALIGN;
-    output EMACPHYLOOPBACKMSB;
-    output EMACPHYMCLKOUT;
-    output EMACPHYMDOUT;
-    output EMACPHYMDTRI;
-    output EMACPHYMGTRXRESET;
-    output EMACPHYMGTTXRESET;
-    output EMACPHYPOWERDOWN;
-    output EMACPHYSYNCACQSTATUS;
-    output EMACPHYTXCHARDISPMODE;
-    output EMACPHYTXCHARDISPVAL;
-    output EMACPHYTXCHARISK;
-    output EMACPHYTXCLK;
-    output EMACPHYTXEN;
-    output EMACPHYTXER;
-    output EMACPHYTXGMIIMIICLKOUT;
-    output EMACSPEEDIS10100;
-    output HOSTMIIMRDY;
-    output [0:31] EMACDCRDBUS;
-    output [15:0] EMACCLIENTRXD;
-    output [31:0] HOSTRDDATA;
-    output [6:0] EMACCLIENTRXSTATS;
-    output [7:0] EMACPHYTXD;
-    input CLIENTEMACDCMLOCKED;
-    input CLIENTEMACPAUSEREQ;
-    input CLIENTEMACRXCLIENTCLKIN;
-    input CLIENTEMACTXCLIENTCLKIN;
-    input CLIENTEMACTXDVLD;
-    input CLIENTEMACTXDVLDMSW;
-    input CLIENTEMACTXFIRSTBYTE;
-    input CLIENTEMACTXUNDERRUN;
-    input DCREMACCLK;
-    input DCREMACENABLE;
-    input DCREMACREAD;
-    input DCREMACWRITE;
-    input HOSTCLK;
-    input HOSTMIIMSEL;
-    input HOSTREQ;
-    input PHYEMACCOL;
-    input PHYEMACCRS;
-    input PHYEMACGTXCLK;
-    input PHYEMACMCLKIN;
-    input PHYEMACMDIN;
-    input PHYEMACMIITXCLK;
-    input PHYEMACRXCHARISCOMMA;
-    input PHYEMACRXCHARISK;
-    input PHYEMACRXCLK;
-    input PHYEMACRXDISPERR;
-    input PHYEMACRXDV;
-    input PHYEMACRXER;
-    input PHYEMACRXNOTINTABLE;
-    input PHYEMACRXRUNDISP;
-    input PHYEMACSIGNALDET;
-    input PHYEMACTXBUFERR;
-    input PHYEMACTXGMIIMIICLKIN;
-    input RESET;
-    input [0:31] DCREMACDBUS;
-    input [0:9] DCREMACABUS;
-    input [15:0] CLIENTEMACPAUSEVAL;
-    input [15:0] CLIENTEMACTXD;
-    input [1:0] HOSTOPCODE;
-    input [1:0] PHYEMACRXBUFSTATUS;
-    input [2:0] PHYEMACRXCLKCORCNT;
-    input [31:0] HOSTWRDATA;
-    input [4:0] PHYEMACPHYAD;
-    input [7:0] CLIENTEMACTXIFGDELAY;
-    input [7:0] PHYEMACRXD;
-    input [9:0] HOSTADDR;
-endmodule
-
-module CMAC (...);
-    parameter CTL_PTP_TRANSPCLK_MODE = "FALSE";
-    parameter CTL_RX_CHECK_ACK = "TRUE";
-    parameter CTL_RX_CHECK_PREAMBLE = "FALSE";
-    parameter CTL_RX_CHECK_SFD = "FALSE";
-    parameter CTL_RX_DELETE_FCS = "TRUE";
-    parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808;
-    parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808;
-    parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808;
-    parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808;
-    parameter CTL_RX_FORWARD_CONTROL = "FALSE";
-    parameter CTL_RX_IGNORE_FCS = "FALSE";
-    parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580;
-    parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40;
-    parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001;
-    parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF;
-    parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF;
-    parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000;
-    parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000;
-    parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001;
-    parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001;
-    parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000;
-    parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000;
-    parameter CTL_RX_PROCESS_LFI = "FALSE";
-    parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF;
-    parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
-    parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
-    parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600;
-    parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
-    parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
-    parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
-    parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
-    parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
-    parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
-    parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800;
-    parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
-    parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
-    parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
-    parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
-    parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
-    parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
-    parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
-    parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
-    parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
-    parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
-    parameter CTL_TEST_MODE_PIN_CHAR = "FALSE";
-    parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001;
-    parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001;
-    parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808;
-    parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808;
-    parameter CTL_TX_FCS_INS_ENABLE = "TRUE";
-    parameter CTL_TX_IGNORE_FCS = "FALSE";
-    parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001;
-    parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001;
-    parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE";
-    parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1;
-    parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000;
-    parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000;
-    parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF;
-    parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
-    parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
-    parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600;
-    parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
-    parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
-    parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
-    parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
-    parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
-    parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
-    parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800;
-    parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
-    parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
-    parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
-    parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
-    parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
-    parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
-    parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
-    parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
-    parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
-    parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
-    parameter SIM_VERSION = "2.0";
-    parameter TEST_MODE_PIN_CHAR = "FALSE";
-    output [15:0] DRP_DO;
-    output DRP_RDY;
-    output [127:0] RX_DATAOUT0;
-    output [127:0] RX_DATAOUT1;
-    output [127:0] RX_DATAOUT2;
-    output [127:0] RX_DATAOUT3;
-    output RX_ENAOUT0;
-    output RX_ENAOUT1;
-    output RX_ENAOUT2;
-    output RX_ENAOUT3;
-    output RX_EOPOUT0;
-    output RX_EOPOUT1;
-    output RX_EOPOUT2;
-    output RX_EOPOUT3;
-    output RX_ERROUT0;
-    output RX_ERROUT1;
-    output RX_ERROUT2;
-    output RX_ERROUT3;
-    output [6:0] RX_LANE_ALIGNER_FILL_0;
-    output [6:0] RX_LANE_ALIGNER_FILL_1;
-    output [6:0] RX_LANE_ALIGNER_FILL_10;
-    output [6:0] RX_LANE_ALIGNER_FILL_11;
-    output [6:0] RX_LANE_ALIGNER_FILL_12;
-    output [6:0] RX_LANE_ALIGNER_FILL_13;
-    output [6:0] RX_LANE_ALIGNER_FILL_14;
-    output [6:0] RX_LANE_ALIGNER_FILL_15;
-    output [6:0] RX_LANE_ALIGNER_FILL_16;
-    output [6:0] RX_LANE_ALIGNER_FILL_17;
-    output [6:0] RX_LANE_ALIGNER_FILL_18;
-    output [6:0] RX_LANE_ALIGNER_FILL_19;
-    output [6:0] RX_LANE_ALIGNER_FILL_2;
-    output [6:0] RX_LANE_ALIGNER_FILL_3;
-    output [6:0] RX_LANE_ALIGNER_FILL_4;
-    output [6:0] RX_LANE_ALIGNER_FILL_5;
-    output [6:0] RX_LANE_ALIGNER_FILL_6;
-    output [6:0] RX_LANE_ALIGNER_FILL_7;
-    output [6:0] RX_LANE_ALIGNER_FILL_8;
-    output [6:0] RX_LANE_ALIGNER_FILL_9;
-    output [3:0] RX_MTYOUT0;
-    output [3:0] RX_MTYOUT1;
-    output [3:0] RX_MTYOUT2;
-    output [3:0] RX_MTYOUT3;
-    output [4:0] RX_PTP_PCSLANE_OUT;
-    output [79:0] RX_PTP_TSTAMP_OUT;
-    output RX_SOPOUT0;
-    output RX_SOPOUT1;
-    output RX_SOPOUT2;
-    output RX_SOPOUT3;
-    output STAT_RX_ALIGNED;
-    output STAT_RX_ALIGNED_ERR;
-    output [6:0] STAT_RX_BAD_CODE;
-    output [3:0] STAT_RX_BAD_FCS;
-    output STAT_RX_BAD_PREAMBLE;
-    output STAT_RX_BAD_SFD;
-    output STAT_RX_BIP_ERR_0;
-    output STAT_RX_BIP_ERR_1;
-    output STAT_RX_BIP_ERR_10;
-    output STAT_RX_BIP_ERR_11;
-    output STAT_RX_BIP_ERR_12;
-    output STAT_RX_BIP_ERR_13;
-    output STAT_RX_BIP_ERR_14;
-    output STAT_RX_BIP_ERR_15;
-    output STAT_RX_BIP_ERR_16;
-    output STAT_RX_BIP_ERR_17;
-    output STAT_RX_BIP_ERR_18;
-    output STAT_RX_BIP_ERR_19;
-    output STAT_RX_BIP_ERR_2;
-    output STAT_RX_BIP_ERR_3;
-    output STAT_RX_BIP_ERR_4;
-    output STAT_RX_BIP_ERR_5;
-    output STAT_RX_BIP_ERR_6;
-    output STAT_RX_BIP_ERR_7;
-    output STAT_RX_BIP_ERR_8;
-    output STAT_RX_BIP_ERR_9;
-    output [19:0] STAT_RX_BLOCK_LOCK;
-    output STAT_RX_BROADCAST;
-    output [3:0] STAT_RX_FRAGMENT;
-    output [3:0] STAT_RX_FRAMING_ERR_0;
-    output [3:0] STAT_RX_FRAMING_ERR_1;
-    output [3:0] STAT_RX_FRAMING_ERR_10;
-    output [3:0] STAT_RX_FRAMING_ERR_11;
-    output [3:0] STAT_RX_FRAMING_ERR_12;
-    output [3:0] STAT_RX_FRAMING_ERR_13;
-    output [3:0] STAT_RX_FRAMING_ERR_14;
-    output [3:0] STAT_RX_FRAMING_ERR_15;
-    output [3:0] STAT_RX_FRAMING_ERR_16;
-    output [3:0] STAT_RX_FRAMING_ERR_17;
-    output [3:0] STAT_RX_FRAMING_ERR_18;
-    output [3:0] STAT_RX_FRAMING_ERR_19;
-    output [3:0] STAT_RX_FRAMING_ERR_2;
-    output [3:0] STAT_RX_FRAMING_ERR_3;
-    output [3:0] STAT_RX_FRAMING_ERR_4;
-    output [3:0] STAT_RX_FRAMING_ERR_5;
-    output [3:0] STAT_RX_FRAMING_ERR_6;
-    output [3:0] STAT_RX_FRAMING_ERR_7;
-    output [3:0] STAT_RX_FRAMING_ERR_8;
-    output [3:0] STAT_RX_FRAMING_ERR_9;
-    output STAT_RX_FRAMING_ERR_VALID_0;
-    output STAT_RX_FRAMING_ERR_VALID_1;
-    output STAT_RX_FRAMING_ERR_VALID_10;
-    output STAT_RX_FRAMING_ERR_VALID_11;
-    output STAT_RX_FRAMING_ERR_VALID_12;
-    output STAT_RX_FRAMING_ERR_VALID_13;
-    output STAT_RX_FRAMING_ERR_VALID_14;
-    output STAT_RX_FRAMING_ERR_VALID_15;
-    output STAT_RX_FRAMING_ERR_VALID_16;
-    output STAT_RX_FRAMING_ERR_VALID_17;
-    output STAT_RX_FRAMING_ERR_VALID_18;
-    output STAT_RX_FRAMING_ERR_VALID_19;
-    output STAT_RX_FRAMING_ERR_VALID_2;
-    output STAT_RX_FRAMING_ERR_VALID_3;
-    output STAT_RX_FRAMING_ERR_VALID_4;
-    output STAT_RX_FRAMING_ERR_VALID_5;
-    output STAT_RX_FRAMING_ERR_VALID_6;
-    output STAT_RX_FRAMING_ERR_VALID_7;
-    output STAT_RX_FRAMING_ERR_VALID_8;
-    output STAT_RX_FRAMING_ERR_VALID_9;
-    output STAT_RX_GOT_SIGNAL_OS;
-    output STAT_RX_HI_BER;
-    output STAT_RX_INRANGEERR;
-    output STAT_RX_INTERNAL_LOCAL_FAULT;
-    output STAT_RX_JABBER;
-    output [7:0] STAT_RX_LANE0_VLM_BIP7;
-    output STAT_RX_LANE0_VLM_BIP7_VALID;
-    output STAT_RX_LOCAL_FAULT;
-    output [19:0] STAT_RX_MF_ERR;
-    output [19:0] STAT_RX_MF_LEN_ERR;
-    output [19:0] STAT_RX_MF_REPEAT_ERR;
-    output STAT_RX_MISALIGNED;
-    output STAT_RX_MULTICAST;
-    output STAT_RX_OVERSIZE;
-    output STAT_RX_PACKET_1024_1518_BYTES;
-    output STAT_RX_PACKET_128_255_BYTES;
-    output STAT_RX_PACKET_1519_1522_BYTES;
-    output STAT_RX_PACKET_1523_1548_BYTES;
-    output STAT_RX_PACKET_1549_2047_BYTES;
-    output STAT_RX_PACKET_2048_4095_BYTES;
-    output STAT_RX_PACKET_256_511_BYTES;
-    output STAT_RX_PACKET_4096_8191_BYTES;
-    output STAT_RX_PACKET_512_1023_BYTES;
-    output STAT_RX_PACKET_64_BYTES;
-    output STAT_RX_PACKET_65_127_BYTES;
-    output STAT_RX_PACKET_8192_9215_BYTES;
-    output STAT_RX_PACKET_BAD_FCS;
-    output STAT_RX_PACKET_LARGE;
-    output [3:0] STAT_RX_PACKET_SMALL;
-    output STAT_RX_PAUSE;
-    output [15:0] STAT_RX_PAUSE_QUANTA0;
-    output [15:0] STAT_RX_PAUSE_QUANTA1;
-    output [15:0] STAT_RX_PAUSE_QUANTA2;
-    output [15:0] STAT_RX_PAUSE_QUANTA3;
-    output [15:0] STAT_RX_PAUSE_QUANTA4;
-    output [15:0] STAT_RX_PAUSE_QUANTA5;
-    output [15:0] STAT_RX_PAUSE_QUANTA6;
-    output [15:0] STAT_RX_PAUSE_QUANTA7;
-    output [15:0] STAT_RX_PAUSE_QUANTA8;
-    output [8:0] STAT_RX_PAUSE_REQ;
-    output [8:0] STAT_RX_PAUSE_VALID;
-    output STAT_RX_RECEIVED_LOCAL_FAULT;
-    output STAT_RX_REMOTE_FAULT;
-    output STAT_RX_STATUS;
-    output [3:0] STAT_RX_STOMPED_FCS;
-    output [19:0] STAT_RX_SYNCED;
-    output [19:0] STAT_RX_SYNCED_ERR;
-    output [2:0] STAT_RX_TEST_PATTERN_MISMATCH;
-    output STAT_RX_TOOLONG;
-    output [7:0] STAT_RX_TOTAL_BYTES;
-    output [13:0] STAT_RX_TOTAL_GOOD_BYTES;
-    output STAT_RX_TOTAL_GOOD_PACKETS;
-    output [3:0] STAT_RX_TOTAL_PACKETS;
-    output STAT_RX_TRUNCATED;
-    output [3:0] STAT_RX_UNDERSIZE;
-    output STAT_RX_UNICAST;
-    output STAT_RX_USER_PAUSE;
-    output STAT_RX_VLAN;
-    output [19:0] STAT_RX_VL_DEMUXED;
-    output [4:0] STAT_RX_VL_NUMBER_0;
-    output [4:0] STAT_RX_VL_NUMBER_1;
-    output [4:0] STAT_RX_VL_NUMBER_10;
-    output [4:0] STAT_RX_VL_NUMBER_11;
-    output [4:0] STAT_RX_VL_NUMBER_12;
-    output [4:0] STAT_RX_VL_NUMBER_13;
-    output [4:0] STAT_RX_VL_NUMBER_14;
-    output [4:0] STAT_RX_VL_NUMBER_15;
-    output [4:0] STAT_RX_VL_NUMBER_16;
-    output [4:0] STAT_RX_VL_NUMBER_17;
-    output [4:0] STAT_RX_VL_NUMBER_18;
-    output [4:0] STAT_RX_VL_NUMBER_19;
-    output [4:0] STAT_RX_VL_NUMBER_2;
-    output [4:0] STAT_RX_VL_NUMBER_3;
-    output [4:0] STAT_RX_VL_NUMBER_4;
-    output [4:0] STAT_RX_VL_NUMBER_5;
-    output [4:0] STAT_RX_VL_NUMBER_6;
-    output [4:0] STAT_RX_VL_NUMBER_7;
-    output [4:0] STAT_RX_VL_NUMBER_8;
-    output [4:0] STAT_RX_VL_NUMBER_9;
-    output STAT_TX_BAD_FCS;
-    output STAT_TX_BROADCAST;
-    output STAT_TX_FRAME_ERROR;
-    output STAT_TX_LOCAL_FAULT;
-    output STAT_TX_MULTICAST;
-    output STAT_TX_PACKET_1024_1518_BYTES;
-    output STAT_TX_PACKET_128_255_BYTES;
-    output STAT_TX_PACKET_1519_1522_BYTES;
-    output STAT_TX_PACKET_1523_1548_BYTES;
-    output STAT_TX_PACKET_1549_2047_BYTES;
-    output STAT_TX_PACKET_2048_4095_BYTES;
-    output STAT_TX_PACKET_256_511_BYTES;
-    output STAT_TX_PACKET_4096_8191_BYTES;
-    output STAT_TX_PACKET_512_1023_BYTES;
-    output STAT_TX_PACKET_64_BYTES;
-    output STAT_TX_PACKET_65_127_BYTES;
-    output STAT_TX_PACKET_8192_9215_BYTES;
-    output STAT_TX_PACKET_LARGE;
-    output STAT_TX_PACKET_SMALL;
-    output STAT_TX_PAUSE;
-    output [8:0] STAT_TX_PAUSE_VALID;
-    output STAT_TX_PTP_FIFO_READ_ERROR;
-    output STAT_TX_PTP_FIFO_WRITE_ERROR;
-    output [6:0] STAT_TX_TOTAL_BYTES;
-    output [13:0] STAT_TX_TOTAL_GOOD_BYTES;
-    output STAT_TX_TOTAL_GOOD_PACKETS;
-    output STAT_TX_TOTAL_PACKETS;
-    output STAT_TX_UNICAST;
-    output STAT_TX_USER_PAUSE;
-    output STAT_TX_VLAN;
-    output TX_OVFOUT;
-    output [4:0] TX_PTP_PCSLANE_OUT;
-    output [79:0] TX_PTP_TSTAMP_OUT;
-    output [15:0] TX_PTP_TSTAMP_TAG_OUT;
-    output TX_PTP_TSTAMP_VALID_OUT;
-    output TX_RDYOUT;
-    output [15:0] TX_SERDES_ALT_DATA0;
-    output [15:0] TX_SERDES_ALT_DATA1;
-    output [15:0] TX_SERDES_ALT_DATA2;
-    output [15:0] TX_SERDES_ALT_DATA3;
-    output [63:0] TX_SERDES_DATA0;
-    output [63:0] TX_SERDES_DATA1;
-    output [63:0] TX_SERDES_DATA2;
-    output [63:0] TX_SERDES_DATA3;
-    output [31:0] TX_SERDES_DATA4;
-    output [31:0] TX_SERDES_DATA5;
-    output [31:0] TX_SERDES_DATA6;
-    output [31:0] TX_SERDES_DATA7;
-    output [31:0] TX_SERDES_DATA8;
-    output [31:0] TX_SERDES_DATA9;
-    output TX_UNFOUT;
-    input CTL_CAUI4_MODE;
-    input CTL_RX_CHECK_ETYPE_GCP;
-    input CTL_RX_CHECK_ETYPE_GPP;
-    input CTL_RX_CHECK_ETYPE_PCP;
-    input CTL_RX_CHECK_ETYPE_PPP;
-    input CTL_RX_CHECK_MCAST_GCP;
-    input CTL_RX_CHECK_MCAST_GPP;
-    input CTL_RX_CHECK_MCAST_PCP;
-    input CTL_RX_CHECK_MCAST_PPP;
-    input CTL_RX_CHECK_OPCODE_GCP;
-    input CTL_RX_CHECK_OPCODE_GPP;
-    input CTL_RX_CHECK_OPCODE_PCP;
-    input CTL_RX_CHECK_OPCODE_PPP;
-    input CTL_RX_CHECK_SA_GCP;
-    input CTL_RX_CHECK_SA_GPP;
-    input CTL_RX_CHECK_SA_PCP;
-    input CTL_RX_CHECK_SA_PPP;
-    input CTL_RX_CHECK_UCAST_GCP;
-    input CTL_RX_CHECK_UCAST_GPP;
-    input CTL_RX_CHECK_UCAST_PCP;
-    input CTL_RX_CHECK_UCAST_PPP;
-    input CTL_RX_ENABLE;
-    input CTL_RX_ENABLE_GCP;
-    input CTL_RX_ENABLE_GPP;
-    input CTL_RX_ENABLE_PCP;
-    input CTL_RX_ENABLE_PPP;
-    input CTL_RX_FORCE_RESYNC;
-    input [8:0] CTL_RX_PAUSE_ACK;
-    input [8:0] CTL_RX_PAUSE_ENABLE;
-    input [79:0] CTL_RX_SYSTEMTIMERIN;
-    input CTL_RX_TEST_PATTERN;
-    input CTL_TX_ENABLE;
-    input CTL_TX_LANE0_VLM_BIP7_OVERRIDE;
-    input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE;
-    input [8:0] CTL_TX_PAUSE_ENABLE;
-    input [15:0] CTL_TX_PAUSE_QUANTA0;
-    input [15:0] CTL_TX_PAUSE_QUANTA1;
-    input [15:0] CTL_TX_PAUSE_QUANTA2;
-    input [15:0] CTL_TX_PAUSE_QUANTA3;
-    input [15:0] CTL_TX_PAUSE_QUANTA4;
-    input [15:0] CTL_TX_PAUSE_QUANTA5;
-    input [15:0] CTL_TX_PAUSE_QUANTA6;
-    input [15:0] CTL_TX_PAUSE_QUANTA7;
-    input [15:0] CTL_TX_PAUSE_QUANTA8;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8;
-    input [8:0] CTL_TX_PAUSE_REQ;
-    input CTL_TX_PTP_VLANE_ADJUST_MODE;
-    input CTL_TX_RESEND_PAUSE;
-    input CTL_TX_SEND_IDLE;
-    input CTL_TX_SEND_RFI;
-    input [79:0] CTL_TX_SYSTEMTIMERIN;
-    input CTL_TX_TEST_PATTERN;
-    input [9:0] DRP_ADDR;
-    input DRP_CLK;
-    input [15:0] DRP_DI;
-    input DRP_EN;
-    input DRP_WE;
-    input RX_CLK;
-    input RX_RESET;
-    input [15:0] RX_SERDES_ALT_DATA0;
-    input [15:0] RX_SERDES_ALT_DATA1;
-    input [15:0] RX_SERDES_ALT_DATA2;
-    input [15:0] RX_SERDES_ALT_DATA3;
-    input [9:0] RX_SERDES_CLK;
-    input [63:0] RX_SERDES_DATA0;
-    input [63:0] RX_SERDES_DATA1;
-    input [63:0] RX_SERDES_DATA2;
-    input [63:0] RX_SERDES_DATA3;
-    input [31:0] RX_SERDES_DATA4;
-    input [31:0] RX_SERDES_DATA5;
-    input [31:0] RX_SERDES_DATA6;
-    input [31:0] RX_SERDES_DATA7;
-    input [31:0] RX_SERDES_DATA8;
-    input [31:0] RX_SERDES_DATA9;
-    input [9:0] RX_SERDES_RESET;
-    input TX_CLK;
-    input [127:0] TX_DATAIN0;
-    input [127:0] TX_DATAIN1;
-    input [127:0] TX_DATAIN2;
-    input [127:0] TX_DATAIN3;
-    input TX_ENAIN0;
-    input TX_ENAIN1;
-    input TX_ENAIN2;
-    input TX_ENAIN3;
-    input TX_EOPIN0;
-    input TX_EOPIN1;
-    input TX_EOPIN2;
-    input TX_EOPIN3;
-    input TX_ERRIN0;
-    input TX_ERRIN1;
-    input TX_ERRIN2;
-    input TX_ERRIN3;
-    input [3:0] TX_MTYIN0;
-    input [3:0] TX_MTYIN1;
-    input [3:0] TX_MTYIN2;
-    input [3:0] TX_MTYIN3;
-    input [1:0] TX_PTP_1588OP_IN;
-    input [15:0] TX_PTP_CHKSUM_OFFSET_IN;
-    input [63:0] TX_PTP_RXTSTAMP_IN;
-    input [15:0] TX_PTP_TAG_FIELD_IN;
-    input [15:0] TX_PTP_TSTAMP_OFFSET_IN;
-    input TX_PTP_UPD_CHKSUM_IN;
-    input TX_RESET;
-    input TX_SOPIN0;
-    input TX_SOPIN1;
-    input TX_SOPIN2;
-    input TX_SOPIN3;
-endmodule
-
-module CMACE4 (...);
-    parameter CTL_PTP_TRANSPCLK_MODE = "FALSE";
-    parameter CTL_RX_CHECK_ACK = "TRUE";
-    parameter CTL_RX_CHECK_PREAMBLE = "FALSE";
-    parameter CTL_RX_CHECK_SFD = "FALSE";
-    parameter CTL_RX_DELETE_FCS = "TRUE";
-    parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808;
-    parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808;
-    parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808;
-    parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808;
-    parameter CTL_RX_FORWARD_CONTROL = "FALSE";
-    parameter CTL_RX_IGNORE_FCS = "FALSE";
-    parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580;
-    parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40;
-    parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001;
-    parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF;
-    parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF;
-    parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000;
-    parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000;
-    parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001;
-    parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001;
-    parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000;
-    parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000;
-    parameter CTL_RX_PROCESS_LFI = "FALSE";
-    parameter [8:0] CTL_RX_RSFEC_AM_THRESHOLD = 9'h046;
-    parameter [1:0] CTL_RX_RSFEC_FILL_ADJUST = 2'h0;
-    parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF;
-    parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
-    parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
-    parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600;
-    parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
-    parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
-    parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
-    parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
-    parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
-    parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
-    parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800;
-    parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
-    parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
-    parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
-    parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
-    parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
-    parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
-    parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
-    parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
-    parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
-    parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
-    parameter CTL_TEST_MODE_PIN_CHAR = "FALSE";
-    parameter CTL_TX_CUSTOM_PREAMBLE_ENABLE = "FALSE";
-    parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001;
-    parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001;
-    parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808;
-    parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808;
-    parameter CTL_TX_FCS_INS_ENABLE = "TRUE";
-    parameter CTL_TX_IGNORE_FCS = "FALSE";
-    parameter [3:0] CTL_TX_IPG_VALUE = 4'hC;
-    parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001;
-    parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001;
-    parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE";
-    parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1;
-    parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000;
-    parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000;
-    parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF;
-    parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
-    parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
-    parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600;
-    parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
-    parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
-    parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
-    parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
-    parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
-    parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
-    parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800;
-    parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
-    parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
-    parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
-    parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
-    parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
-    parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
-    parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
-    parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
-    parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
-    parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
-    parameter SIM_DEVICE = "ULTRASCALE_PLUS";
-    parameter TEST_MODE_PIN_CHAR = "FALSE";
-    output [15:0] DRP_DO;
-    output DRP_RDY;
-    output [329:0] RSFEC_BYPASS_RX_DOUT;
-    output RSFEC_BYPASS_RX_DOUT_CW_START;
-    output RSFEC_BYPASS_RX_DOUT_VALID;
-    output [329:0] RSFEC_BYPASS_TX_DOUT;
-    output RSFEC_BYPASS_TX_DOUT_CW_START;
-    output RSFEC_BYPASS_TX_DOUT_VALID;
-    output [127:0] RX_DATAOUT0;
-    output [127:0] RX_DATAOUT1;
-    output [127:0] RX_DATAOUT2;
-    output [127:0] RX_DATAOUT3;
-    output RX_ENAOUT0;
-    output RX_ENAOUT1;
-    output RX_ENAOUT2;
-    output RX_ENAOUT3;
-    output RX_EOPOUT0;
-    output RX_EOPOUT1;
-    output RX_EOPOUT2;
-    output RX_EOPOUT3;
-    output RX_ERROUT0;
-    output RX_ERROUT1;
-    output RX_ERROUT2;
-    output RX_ERROUT3;
-    output [6:0] RX_LANE_ALIGNER_FILL_0;
-    output [6:0] RX_LANE_ALIGNER_FILL_1;
-    output [6:0] RX_LANE_ALIGNER_FILL_10;
-    output [6:0] RX_LANE_ALIGNER_FILL_11;
-    output [6:0] RX_LANE_ALIGNER_FILL_12;
-    output [6:0] RX_LANE_ALIGNER_FILL_13;
-    output [6:0] RX_LANE_ALIGNER_FILL_14;
-    output [6:0] RX_LANE_ALIGNER_FILL_15;
-    output [6:0] RX_LANE_ALIGNER_FILL_16;
-    output [6:0] RX_LANE_ALIGNER_FILL_17;
-    output [6:0] RX_LANE_ALIGNER_FILL_18;
-    output [6:0] RX_LANE_ALIGNER_FILL_19;
-    output [6:0] RX_LANE_ALIGNER_FILL_2;
-    output [6:0] RX_LANE_ALIGNER_FILL_3;
-    output [6:0] RX_LANE_ALIGNER_FILL_4;
-    output [6:0] RX_LANE_ALIGNER_FILL_5;
-    output [6:0] RX_LANE_ALIGNER_FILL_6;
-    output [6:0] RX_LANE_ALIGNER_FILL_7;
-    output [6:0] RX_LANE_ALIGNER_FILL_8;
-    output [6:0] RX_LANE_ALIGNER_FILL_9;
-    output [3:0] RX_MTYOUT0;
-    output [3:0] RX_MTYOUT1;
-    output [3:0] RX_MTYOUT2;
-    output [3:0] RX_MTYOUT3;
-    output [7:0] RX_OTN_BIP8_0;
-    output [7:0] RX_OTN_BIP8_1;
-    output [7:0] RX_OTN_BIP8_2;
-    output [7:0] RX_OTN_BIP8_3;
-    output [7:0] RX_OTN_BIP8_4;
-    output [65:0] RX_OTN_DATA_0;
-    output [65:0] RX_OTN_DATA_1;
-    output [65:0] RX_OTN_DATA_2;
-    output [65:0] RX_OTN_DATA_3;
-    output [65:0] RX_OTN_DATA_4;
-    output RX_OTN_ENA;
-    output RX_OTN_LANE0;
-    output RX_OTN_VLMARKER;
-    output [55:0] RX_PREOUT;
-    output [4:0] RX_PTP_PCSLANE_OUT;
-    output [79:0] RX_PTP_TSTAMP_OUT;
-    output RX_SOPOUT0;
-    output RX_SOPOUT1;
-    output RX_SOPOUT2;
-    output RX_SOPOUT3;
-    output STAT_RX_ALIGNED;
-    output STAT_RX_ALIGNED_ERR;
-    output [2:0] STAT_RX_BAD_CODE;
-    output [2:0] STAT_RX_BAD_FCS;
-    output STAT_RX_BAD_PREAMBLE;
-    output STAT_RX_BAD_SFD;
-    output STAT_RX_BIP_ERR_0;
-    output STAT_RX_BIP_ERR_1;
-    output STAT_RX_BIP_ERR_10;
-    output STAT_RX_BIP_ERR_11;
-    output STAT_RX_BIP_ERR_12;
-    output STAT_RX_BIP_ERR_13;
-    output STAT_RX_BIP_ERR_14;
-    output STAT_RX_BIP_ERR_15;
-    output STAT_RX_BIP_ERR_16;
-    output STAT_RX_BIP_ERR_17;
-    output STAT_RX_BIP_ERR_18;
-    output STAT_RX_BIP_ERR_19;
-    output STAT_RX_BIP_ERR_2;
-    output STAT_RX_BIP_ERR_3;
-    output STAT_RX_BIP_ERR_4;
-    output STAT_RX_BIP_ERR_5;
-    output STAT_RX_BIP_ERR_6;
-    output STAT_RX_BIP_ERR_7;
-    output STAT_RX_BIP_ERR_8;
-    output STAT_RX_BIP_ERR_9;
-    output [19:0] STAT_RX_BLOCK_LOCK;
-    output STAT_RX_BROADCAST;
-    output [2:0] STAT_RX_FRAGMENT;
-    output [1:0] STAT_RX_FRAMING_ERR_0;
-    output [1:0] STAT_RX_FRAMING_ERR_1;
-    output [1:0] STAT_RX_FRAMING_ERR_10;
-    output [1:0] STAT_RX_FRAMING_ERR_11;
-    output [1:0] STAT_RX_FRAMING_ERR_12;
-    output [1:0] STAT_RX_FRAMING_ERR_13;
-    output [1:0] STAT_RX_FRAMING_ERR_14;
-    output [1:0] STAT_RX_FRAMING_ERR_15;
-    output [1:0] STAT_RX_FRAMING_ERR_16;
-    output [1:0] STAT_RX_FRAMING_ERR_17;
-    output [1:0] STAT_RX_FRAMING_ERR_18;
-    output [1:0] STAT_RX_FRAMING_ERR_19;
-    output [1:0] STAT_RX_FRAMING_ERR_2;
-    output [1:0] STAT_RX_FRAMING_ERR_3;
-    output [1:0] STAT_RX_FRAMING_ERR_4;
-    output [1:0] STAT_RX_FRAMING_ERR_5;
-    output [1:0] STAT_RX_FRAMING_ERR_6;
-    output [1:0] STAT_RX_FRAMING_ERR_7;
-    output [1:0] STAT_RX_FRAMING_ERR_8;
-    output [1:0] STAT_RX_FRAMING_ERR_9;
-    output STAT_RX_FRAMING_ERR_VALID_0;
-    output STAT_RX_FRAMING_ERR_VALID_1;
-    output STAT_RX_FRAMING_ERR_VALID_10;
-    output STAT_RX_FRAMING_ERR_VALID_11;
-    output STAT_RX_FRAMING_ERR_VALID_12;
-    output STAT_RX_FRAMING_ERR_VALID_13;
-    output STAT_RX_FRAMING_ERR_VALID_14;
-    output STAT_RX_FRAMING_ERR_VALID_15;
-    output STAT_RX_FRAMING_ERR_VALID_16;
-    output STAT_RX_FRAMING_ERR_VALID_17;
-    output STAT_RX_FRAMING_ERR_VALID_18;
-    output STAT_RX_FRAMING_ERR_VALID_19;
-    output STAT_RX_FRAMING_ERR_VALID_2;
-    output STAT_RX_FRAMING_ERR_VALID_3;
-    output STAT_RX_FRAMING_ERR_VALID_4;
-    output STAT_RX_FRAMING_ERR_VALID_5;
-    output STAT_RX_FRAMING_ERR_VALID_6;
-    output STAT_RX_FRAMING_ERR_VALID_7;
-    output STAT_RX_FRAMING_ERR_VALID_8;
-    output STAT_RX_FRAMING_ERR_VALID_9;
-    output STAT_RX_GOT_SIGNAL_OS;
-    output STAT_RX_HI_BER;
-    output STAT_RX_INRANGEERR;
-    output STAT_RX_INTERNAL_LOCAL_FAULT;
-    output STAT_RX_JABBER;
-    output [7:0] STAT_RX_LANE0_VLM_BIP7;
-    output STAT_RX_LANE0_VLM_BIP7_VALID;
-    output STAT_RX_LOCAL_FAULT;
-    output [19:0] STAT_RX_MF_ERR;
-    output [19:0] STAT_RX_MF_LEN_ERR;
-    output [19:0] STAT_RX_MF_REPEAT_ERR;
-    output STAT_RX_MISALIGNED;
-    output STAT_RX_MULTICAST;
-    output STAT_RX_OVERSIZE;
-    output STAT_RX_PACKET_1024_1518_BYTES;
-    output STAT_RX_PACKET_128_255_BYTES;
-    output STAT_RX_PACKET_1519_1522_BYTES;
-    output STAT_RX_PACKET_1523_1548_BYTES;
-    output STAT_RX_PACKET_1549_2047_BYTES;
-    output STAT_RX_PACKET_2048_4095_BYTES;
-    output STAT_RX_PACKET_256_511_BYTES;
-    output STAT_RX_PACKET_4096_8191_BYTES;
-    output STAT_RX_PACKET_512_1023_BYTES;
-    output STAT_RX_PACKET_64_BYTES;
-    output STAT_RX_PACKET_65_127_BYTES;
-    output STAT_RX_PACKET_8192_9215_BYTES;
-    output STAT_RX_PACKET_BAD_FCS;
-    output STAT_RX_PACKET_LARGE;
-    output [2:0] STAT_RX_PACKET_SMALL;
-    output STAT_RX_PAUSE;
-    output [15:0] STAT_RX_PAUSE_QUANTA0;
-    output [15:0] STAT_RX_PAUSE_QUANTA1;
-    output [15:0] STAT_RX_PAUSE_QUANTA2;
-    output [15:0] STAT_RX_PAUSE_QUANTA3;
-    output [15:0] STAT_RX_PAUSE_QUANTA4;
-    output [15:0] STAT_RX_PAUSE_QUANTA5;
-    output [15:0] STAT_RX_PAUSE_QUANTA6;
-    output [15:0] STAT_RX_PAUSE_QUANTA7;
-    output [15:0] STAT_RX_PAUSE_QUANTA8;
-    output [8:0] STAT_RX_PAUSE_REQ;
-    output [8:0] STAT_RX_PAUSE_VALID;
-    output STAT_RX_RECEIVED_LOCAL_FAULT;
-    output STAT_RX_REMOTE_FAULT;
-    output STAT_RX_RSFEC_AM_LOCK0;
-    output STAT_RX_RSFEC_AM_LOCK1;
-    output STAT_RX_RSFEC_AM_LOCK2;
-    output STAT_RX_RSFEC_AM_LOCK3;
-    output STAT_RX_RSFEC_CORRECTED_CW_INC;
-    output STAT_RX_RSFEC_CW_INC;
-    output [2:0] STAT_RX_RSFEC_ERR_COUNT0_INC;
-    output [2:0] STAT_RX_RSFEC_ERR_COUNT1_INC;
-    output [2:0] STAT_RX_RSFEC_ERR_COUNT2_INC;
-    output [2:0] STAT_RX_RSFEC_ERR_COUNT3_INC;
-    output STAT_RX_RSFEC_HI_SER;
-    output STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS;
-    output [13:0] STAT_RX_RSFEC_LANE_FILL_0;
-    output [13:0] STAT_RX_RSFEC_LANE_FILL_1;
-    output [13:0] STAT_RX_RSFEC_LANE_FILL_2;
-    output [13:0] STAT_RX_RSFEC_LANE_FILL_3;
-    output [7:0] STAT_RX_RSFEC_LANE_MAPPING;
-    output [31:0] STAT_RX_RSFEC_RSVD;
-    output STAT_RX_RSFEC_UNCORRECTED_CW_INC;
-    output STAT_RX_STATUS;
-    output [2:0] STAT_RX_STOMPED_FCS;
-    output [19:0] STAT_RX_SYNCED;
-    output [19:0] STAT_RX_SYNCED_ERR;
-    output [2:0] STAT_RX_TEST_PATTERN_MISMATCH;
-    output STAT_RX_TOOLONG;
-    output [6:0] STAT_RX_TOTAL_BYTES;
-    output [13:0] STAT_RX_TOTAL_GOOD_BYTES;
-    output STAT_RX_TOTAL_GOOD_PACKETS;
-    output [2:0] STAT_RX_TOTAL_PACKETS;
-    output STAT_RX_TRUNCATED;
-    output [2:0] STAT_RX_UNDERSIZE;
-    output STAT_RX_UNICAST;
-    output STAT_RX_USER_PAUSE;
-    output STAT_RX_VLAN;
-    output [19:0] STAT_RX_VL_DEMUXED;
-    output [4:0] STAT_RX_VL_NUMBER_0;
-    output [4:0] STAT_RX_VL_NUMBER_1;
-    output [4:0] STAT_RX_VL_NUMBER_10;
-    output [4:0] STAT_RX_VL_NUMBER_11;
-    output [4:0] STAT_RX_VL_NUMBER_12;
-    output [4:0] STAT_RX_VL_NUMBER_13;
-    output [4:0] STAT_RX_VL_NUMBER_14;
-    output [4:0] STAT_RX_VL_NUMBER_15;
-    output [4:0] STAT_RX_VL_NUMBER_16;
-    output [4:0] STAT_RX_VL_NUMBER_17;
-    output [4:0] STAT_RX_VL_NUMBER_18;
-    output [4:0] STAT_RX_VL_NUMBER_19;
-    output [4:0] STAT_RX_VL_NUMBER_2;
-    output [4:0] STAT_RX_VL_NUMBER_3;
-    output [4:0] STAT_RX_VL_NUMBER_4;
-    output [4:0] STAT_RX_VL_NUMBER_5;
-    output [4:0] STAT_RX_VL_NUMBER_6;
-    output [4:0] STAT_RX_VL_NUMBER_7;
-    output [4:0] STAT_RX_VL_NUMBER_8;
-    output [4:0] STAT_RX_VL_NUMBER_9;
-    output STAT_TX_BAD_FCS;
-    output STAT_TX_BROADCAST;
-    output STAT_TX_FRAME_ERROR;
-    output STAT_TX_LOCAL_FAULT;
-    output STAT_TX_MULTICAST;
-    output STAT_TX_PACKET_1024_1518_BYTES;
-    output STAT_TX_PACKET_128_255_BYTES;
-    output STAT_TX_PACKET_1519_1522_BYTES;
-    output STAT_TX_PACKET_1523_1548_BYTES;
-    output STAT_TX_PACKET_1549_2047_BYTES;
-    output STAT_TX_PACKET_2048_4095_BYTES;
-    output STAT_TX_PACKET_256_511_BYTES;
-    output STAT_TX_PACKET_4096_8191_BYTES;
-    output STAT_TX_PACKET_512_1023_BYTES;
-    output STAT_TX_PACKET_64_BYTES;
-    output STAT_TX_PACKET_65_127_BYTES;
-    output STAT_TX_PACKET_8192_9215_BYTES;
-    output STAT_TX_PACKET_LARGE;
-    output STAT_TX_PACKET_SMALL;
-    output STAT_TX_PAUSE;
-    output [8:0] STAT_TX_PAUSE_VALID;
-    output STAT_TX_PTP_FIFO_READ_ERROR;
-    output STAT_TX_PTP_FIFO_WRITE_ERROR;
-    output [5:0] STAT_TX_TOTAL_BYTES;
-    output [13:0] STAT_TX_TOTAL_GOOD_BYTES;
-    output STAT_TX_TOTAL_GOOD_PACKETS;
-    output STAT_TX_TOTAL_PACKETS;
-    output STAT_TX_UNICAST;
-    output STAT_TX_USER_PAUSE;
-    output STAT_TX_VLAN;
-    output TX_OVFOUT;
-    output [4:0] TX_PTP_PCSLANE_OUT;
-    output [79:0] TX_PTP_TSTAMP_OUT;
-    output [15:0] TX_PTP_TSTAMP_TAG_OUT;
-    output TX_PTP_TSTAMP_VALID_OUT;
-    output TX_RDYOUT;
-    output [15:0] TX_SERDES_ALT_DATA0;
-    output [15:0] TX_SERDES_ALT_DATA1;
-    output [15:0] TX_SERDES_ALT_DATA2;
-    output [15:0] TX_SERDES_ALT_DATA3;
-    output [63:0] TX_SERDES_DATA0;
-    output [63:0] TX_SERDES_DATA1;
-    output [63:0] TX_SERDES_DATA2;
-    output [63:0] TX_SERDES_DATA3;
-    output [31:0] TX_SERDES_DATA4;
-    output [31:0] TX_SERDES_DATA5;
-    output [31:0] TX_SERDES_DATA6;
-    output [31:0] TX_SERDES_DATA7;
-    output [31:0] TX_SERDES_DATA8;
-    output [31:0] TX_SERDES_DATA9;
-    output TX_UNFOUT;
-    input CTL_CAUI4_MODE;
-    input CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE;
-    input CTL_RSFEC_IEEE_ERROR_INDICATION_MODE;
-    input CTL_RX_CHECK_ETYPE_GCP;
-    input CTL_RX_CHECK_ETYPE_GPP;
-    input CTL_RX_CHECK_ETYPE_PCP;
-    input CTL_RX_CHECK_ETYPE_PPP;
-    input CTL_RX_CHECK_MCAST_GCP;
-    input CTL_RX_CHECK_MCAST_GPP;
-    input CTL_RX_CHECK_MCAST_PCP;
-    input CTL_RX_CHECK_MCAST_PPP;
-    input CTL_RX_CHECK_OPCODE_GCP;
-    input CTL_RX_CHECK_OPCODE_GPP;
-    input CTL_RX_CHECK_OPCODE_PCP;
-    input CTL_RX_CHECK_OPCODE_PPP;
-    input CTL_RX_CHECK_SA_GCP;
-    input CTL_RX_CHECK_SA_GPP;
-    input CTL_RX_CHECK_SA_PCP;
-    input CTL_RX_CHECK_SA_PPP;
-    input CTL_RX_CHECK_UCAST_GCP;
-    input CTL_RX_CHECK_UCAST_GPP;
-    input CTL_RX_CHECK_UCAST_PCP;
-    input CTL_RX_CHECK_UCAST_PPP;
-    input CTL_RX_ENABLE;
-    input CTL_RX_ENABLE_GCP;
-    input CTL_RX_ENABLE_GPP;
-    input CTL_RX_ENABLE_PCP;
-    input CTL_RX_ENABLE_PPP;
-    input CTL_RX_FORCE_RESYNC;
-    input [8:0] CTL_RX_PAUSE_ACK;
-    input [8:0] CTL_RX_PAUSE_ENABLE;
-    input CTL_RX_RSFEC_ENABLE;
-    input CTL_RX_RSFEC_ENABLE_CORRECTION;
-    input CTL_RX_RSFEC_ENABLE_INDICATION;
-    input [79:0] CTL_RX_SYSTEMTIMERIN;
-    input CTL_RX_TEST_PATTERN;
-    input CTL_TX_ENABLE;
-    input CTL_TX_LANE0_VLM_BIP7_OVERRIDE;
-    input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE;
-    input [8:0] CTL_TX_PAUSE_ENABLE;
-    input [15:0] CTL_TX_PAUSE_QUANTA0;
-    input [15:0] CTL_TX_PAUSE_QUANTA1;
-    input [15:0] CTL_TX_PAUSE_QUANTA2;
-    input [15:0] CTL_TX_PAUSE_QUANTA3;
-    input [15:0] CTL_TX_PAUSE_QUANTA4;
-    input [15:0] CTL_TX_PAUSE_QUANTA5;
-    input [15:0] CTL_TX_PAUSE_QUANTA6;
-    input [15:0] CTL_TX_PAUSE_QUANTA7;
-    input [15:0] CTL_TX_PAUSE_QUANTA8;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7;
-    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8;
-    input [8:0] CTL_TX_PAUSE_REQ;
-    input CTL_TX_PTP_VLANE_ADJUST_MODE;
-    input CTL_TX_RESEND_PAUSE;
-    input CTL_TX_RSFEC_ENABLE;
-    input CTL_TX_SEND_IDLE;
-    input CTL_TX_SEND_LFI;
-    input CTL_TX_SEND_RFI;
-    input [79:0] CTL_TX_SYSTEMTIMERIN;
-    input CTL_TX_TEST_PATTERN;
-    input [9:0] DRP_ADDR;
-    input DRP_CLK;
-    input [15:0] DRP_DI;
-    input DRP_EN;
-    input DRP_WE;
-    input [329:0] RSFEC_BYPASS_RX_DIN;
-    input RSFEC_BYPASS_RX_DIN_CW_START;
-    input [329:0] RSFEC_BYPASS_TX_DIN;
-    input RSFEC_BYPASS_TX_DIN_CW_START;
-    input RX_CLK;
-    input RX_RESET;
-    input [15:0] RX_SERDES_ALT_DATA0;
-    input [15:0] RX_SERDES_ALT_DATA1;
-    input [15:0] RX_SERDES_ALT_DATA2;
-    input [15:0] RX_SERDES_ALT_DATA3;
-    input [9:0] RX_SERDES_CLK;
-    input [63:0] RX_SERDES_DATA0;
-    input [63:0] RX_SERDES_DATA1;
-    input [63:0] RX_SERDES_DATA2;
-    input [63:0] RX_SERDES_DATA3;
-    input [31:0] RX_SERDES_DATA4;
-    input [31:0] RX_SERDES_DATA5;
-    input [31:0] RX_SERDES_DATA6;
-    input [31:0] RX_SERDES_DATA7;
-    input [31:0] RX_SERDES_DATA8;
-    input [31:0] RX_SERDES_DATA9;
-    input [9:0] RX_SERDES_RESET;
-    input TX_CLK;
-    input [127:0] TX_DATAIN0;
-    input [127:0] TX_DATAIN1;
-    input [127:0] TX_DATAIN2;
-    input [127:0] TX_DATAIN3;
-    input TX_ENAIN0;
-    input TX_ENAIN1;
-    input TX_ENAIN2;
-    input TX_ENAIN3;
-    input TX_EOPIN0;
-    input TX_EOPIN1;
-    input TX_EOPIN2;
-    input TX_EOPIN3;
-    input TX_ERRIN0;
-    input TX_ERRIN1;
-    input TX_ERRIN2;
-    input TX_ERRIN3;
-    input [3:0] TX_MTYIN0;
-    input [3:0] TX_MTYIN1;
-    input [3:0] TX_MTYIN2;
-    input [3:0] TX_MTYIN3;
-    input [55:0] TX_PREIN;
-    input [1:0] TX_PTP_1588OP_IN;
-    input [15:0] TX_PTP_CHKSUM_OFFSET_IN;
-    input [63:0] TX_PTP_RXTSTAMP_IN;
-    input [15:0] TX_PTP_TAG_FIELD_IN;
-    input [15:0] TX_PTP_TSTAMP_OFFSET_IN;
-    input TX_PTP_UPD_CHKSUM_IN;
-    input TX_RESET;
-    input TX_SOPIN0;
-    input TX_SOPIN1;
-    input TX_SOPIN2;
-    input TX_SOPIN3;
-endmodule
-
-module PPC405_ADV (...);
-    parameter in_delay=100;
-    parameter out_delay=100;
-    output APUFCMDECODED;
-    output APUFCMDECUDIVALID;
-    output APUFCMENDIAN;
-    output APUFCMFLUSH;
-    output APUFCMINSTRVALID;
-    output APUFCMLOADDVALID;
-    output APUFCMOPERANDVALID;
-    output APUFCMWRITEBACKOK;
-    output APUFCMXERCA;
-    output C405CPMCORESLEEPREQ;
-    output C405CPMMSRCE;
-    output C405CPMMSREE;
-    output C405CPMTIMERIRQ;
-    output C405CPMTIMERRESETREQ;
-    output C405DBGLOADDATAONAPUDBUS;
-    output C405DBGMSRWE;
-    output C405DBGSTOPACK;
-    output C405DBGWBCOMPLETE;
-    output C405DBGWBFULL;
-    output C405JTGCAPTUREDR;
-    output C405JTGEXTEST;
-    output C405JTGPGMOUT;
-    output C405JTGSHIFTDR;
-    output C405JTGTDO;
-    output C405JTGTDOEN;
-    output C405JTGUPDATEDR;
-    output C405PLBDCUABORT;
-    output C405PLBDCUCACHEABLE;
-    output C405PLBDCUGUARDED;
-    output C405PLBDCUREQUEST;
-    output C405PLBDCURNW;
-    output C405PLBDCUSIZE2;
-    output C405PLBDCUU0ATTR;
-    output C405PLBDCUWRITETHRU;
-    output C405PLBICUABORT;
-    output C405PLBICUCACHEABLE;
-    output C405PLBICUREQUEST;
-    output C405PLBICUU0ATTR;
-    output C405RSTCHIPRESETREQ;
-    output C405RSTCORERESETREQ;
-    output C405RSTSYSRESETREQ;
-    output C405TRCCYCLE;
-    output C405TRCTRIGGEREVENTOUT;
-    output C405XXXMACHINECHECK;
-    output DCREMACCLK;
-    output DCREMACENABLER;
-    output DCREMACREAD;
-    output DCREMACWRITE;
-    output DSOCMBRAMEN;
-    output DSOCMBUSY;
-    output DSOCMRDADDRVALID;
-    output DSOCMWRADDRVALID;
-    output EXTDCRREAD;
-    output EXTDCRWRITE;
-    output ISOCMBRAMEN;
-    output ISOCMBRAMEVENWRITEEN;
-    output ISOCMBRAMODDWRITEEN;
-    output ISOCMDCRBRAMEVENEN;
-    output ISOCMDCRBRAMODDEN;
-    output ISOCMDCRBRAMRDSELECT;
-    output [0:10] C405TRCTRIGGEREVENTTYPE;
-    output [0:1] C405PLBDCUPRIORITY;
-    output [0:1] C405PLBICUPRIORITY;
-    output [0:1] C405TRCEVENEXECUTIONSTATUS;
-    output [0:1] C405TRCODDEXECUTIONSTATUS;
-    output [0:29] C405DBGWBIAR;
-    output [0:29] C405PLBICUABUS;
-    output [0:2] APUFCMDECUDI;
-    output [0:31] APUFCMINSTRUCTION;
-    output [0:31] APUFCMLOADDATA;
-    output [0:31] APUFCMRADATA;
-    output [0:31] APUFCMRBDATA;
-    output [0:31] C405PLBDCUABUS;
-    output [0:31] DCREMACDBUS;
-    output [0:31] DSOCMBRAMWRDBUS;
-    output [0:31] EXTDCRDBUSOUT;
-    output [0:31] ISOCMBRAMWRDBUS;
-    output [0:3] APUFCMLOADBYTEEN;
-    output [0:3] C405TRCTRACESTATUS;
-    output [0:3] DSOCMBRAMBYTEWRITE;
-    output [0:63] C405PLBDCUWRDBUS;
-    output [0:7] C405PLBDCUBE;
-    output [0:9] EXTDCRABUS;
-    output [2:3] C405PLBICUSIZE;
-    output [8:28] ISOCMBRAMRDABUS;
-    output [8:28] ISOCMBRAMWRABUS;
-    output [8:29] DSOCMBRAMABUS;
-    output [8:9] DCREMACABUS;
-    input BRAMDSOCMCLK;
-    input BRAMISOCMCLK;
-    input CPMC405CLOCK;
-    input CPMC405CORECLKINACTIVE;
-    input CPMC405CPUCLKEN;
-    input CPMC405JTAGCLKEN;
-    input CPMC405SYNCBYPASS;
-    input CPMC405TIMERCLKEN;
-    input CPMC405TIMERTICK;
-    input CPMDCRCLK;
-    input CPMFCMCLK;
-    input DBGC405DEBUGHALT;
-    input DBGC405EXTBUSHOLDACK;
-    input DBGC405UNCONDDEBUGEVENT;
-    input DSOCMRWCOMPLETE;
-    input EICC405CRITINPUTIRQ;
-    input EICC405EXTINPUTIRQ;
-    input EMACDCRACK;
-    input EXTDCRACK;
-    input FCMAPUDCDCREN;
-    input FCMAPUDCDFORCEALIGN;
-    input FCMAPUDCDFORCEBESTEERING;
-    input FCMAPUDCDFPUOP;
-    input FCMAPUDCDGPRWRITE;
-    input FCMAPUDCDLDSTBYTE;
-    input FCMAPUDCDLDSTDW;
-    input FCMAPUDCDLDSTHW;
-    input FCMAPUDCDLDSTQW;
-    input FCMAPUDCDLDSTWD;
-    input FCMAPUDCDLOAD;
-    input FCMAPUDCDPRIVOP;
-    input FCMAPUDCDRAEN;
-    input FCMAPUDCDRBEN;
-    input FCMAPUDCDSTORE;
-    input FCMAPUDCDTRAPBE;
-    input FCMAPUDCDTRAPLE;
-    input FCMAPUDCDUPDATE;
-    input FCMAPUDCDXERCAEN;
-    input FCMAPUDCDXEROVEN;
-    input FCMAPUDECODEBUSY;
-    input FCMAPUDONE;
-    input FCMAPUEXCEPTION;
-    input FCMAPUEXEBLOCKINGMCO;
-    input FCMAPUEXENONBLOCKINGMCO;
-    input FCMAPUINSTRACK;
-    input FCMAPULOADWAIT;
-    input FCMAPURESULTVALID;
-    input FCMAPUSLEEPNOTREADY;
-    input FCMAPUXERCA;
-    input FCMAPUXEROV;
-    input JTGC405BNDSCANTDO;
-    input JTGC405TCK;
-    input JTGC405TDI;
-    input JTGC405TMS;
-    input JTGC405TRSTNEG;
-    input MCBCPUCLKEN;
-    input MCBJTAGEN;
-    input MCBTIMEREN;
-    input MCPPCRST;
-    input PLBC405DCUADDRACK;
-    input PLBC405DCUBUSY;
-    input PLBC405DCUERR;
-    input PLBC405DCURDDACK;
-    input PLBC405DCUSSIZE1;
-    input PLBC405DCUWRDACK;
-    input PLBC405ICUADDRACK;
-    input PLBC405ICUBUSY;
-    input PLBC405ICUERR;
-    input PLBC405ICURDDACK;
-    input PLBC405ICUSSIZE1;
-    input PLBCLK;
-    input RSTC405RESETCHIP;
-    input RSTC405RESETCORE;
-    input RSTC405RESETSYS;
-    input TIEC405DETERMINISTICMULT;
-    input TIEC405DISOPERANDFWD;
-    input TIEC405MMUEN;
-    input TIEPVRBIT10;
-    input TIEPVRBIT11;
-    input TIEPVRBIT28;
-    input TIEPVRBIT29;
-    input TIEPVRBIT30;
-    input TIEPVRBIT31;
-    input TIEPVRBIT8;
-    input TIEPVRBIT9;
-    input TRCC405TRACEDISABLE;
-    input TRCC405TRIGGEREVENTIN;
-    input [0:15] TIEAPUCONTROL;
-    input [0:23] TIEAPUUDI1;
-    input [0:23] TIEAPUUDI2;
-    input [0:23] TIEAPUUDI3;
-    input [0:23] TIEAPUUDI4;
-    input [0:23] TIEAPUUDI5;
-    input [0:23] TIEAPUUDI6;
-    input [0:23] TIEAPUUDI7;
-    input [0:23] TIEAPUUDI8;
-    input [0:2] FCMAPUEXECRFIELD;
-    input [0:31] BRAMDSOCMRDDBUS;
-    input [0:31] BRAMISOCMDCRRDDBUS;
-    input [0:31] EMACDCRDBUS;
-    input [0:31] EXTDCRDBUSIN;
-    input [0:31] FCMAPURESULT;
-    input [0:3] FCMAPUCR;
-    input [0:5] TIEDCRADDR;
-    input [0:63] BRAMISOCMRDDBUS;
-    input [0:63] PLBC405DCURDDBUS;
-    input [0:63] PLBC405ICURDDBUS;
-    input [0:7] DSARCVALUE;
-    input [0:7] DSCNTLVALUE;
-    input [0:7] ISARCVALUE;
-    input [0:7] ISCNTLVALUE;
-    input [1:3] PLBC405DCURDWDADDR;
-    input [1:3] PLBC405ICURDWDADDR;
-endmodule
-
-module PPC440 (...);
-    parameter CLOCK_DELAY = "FALSE";
-    parameter DCR_AUTOLOCK_ENABLE = "TRUE";
-    parameter PPCDM_ASYNCMODE = "FALSE";
-    parameter PPCDS_ASYNCMODE = "FALSE";
-    parameter PPCS0_WIDTH_128N64 = "TRUE";
-    parameter PPCS1_WIDTH_128N64 = "TRUE";
-    parameter [0:16] APU_CONTROL = 17'h02000;
-    parameter [0:23] APU_UDI0 = 24'h000000;
-    parameter [0:23] APU_UDI1 = 24'h000000;
-    parameter [0:23] APU_UDI10 = 24'h000000;
-    parameter [0:23] APU_UDI11 = 24'h000000;
-    parameter [0:23] APU_UDI12 = 24'h000000;
-    parameter [0:23] APU_UDI13 = 24'h000000;
-    parameter [0:23] APU_UDI14 = 24'h000000;
-    parameter [0:23] APU_UDI15 = 24'h000000;
-    parameter [0:23] APU_UDI2 = 24'h000000;
-    parameter [0:23] APU_UDI3 = 24'h000000;
-    parameter [0:23] APU_UDI4 = 24'h000000;
-    parameter [0:23] APU_UDI5 = 24'h000000;
-    parameter [0:23] APU_UDI6 = 24'h000000;
-    parameter [0:23] APU_UDI7 = 24'h000000;
-    parameter [0:23] APU_UDI8 = 24'h000000;
-    parameter [0:23] APU_UDI9 = 24'h000000;
-    parameter [0:31] DMA0_RXCHANNELCTRL = 32'h01010000;
-    parameter [0:31] DMA0_TXCHANNELCTRL = 32'h01010000;
-    parameter [0:31] DMA1_RXCHANNELCTRL = 32'h01010000;
-    parameter [0:31] DMA1_TXCHANNELCTRL = 32'h01010000;
-    parameter [0:31] DMA2_RXCHANNELCTRL = 32'h01010000;
-    parameter [0:31] DMA2_TXCHANNELCTRL = 32'h01010000;
-    parameter [0:31] DMA3_RXCHANNELCTRL = 32'h01010000;
-    parameter [0:31] DMA3_TXCHANNELCTRL = 32'h01010000;
-    parameter [0:31] INTERCONNECT_IMASK = 32'hFFFFFFFF;
-    parameter [0:31] INTERCONNECT_TMPL_SEL = 32'h3FFFFFFF;
-    parameter [0:31] MI_ARBCONFIG = 32'h00432010;
-    parameter [0:31] MI_BANKCONFLICT_MASK = 32'h00000000;
-    parameter [0:31] MI_CONTROL = 32'h0000008F;
-    parameter [0:31] MI_ROWCONFLICT_MASK = 32'h00000000;
-    parameter [0:31] PPCM_ARBCONFIG = 32'h00432010;
-    parameter [0:31] PPCM_CONTROL = 32'h8000019F;
-    parameter [0:31] PPCM_COUNTER = 32'h00000500;
-    parameter [0:31] PPCS0_ADDRMAP_TMPL0 = 32'hFFFFFFFF;
-    parameter [0:31] PPCS0_ADDRMAP_TMPL1 = 32'hFFFFFFFF;
-    parameter [0:31] PPCS0_ADDRMAP_TMPL2 = 32'hFFFFFFFF;
-    parameter [0:31] PPCS0_ADDRMAP_TMPL3 = 32'hFFFFFFFF;
-    parameter [0:31] PPCS0_CONTROL = 32'h8033336C;
-    parameter [0:31] PPCS1_ADDRMAP_TMPL0 = 32'hFFFFFFFF;
-    parameter [0:31] PPCS1_ADDRMAP_TMPL1 = 32'hFFFFFFFF;
-    parameter [0:31] PPCS1_ADDRMAP_TMPL2 = 32'hFFFFFFFF;
-    parameter [0:31] PPCS1_ADDRMAP_TMPL3 = 32'hFFFFFFFF;
-    parameter [0:31] PPCS1_CONTROL = 32'h8033336C;
-    parameter [0:31] XBAR_ADDRMAP_TMPL0 = 32'hFFFF0000;
-    parameter [0:31] XBAR_ADDRMAP_TMPL1 = 32'h00000000;
-    parameter [0:31] XBAR_ADDRMAP_TMPL2 = 32'h00000000;
-    parameter [0:31] XBAR_ADDRMAP_TMPL3 = 32'h00000000;
-    parameter [0:7] DMA0_CONTROL = 8'h00;
-    parameter [0:7] DMA1_CONTROL = 8'h00;
-    parameter [0:7] DMA2_CONTROL = 8'h00;
-    parameter [0:7] DMA3_CONTROL = 8'h00;
-    parameter [0:9] DMA0_RXIRQTIMER = 10'h3FF;
-    parameter [0:9] DMA0_TXIRQTIMER = 10'h3FF;
-    parameter [0:9] DMA1_RXIRQTIMER = 10'h3FF;
-    parameter [0:9] DMA1_TXIRQTIMER = 10'h3FF;
-    parameter [0:9] DMA2_RXIRQTIMER = 10'h3FF;
-    parameter [0:9] DMA2_TXIRQTIMER = 10'h3FF;
-    parameter [0:9] DMA3_RXIRQTIMER = 10'h3FF;
-    parameter [0:9] DMA3_TXIRQTIMER = 10'h3FF;
-    output APUFCMDECFPUOP;
-    output APUFCMDECLOAD;
-    output APUFCMDECNONAUTON;
-    output APUFCMDECSTORE;
-    output APUFCMDECUDIVALID;
-    output APUFCMENDIAN;
-    output APUFCMFLUSH;
-    output APUFCMINSTRVALID;
-    output APUFCMLOADDVALID;
-    output APUFCMMSRFE0;
-    output APUFCMMSRFE1;
-    output APUFCMNEXTINSTRREADY;
-    output APUFCMOPERANDVALID;
-    output APUFCMWRITEBACKOK;
-    output C440CPMCORESLEEPREQ;
-    output C440CPMDECIRPTREQ;
-    output C440CPMFITIRPTREQ;
-    output C440CPMMSRCE;
-    output C440CPMMSREE;
-    output C440CPMTIMERRESETREQ;
-    output C440CPMWDIRPTREQ;
-    output C440JTGTDO;
-    output C440JTGTDOEN;
-    output C440MACHINECHECK;
-    output C440RSTCHIPRESETREQ;
-    output C440RSTCORERESETREQ;
-    output C440RSTSYSTEMRESETREQ;
-    output C440TRCCYCLE;
-    output C440TRCTRIGGEREVENTOUT;
-    output DMA0LLRSTENGINEACK;
-    output DMA0LLRXDSTRDYN;
-    output DMA0LLTXEOFN;
-    output DMA0LLTXEOPN;
-    output DMA0LLTXSOFN;
-    output DMA0LLTXSOPN;
-    output DMA0LLTXSRCRDYN;
-    output DMA0RXIRQ;
-    output DMA0TXIRQ;
-    output DMA1LLRSTENGINEACK;
-    output DMA1LLRXDSTRDYN;
-    output DMA1LLTXEOFN;
-    output DMA1LLTXEOPN;
-    output DMA1LLTXSOFN;
-    output DMA1LLTXSOPN;
-    output DMA1LLTXSRCRDYN;
-    output DMA1RXIRQ;
-    output DMA1TXIRQ;
-    output DMA2LLRSTENGINEACK;
-    output DMA2LLRXDSTRDYN;
-    output DMA2LLTXEOFN;
-    output DMA2LLTXEOPN;
-    output DMA2LLTXSOFN;
-    output DMA2LLTXSOPN;
-    output DMA2LLTXSRCRDYN;
-    output DMA2RXIRQ;
-    output DMA2TXIRQ;
-    output DMA3LLRSTENGINEACK;
-    output DMA3LLRXDSTRDYN;
-    output DMA3LLTXEOFN;
-    output DMA3LLTXEOPN;
-    output DMA3LLTXSOFN;
-    output DMA3LLTXSOPN;
-    output DMA3LLTXSRCRDYN;
-    output DMA3RXIRQ;
-    output DMA3TXIRQ;
-    output MIMCADDRESSVALID;
-    output MIMCBANKCONFLICT;
-    output MIMCREADNOTWRITE;
-    output MIMCROWCONFLICT;
-    output MIMCWRITEDATAVALID;
-    output PPCCPMINTERCONNECTBUSY;
-    output PPCDMDCRREAD;
-    output PPCDMDCRWRITE;
-    output PPCDSDCRACK;
-    output PPCDSDCRTIMEOUTWAIT;
-    output PPCEICINTERCONNECTIRQ;
-    output PPCMPLBABORT;
-    output PPCMPLBBUSLOCK;
-    output PPCMPLBLOCKERR;
-    output PPCMPLBRDBURST;
-    output PPCMPLBREQUEST;
-    output PPCMPLBRNW;
-    output PPCMPLBWRBURST;
-    output PPCS0PLBADDRACK;
-    output PPCS0PLBRDBTERM;
-    output PPCS0PLBRDCOMP;
-    output PPCS0PLBRDDACK;
-    output PPCS0PLBREARBITRATE;
-    output PPCS0PLBWAIT;
-    output PPCS0PLBWRBTERM;
-    output PPCS0PLBWRCOMP;
-    output PPCS0PLBWRDACK;
-    output PPCS1PLBADDRACK;
-    output PPCS1PLBRDBTERM;
-    output PPCS1PLBRDCOMP;
-    output PPCS1PLBRDDACK;
-    output PPCS1PLBREARBITRATE;
-    output PPCS1PLBWAIT;
-    output PPCS1PLBWRBTERM;
-    output PPCS1PLBWRCOMP;
-    output PPCS1PLBWRDACK;
-    output [0:127] APUFCMLOADDATA;
-    output [0:127] MIMCWRITEDATA;
-    output [0:127] PPCMPLBWRDBUS;
-    output [0:127] PPCS0PLBRDDBUS;
-    output [0:127] PPCS1PLBRDDBUS;
-    output [0:13] C440TRCTRIGGEREVENTTYPE;
-    output [0:15] MIMCBYTEENABLE;
-    output [0:15] PPCMPLBBE;
-    output [0:15] PPCMPLBTATTRIBUTE;
-    output [0:1] PPCMPLBPRIORITY;
-    output [0:1] PPCS0PLBSSIZE;
-    output [0:1] PPCS1PLBSSIZE;
-    output [0:2] APUFCMDECLDSTXFERSIZE;
-    output [0:2] C440TRCBRANCHSTATUS;
-    output [0:2] PPCMPLBTYPE;
-    output [0:31] APUFCMINSTRUCTION;
-    output [0:31] APUFCMRADATA;
-    output [0:31] APUFCMRBDATA;
-    output [0:31] DMA0LLTXD;
-    output [0:31] DMA1LLTXD;
-    output [0:31] DMA2LLTXD;
-    output [0:31] DMA3LLTXD;
-    output [0:31] PPCDMDCRDBUSOUT;
-    output [0:31] PPCDSDCRDBUSIN;
-    output [0:31] PPCMPLBABUS;
-    output [0:35] MIMCADDRESS;
-    output [0:3] APUFCMDECUDI;
-    output [0:3] APUFCMLOADBYTEADDR;
-    output [0:3] DMA0LLTXREM;
-    output [0:3] DMA1LLTXREM;
-    output [0:3] DMA2LLTXREM;
-    output [0:3] DMA3LLTXREM;
-    output [0:3] PPCMPLBSIZE;
-    output [0:3] PPCS0PLBMBUSY;
-    output [0:3] PPCS0PLBMIRQ;
-    output [0:3] PPCS0PLBMRDERR;
-    output [0:3] PPCS0PLBMWRERR;
-    output [0:3] PPCS0PLBRDWDADDR;
-    output [0:3] PPCS1PLBMBUSY;
-    output [0:3] PPCS1PLBMIRQ;
-    output [0:3] PPCS1PLBMRDERR;
-    output [0:3] PPCS1PLBMWRERR;
-    output [0:3] PPCS1PLBRDWDADDR;
-    output [0:4] C440TRCEXECUTIONSTATUS;
-    output [0:6] C440TRCTRACESTATUS;
-    output [0:7] C440DBGSYSTEMCONTROL;
-    output [0:9] PPCDMDCRABUS;
-    output [20:21] PPCDMDCRUABUS;
-    output [28:31] PPCMPLBUABUS;
-    input CPMC440CLK;
-    input CPMC440CLKEN;
-    input CPMC440CORECLOCKINACTIVE;
-    input CPMC440TIMERCLOCK;
-    input CPMDCRCLK;
-    input CPMDMA0LLCLK;
-    input CPMDMA1LLCLK;
-    input CPMDMA2LLCLK;
-    input CPMDMA3LLCLK;
-    input CPMFCMCLK;
-    input CPMINTERCONNECTCLK;
-    input CPMINTERCONNECTCLKEN;
-    input CPMINTERCONNECTCLKNTO1;
-    input CPMMCCLK;
-    input CPMPPCMPLBCLK;
-    input CPMPPCS0PLBCLK;
-    input CPMPPCS1PLBCLK;
-    input DBGC440DEBUGHALT;
-    input DBGC440UNCONDDEBUGEVENT;
-    input DCRPPCDMACK;
-    input DCRPPCDMTIMEOUTWAIT;
-    input DCRPPCDSREAD;
-    input DCRPPCDSWRITE;
-    input EICC440CRITIRQ;
-    input EICC440EXTIRQ;
-    input FCMAPUCONFIRMINSTR;
-    input FCMAPUDONE;
-    input FCMAPUEXCEPTION;
-    input FCMAPUFPSCRFEX;
-    input FCMAPURESULTVALID;
-    input FCMAPUSLEEPNOTREADY;
-    input JTGC440TCK;
-    input JTGC440TDI;
-    input JTGC440TMS;
-    input JTGC440TRSTNEG;
-    input LLDMA0RSTENGINEREQ;
-    input LLDMA0RXEOFN;
-    input LLDMA0RXEOPN;
-    input LLDMA0RXSOFN;
-    input LLDMA0RXSOPN;
-    input LLDMA0RXSRCRDYN;
-    input LLDMA0TXDSTRDYN;
-    input LLDMA1RSTENGINEREQ;
-    input LLDMA1RXEOFN;
-    input LLDMA1RXEOPN;
-    input LLDMA1RXSOFN;
-    input LLDMA1RXSOPN;
-    input LLDMA1RXSRCRDYN;
-    input LLDMA1TXDSTRDYN;
-    input LLDMA2RSTENGINEREQ;
-    input LLDMA2RXEOFN;
-    input LLDMA2RXEOPN;
-    input LLDMA2RXSOFN;
-    input LLDMA2RXSOPN;
-    input LLDMA2RXSRCRDYN;
-    input LLDMA2TXDSTRDYN;
-    input LLDMA3RSTENGINEREQ;
-    input LLDMA3RXEOFN;
-    input LLDMA3RXEOPN;
-    input LLDMA3RXSOFN;
-    input LLDMA3RXSOPN;
-    input LLDMA3RXSRCRDYN;
-    input LLDMA3TXDSTRDYN;
-    input MCMIADDRREADYTOACCEPT;
-    input MCMIREADDATAERR;
-    input MCMIREADDATAVALID;
-    input PLBPPCMADDRACK;
-    input PLBPPCMMBUSY;
-    input PLBPPCMMIRQ;
-    input PLBPPCMMRDERR;
-    input PLBPPCMMWRERR;
-    input PLBPPCMRDBTERM;
-    input PLBPPCMRDDACK;
-    input PLBPPCMRDPENDREQ;
-    input PLBPPCMREARBITRATE;
-    input PLBPPCMTIMEOUT;
-    input PLBPPCMWRBTERM;
-    input PLBPPCMWRDACK;
-    input PLBPPCMWRPENDREQ;
-    input PLBPPCS0ABORT;
-    input PLBPPCS0BUSLOCK;
-    input PLBPPCS0LOCKERR;
-    input PLBPPCS0PAVALID;
-    input PLBPPCS0RDBURST;
-    input PLBPPCS0RDPENDREQ;
-    input PLBPPCS0RDPRIM;
-    input PLBPPCS0RNW;
-    input PLBPPCS0SAVALID;
-    input PLBPPCS0WRBURST;
-    input PLBPPCS0WRPENDREQ;
-    input PLBPPCS0WRPRIM;
-    input PLBPPCS1ABORT;
-    input PLBPPCS1BUSLOCK;
-    input PLBPPCS1LOCKERR;
-    input PLBPPCS1PAVALID;
-    input PLBPPCS1RDBURST;
-    input PLBPPCS1RDPENDREQ;
-    input PLBPPCS1RDPRIM;
-    input PLBPPCS1RNW;
-    input PLBPPCS1SAVALID;
-    input PLBPPCS1WRBURST;
-    input PLBPPCS1WRPENDREQ;
-    input PLBPPCS1WRPRIM;
-    input RSTC440RESETCHIP;
-    input RSTC440RESETCORE;
-    input RSTC440RESETSYSTEM;
-    input TIEC440ENDIANRESET;
-    input TRCC440TRACEDISABLE;
-    input TRCC440TRIGGEREVENTIN;
-    input [0:127] FCMAPUSTOREDATA;
-    input [0:127] MCMIREADDATA;
-    input [0:127] PLBPPCMRDDBUS;
-    input [0:127] PLBPPCS0WRDBUS;
-    input [0:127] PLBPPCS1WRDBUS;
-    input [0:15] PLBPPCS0BE;
-    input [0:15] PLBPPCS0TATTRIBUTE;
-    input [0:15] PLBPPCS1BE;
-    input [0:15] PLBPPCS1TATTRIBUTE;
-    input [0:1] PLBPPCMRDPENDPRI;
-    input [0:1] PLBPPCMREQPRI;
-    input [0:1] PLBPPCMSSIZE;
-    input [0:1] PLBPPCMWRPENDPRI;
-    input [0:1] PLBPPCS0MASTERID;
-    input [0:1] PLBPPCS0MSIZE;
-    input [0:1] PLBPPCS0RDPENDPRI;
-    input [0:1] PLBPPCS0REQPRI;
-    input [0:1] PLBPPCS0WRPENDPRI;
-    input [0:1] PLBPPCS1MASTERID;
-    input [0:1] PLBPPCS1MSIZE;
-    input [0:1] PLBPPCS1RDPENDPRI;
-    input [0:1] PLBPPCS1REQPRI;
-    input [0:1] PLBPPCS1WRPENDPRI;
-    input [0:1] TIEC440DCURDLDCACHEPLBPRIO;
-    input [0:1] TIEC440DCURDNONCACHEPLBPRIO;
-    input [0:1] TIEC440DCURDTOUCHPLBPRIO;
-    input [0:1] TIEC440DCURDURGENTPLBPRIO;
-    input [0:1] TIEC440DCUWRFLUSHPLBPRIO;
-    input [0:1] TIEC440DCUWRSTOREPLBPRIO;
-    input [0:1] TIEC440DCUWRURGENTPLBPRIO;
-    input [0:1] TIEC440ICURDFETCHPLBPRIO;
-    input [0:1] TIEC440ICURDSPECPLBPRIO;
-    input [0:1] TIEC440ICURDTOUCHPLBPRIO;
-    input [0:1] TIEDCRBASEADDR;
-    input [0:2] PLBPPCS0TYPE;
-    input [0:2] PLBPPCS1TYPE;
-    input [0:31] DCRPPCDMDBUSIN;
-    input [0:31] DCRPPCDSDBUSOUT;
-    input [0:31] FCMAPURESULT;
-    input [0:31] LLDMA0RXD;
-    input [0:31] LLDMA1RXD;
-    input [0:31] LLDMA2RXD;
-    input [0:31] LLDMA3RXD;
-    input [0:31] PLBPPCS0ABUS;
-    input [0:31] PLBPPCS1ABUS;
-    input [0:3] FCMAPUCR;
-    input [0:3] LLDMA0RXREM;
-    input [0:3] LLDMA1RXREM;
-    input [0:3] LLDMA2RXREM;
-    input [0:3] LLDMA3RXREM;
-    input [0:3] PLBPPCMRDWDADDR;
-    input [0:3] PLBPPCS0SIZE;
-    input [0:3] PLBPPCS1SIZE;
-    input [0:3] TIEC440ERPNRESET;
-    input [0:3] TIEC440USERRESET;
-    input [0:4] DBGC440SYSTEMSTATUS;
-    input [0:9] DCRPPCDSABUS;
-    input [28:31] PLBPPCS0UABUS;
-    input [28:31] PLBPPCS1UABUS;
-    input [28:31] TIEC440PIR;
-    input [28:31] TIEC440PVR;
+module PCIE4CE4 (...);
+    parameter ARI_CAP_ENABLE = "FALSE";
+    parameter AUTO_FLR_RESPONSE = "FALSE";
+    parameter [7:0] AXISTEN_IF_CCIX_RX_CREDIT_LIMIT = 8'h08;
+    parameter [7:0] AXISTEN_IF_CCIX_TX_CREDIT_LIMIT = 8'h08;
+    parameter AXISTEN_IF_CCIX_TX_REGISTERED_TREADY = "FALSE";
+    parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0;
+    parameter [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0 = 24'hBEBC20;
+    parameter [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1 = 28'h2FAF080;
+    parameter [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE = 2'h0;
+    parameter AXISTEN_IF_CQ_EN_POISONED_MEM_WR = "FALSE";
+    parameter AXISTEN_IF_ENABLE_256_TAGS = "FALSE";
+    parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE";
+    parameter AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = "FALSE";
+    parameter AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK = "TRUE";
+    parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000;
+    parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE";
+    parameter AXISTEN_IF_EXT_512 = "FALSE";
+    parameter AXISTEN_IF_EXT_512_CC_STRADDLE = "FALSE";
+    parameter AXISTEN_IF_EXT_512_CQ_STRADDLE = "FALSE";
+    parameter AXISTEN_IF_EXT_512_RC_STRADDLE = "FALSE";
+    parameter AXISTEN_IF_EXT_512_RQ_STRADDLE = "FALSE";
+    parameter AXISTEN_IF_LEGACY_MODE_ENABLE = "FALSE";
+    parameter AXISTEN_IF_MSIX_FROM_RAM_PIPELINE = "FALSE";
+    parameter AXISTEN_IF_MSIX_RX_PARITY_EN = "TRUE";
+    parameter AXISTEN_IF_MSIX_TO_RAM_PIPELINE = "FALSE";
+    parameter [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE = 2'h0;
+    parameter AXISTEN_IF_RC_STRADDLE = "FALSE";
+    parameter [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE = 2'h0;
+    parameter AXISTEN_IF_RX_PARITY_EN = "TRUE";
+    parameter AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT = "FALSE";
+    parameter AXISTEN_IF_TX_PARITY_EN = "TRUE";
+    parameter [1:0] AXISTEN_IF_WIDTH = 2'h2;
+    parameter CCIX_DIRECT_ATTACH_MODE = "FALSE";
+    parameter CCIX_ENABLE = "FALSE";
+    parameter [15:0] CCIX_VENDOR_ID = 16'h0000;
+    parameter CFG_BYPASS_MODE_ENABLE = "FALSE";
+    parameter CRM_CORE_CLK_FREQ_500 = "TRUE";
+    parameter [1:0] CRM_USER_CLK_FREQ = 2'h2;
+    parameter [15:0] DEBUG_AXI4ST_SPARE = 16'h0000;
+    parameter [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT = 8'h00;
+    parameter [3:0] DEBUG_CAR_SPARE = 4'h0;
+    parameter [15:0] DEBUG_CFG_SPARE = 16'h0000;
+    parameter [15:0] DEBUG_LL_SPARE = 16'h0000;
+    parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR = "FALSE";
+    parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR = "FALSE";
+    parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR = "FALSE";
+    parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL = "FALSE";
+    parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW = "FALSE";
+    parameter DEBUG_PL_DISABLE_SCRAMBLING = "FALSE";
+    parameter DEBUG_PL_SIM_RESET_LFSR = "FALSE";
+    parameter [15:0] DEBUG_PL_SPARE = 16'h0000;
+    parameter DEBUG_TL_DISABLE_FC_TIMEOUT = "FALSE";
+    parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE";
+    parameter [15:0] DEBUG_TL_SPARE = 16'h0000;
+    parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
+    parameter DSN_CAP_ENABLE = "FALSE";
+    parameter EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
+    parameter HEADER_TYPE_OVERRIDE = "FALSE";
+    parameter IS_SWITCH_PORT = "FALSE";
+    parameter LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
+    parameter [8:0] LL_ACK_TIMEOUT = 9'h000;
+    parameter LL_ACK_TIMEOUT_EN = "FALSE";
+    parameter integer LL_ACK_TIMEOUT_FUNC = 0;
+    parameter LL_DISABLE_SCHED_TX_NAK = "FALSE";
+    parameter LL_REPLAY_FROM_RAM_PIPELINE = "FALSE";
+    parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000;
+    parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
+    parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
+    parameter LL_REPLAY_TO_RAM_PIPELINE = "FALSE";
+    parameter LL_RX_TLP_PARITY_GEN = "TRUE";
+    parameter LL_TX_TLP_PARITY_CHK = "TRUE";
+    parameter [15:0] LL_USER_SPARE = 16'h0000;
+    parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h250;
+    parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE";
+    parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE";
+    parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000;
+    parameter MCAP_CONFIGURE_OVERRIDE = "FALSE";
+    parameter MCAP_ENABLE = "FALSE";
+    parameter MCAP_EOS_DESIGN_SWITCH = "FALSE";
+    parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000;
+    parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE";
+    parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE";
+    parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE";
+    parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE";
+    parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE";
+    parameter [15:0] MCAP_VSEC_ID = 16'h0000;
+    parameter [11:0] MCAP_VSEC_LEN = 12'h02C;
+    parameter [3:0] MCAP_VSEC_REV = 4'h0;
+    parameter PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE = "FALSE";
+    parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000;
+    parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000;
+    parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00;
+    parameter [3:0] PF0_ARI_CAP_VER = 4'h1;
+    parameter [4:0] PF0_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
+    parameter [11:0] PF0_ATS_CAP_NEXTPTR = 12'h000;
+    parameter PF0_ATS_CAP_ON = "FALSE";
+    parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF0_BAR0_CONTROL = 3'h4;
+    parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00;
+    parameter [2:0] PF0_BAR1_CONTROL = 3'h0;
+    parameter [5:0] PF0_BAR2_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF0_BAR2_CONTROL = 3'h4;
+    parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF0_BAR3_CONTROL = 3'h0;
+    parameter [5:0] PF0_BAR4_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF0_BAR4_CONTROL = 3'h4;
+    parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF0_BAR5_CONTROL = 3'h0;
+    parameter [7:0] PF0_CAPABILITY_POINTER = 8'h80;
+    parameter [23:0] PF0_CLASS_CODE = 24'h000000;
+    parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE";
+    parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
+    parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
+    parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE";
+    parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE";
+    parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE";
+    parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0;
+    parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE";
+    parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
+    parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0;
+    parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
+    parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE";
+    parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
+    parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C;
+    parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
+    parameter PF0_EXPANSION_ROM_ENABLE = "FALSE";
+    parameter [2:0] PF0_INTERRUPT_PIN = 3'h1;
+    parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0;
+    parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
+    parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
+    parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7;
+    parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 = 7;
+    parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
+    parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
+    parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7;
+    parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 = 7;
+    parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
+    parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
+    parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7;
+    parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 = 7;
+    parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
+    parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
+    parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7;
+    parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 = 7;
+    parameter [0:0] PF0_LINK_CONTROL_RCB = 1'h0;
+    parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
+    parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000;
+    parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000;
+    parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000;
+    parameter [3:0] PF0_LTR_CAP_VER = 4'h1;
+    parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00;
+    parameter integer PF0_MSIX_CAP_PBA_BIR = 0;
+    parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+    parameter integer PF0_MSIX_CAP_TABLE_BIR = 0;
+    parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+    parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000;
+    parameter [5:0] PF0_MSIX_VECTOR_COUNT = 6'h04;
+    parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0;
+    parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00;
+    parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE";
+    parameter [7:0] PF0_PCIE_CAP_NEXTPTR = 8'h00;
+    parameter [7:0] PF0_PM_CAP_ID = 8'h01;
+    parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00;
+    parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE";
+    parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE";
+    parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE";
+    parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE";
+    parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3;
+    parameter PF0_PM_CSR_NOSOFTRESET = "TRUE";
+    parameter [11:0] PF0_PRI_CAP_NEXTPTR = 12'h000;
+    parameter PF0_PRI_CAP_ON = "FALSE";
+    parameter [31:0] PF0_PRI_OST_PR_CAPACITY = 32'h00000000;
+    parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000;
+    parameter PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
+    parameter [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4;
+    parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
+    parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0;
+    parameter [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4;
+    parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0;
+    parameter [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4;
+    parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0;
+    parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000;
+    parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000;
+    parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000;
+    parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1;
+    parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000;
+    parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000;
+    parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
+    parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000;
+    parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+    parameter PF0_TPHR_CAP_ENABLE = "FALSE";
+    parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
+    parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000;
+    parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
+    parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+    parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+    parameter [3:0] PF0_TPHR_CAP_VER = 4'h1;
+    parameter [3:0] PF0_VC_ARB_CAPABILITY = 4'h0;
+    parameter [7:0] PF0_VC_ARB_TBL_OFFSET = 8'h00;
+    parameter PF0_VC_CAP_ENABLE = "FALSE";
+    parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000;
+    parameter [3:0] PF0_VC_CAP_VER = 4'h1;
+    parameter PF0_VC_EXTENDED_COUNT = "FALSE";
+    parameter PF0_VC_LOW_PRIORITY_EXTENDED_COUNT = "FALSE";
+    parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000;
+    parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000;
+    parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00;
+    parameter [4:0] PF1_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
+    parameter [11:0] PF1_ATS_CAP_NEXTPTR = 12'h000;
+    parameter PF1_ATS_CAP_ON = "FALSE";
+    parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF1_BAR0_CONTROL = 3'h4;
+    parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00;
+    parameter [2:0] PF1_BAR1_CONTROL = 3'h0;
+    parameter [5:0] PF1_BAR2_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF1_BAR2_CONTROL = 3'h4;
+    parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF1_BAR3_CONTROL = 3'h0;
+    parameter [5:0] PF1_BAR4_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF1_BAR4_CONTROL = 3'h4;
+    parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF1_BAR5_CONTROL = 3'h0;
+    parameter [7:0] PF1_CAPABILITY_POINTER = 8'h80;
+    parameter [23:0] PF1_CLASS_CODE = 24'h000000;
+    parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
+    parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C;
+    parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
+    parameter PF1_EXPANSION_ROM_ENABLE = "FALSE";
+    parameter [2:0] PF1_INTERRUPT_PIN = 3'h1;
+    parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00;
+    parameter integer PF1_MSIX_CAP_PBA_BIR = 0;
+    parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+    parameter integer PF1_MSIX_CAP_TABLE_BIR = 0;
+    parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+    parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000;
+    parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0;
+    parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00;
+    parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE";
+    parameter [7:0] PF1_PCIE_CAP_NEXTPTR = 8'h00;
+    parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00;
+    parameter [11:0] PF1_PRI_CAP_NEXTPTR = 12'h000;
+    parameter PF1_PRI_CAP_ON = "FALSE";
+    parameter [31:0] PF1_PRI_OST_PR_CAPACITY = 32'h00000000;
+    parameter PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
+    parameter [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4;
+    parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
+    parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0;
+    parameter [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4;
+    parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0;
+    parameter [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4;
+    parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0;
+    parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000;
+    parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000;
+    parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000;
+    parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1;
+    parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000;
+    parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000;
+    parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
+    parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000;
+    parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000;
+    parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
+    parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000;
+    parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000;
+    parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00;
+    parameter [4:0] PF2_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
+    parameter [11:0] PF2_ATS_CAP_NEXTPTR = 12'h000;
+    parameter PF2_ATS_CAP_ON = "FALSE";
+    parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF2_BAR0_CONTROL = 3'h4;
+    parameter [4:0] PF2_BAR1_APERTURE_SIZE = 5'h00;
+    parameter [2:0] PF2_BAR1_CONTROL = 3'h0;
+    parameter [5:0] PF2_BAR2_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF2_BAR2_CONTROL = 3'h4;
+    parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF2_BAR3_CONTROL = 3'h0;
+    parameter [5:0] PF2_BAR4_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF2_BAR4_CONTROL = 3'h4;
+    parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF2_BAR5_CONTROL = 3'h0;
+    parameter [7:0] PF2_CAPABILITY_POINTER = 8'h80;
+    parameter [23:0] PF2_CLASS_CODE = 24'h000000;
+    parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
+    parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C;
+    parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
+    parameter PF2_EXPANSION_ROM_ENABLE = "FALSE";
+    parameter [2:0] PF2_INTERRUPT_PIN = 3'h1;
+    parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00;
+    parameter integer PF2_MSIX_CAP_PBA_BIR = 0;
+    parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+    parameter integer PF2_MSIX_CAP_TABLE_BIR = 0;
+    parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+    parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000;
+    parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0;
+    parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00;
+    parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE";
+    parameter [7:0] PF2_PCIE_CAP_NEXTPTR = 8'h00;
+    parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00;
+    parameter [11:0] PF2_PRI_CAP_NEXTPTR = 12'h000;
+    parameter PF2_PRI_CAP_ON = "FALSE";
+    parameter [31:0] PF2_PRI_OST_PR_CAPACITY = 32'h00000000;
+    parameter PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
+    parameter [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4;
+    parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
+    parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0;
+    parameter [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4;
+    parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0;
+    parameter [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4;
+    parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0;
+    parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000;
+    parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000;
+    parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000;
+    parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1;
+    parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000;
+    parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000;
+    parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
+    parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000;
+    parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000;
+    parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0;
+    parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000;
+    parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000;
+    parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00;
+    parameter [4:0] PF3_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
+    parameter [11:0] PF3_ATS_CAP_NEXTPTR = 12'h000;
+    parameter PF3_ATS_CAP_ON = "FALSE";
+    parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF3_BAR0_CONTROL = 3'h4;
+    parameter [4:0] PF3_BAR1_APERTURE_SIZE = 5'h00;
+    parameter [2:0] PF3_BAR1_CONTROL = 3'h0;
+    parameter [5:0] PF3_BAR2_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF3_BAR2_CONTROL = 3'h4;
+    parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF3_BAR3_CONTROL = 3'h0;
+    parameter [5:0] PF3_BAR4_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF3_BAR4_CONTROL = 3'h4;
+    parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF3_BAR5_CONTROL = 3'h0;
+    parameter [7:0] PF3_CAPABILITY_POINTER = 8'h80;
+    parameter [23:0] PF3_CLASS_CODE = 24'h000000;
+    parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
+    parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C;
+    parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
+    parameter PF3_EXPANSION_ROM_ENABLE = "FALSE";
+    parameter [2:0] PF3_INTERRUPT_PIN = 3'h1;
+    parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00;
+    parameter integer PF3_MSIX_CAP_PBA_BIR = 0;
+    parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+    parameter integer PF3_MSIX_CAP_TABLE_BIR = 0;
+    parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+    parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000;
+    parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0;
+    parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00;
+    parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE";
+    parameter [7:0] PF3_PCIE_CAP_NEXTPTR = 8'h00;
+    parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00;
+    parameter [11:0] PF3_PRI_CAP_NEXTPTR = 12'h000;
+    parameter PF3_PRI_CAP_ON = "FALSE";
+    parameter [31:0] PF3_PRI_OST_PR_CAPACITY = 32'h00000000;
+    parameter PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
+    parameter [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4;
+    parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
+    parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0;
+    parameter [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4;
+    parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0;
+    parameter [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
+    parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4;
+    parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
+    parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0;
+    parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000;
+    parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000;
+    parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000;
+    parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1;
+    parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000;
+    parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000;
+    parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
+    parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000;
+    parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000;
+    parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0;
+    parameter PL_CFG_STATE_ROBUSTNESS_ENABLE = "TRUE";
+    parameter PL_CTRL_SKP_GEN_ENABLE = "FALSE";
+    parameter PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE = "TRUE";
+    parameter PL_DEEMPH_SOURCE_SELECT = "TRUE";
+    parameter PL_DESKEW_ON_SKIP_IN_GEN12 = "FALSE";
+    parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE";
+    parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 = "FALSE";
+    parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE";
+    parameter PL_DISABLE_DC_BALANCE = "FALSE";
+    parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE";
+    parameter PL_DISABLE_LANE_REVERSAL = "FALSE";
+    parameter [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP = 2'h0;
+    parameter PL_DISABLE_RETRAIN_ON_EB_ERROR = "FALSE";
+    parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE";
+    parameter [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR = 16'h0000;
+    parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE";
+    parameter [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK = 2'h0;
+    parameter [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK = 2'h0;
+    parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02;
+    parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1;
+    parameter [1:0] PL_EQ_BYPASS_PHASE23 = 2'h0;
+    parameter [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT = 6'h33;
+    parameter [7:0] PL_EQ_DEFAULT_TX_PRESET = 8'h44;
+    parameter PL_EQ_DISABLE_MISMATCH_CHECK = "TRUE";
+    parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0 = 2'h0;
+    parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1 = 2'h0;
+    parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE";
+    parameter PL_EQ_TX_8G_EQ_TS2_ENABLE = "FALSE";
+    parameter PL_EXIT_LOOPBACK_ON_EI_ENTRY = "TRUE";
+    parameter PL_INFER_EI_DISABLE_LPBK_ACTIVE = "TRUE";
+    parameter PL_INFER_EI_DISABLE_REC_RC = "FALSE";
+    parameter PL_INFER_EI_DISABLE_REC_SPD = "FALSE";
+    parameter [31:0] PL_LANE0_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE10_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE11_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE12_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE13_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE14_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE15_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE1_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE2_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE3_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE4_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE5_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE6_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE7_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE8_EQ_CONTROL = 32'h00003F00;
+    parameter [31:0] PL_LANE9_EQ_CONTROL = 32'h00003F00;
+    parameter [3:0] PL_LINK_CAP_MAX_LINK_SPEED = 4'h4;
+    parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h08;
+    parameter integer PL_N_FTS = 255;
+    parameter PL_QUIESCE_GUARANTEE_DISABLE = "FALSE";
+    parameter PL_REDO_EQ_SOURCE_SELECT = "TRUE";
+    parameter [7:0] PL_REPORT_ALL_PHY_ERRORS = 8'h00;
+    parameter [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS = 2'h0;
+    parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3 = 4'h0;
+    parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4 = 4'h0;
+    parameter [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS = 2'h0;
+    parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3 = 4'h0;
+    parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4 = 4'h0;
+    parameter [1:0] PL_RX_L0S_EXIT_TO_RECOVERY = 2'h0;
+    parameter [1:0] PL_SIM_FAST_LINK_TRAINING = 2'h0;
+    parameter PL_SRIS_ENABLE = "FALSE";
+    parameter [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC = 7'h00;
+    parameter [6:0] PL_SRIS_SKPOS_REC_SPD_VEC = 7'h00;
+    parameter PL_UPSTREAM_FACING = "TRUE";
+    parameter [15:0] PL_USER_SPARE = 16'h0000;
+    parameter [15:0] PL_USER_SPARE2 = 16'h0000;
+    parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h1500;
+    parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h003E8;
+    parameter PM_ENABLE_L23_ENTRY = "FALSE";
+    parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE";
+    parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000100;
+    parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h00000;
+    parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0100;
+    parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+    parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000;
+    parameter SIM_VERSION = "1.0";
+    parameter SPARE_BIT0 = "FALSE";
+    parameter integer SPARE_BIT1 = 0;
+    parameter integer SPARE_BIT2 = 0;
+    parameter SPARE_BIT3 = "FALSE";
+    parameter integer SPARE_BIT4 = 0;
+    parameter integer SPARE_BIT5 = 0;
+    parameter integer SPARE_BIT6 = 0;
+    parameter integer SPARE_BIT7 = 0;
+    parameter integer SPARE_BIT8 = 0;
+    parameter [7:0] SPARE_BYTE0 = 8'h00;
+    parameter [7:0] SPARE_BYTE1 = 8'h00;
+    parameter [7:0] SPARE_BYTE2 = 8'h00;
+    parameter [7:0] SPARE_BYTE3 = 8'h00;
+    parameter [31:0] SPARE_WORD0 = 32'h00000000;
+    parameter [31:0] SPARE_WORD1 = 32'h00000000;
+    parameter [31:0] SPARE_WORD2 = 32'h00000000;
+    parameter [31:0] SPARE_WORD3 = 32'h00000000;
+    parameter [3:0] SRIOV_CAP_ENABLE = 4'h0;
+    parameter TL2CFG_IF_PARITY_CHK = "TRUE";
+    parameter [1:0] TL_COMPLETION_RAM_NUM_TLPS = 2'h0;
+    parameter [1:0] TL_COMPLETION_RAM_SIZE = 2'h1;
+    parameter [11:0] TL_CREDITS_CD = 12'h000;
+    parameter [11:0] TL_CREDITS_CD_VC1 = 12'h000;
+    parameter [7:0] TL_CREDITS_CH = 8'h00;
+    parameter [7:0] TL_CREDITS_CH_VC1 = 8'h00;
+    parameter [11:0] TL_CREDITS_NPD = 12'h004;
+    parameter [11:0] TL_CREDITS_NPD_VC1 = 12'h000;
+    parameter [7:0] TL_CREDITS_NPH = 8'h20;
+    parameter [7:0] TL_CREDITS_NPH_VC1 = 8'h01;
+    parameter [11:0] TL_CREDITS_PD = 12'h0E0;
+    parameter [11:0] TL_CREDITS_PD_VC1 = 12'h3E0;
+    parameter [7:0] TL_CREDITS_PH = 8'h20;
+    parameter [7:0] TL_CREDITS_PH_VC1 = 8'h20;
+    parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME = 5'h02;
+    parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME_VC1 = 5'h02;
+    parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT = 5'h08;
+    parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_VC1 = 5'h08;
+    parameter TL_FEATURE_ENABLE_FC_SCALING = "FALSE";
+    parameter [1:0] TL_PF_ENABLE_REG = 2'h0;
+    parameter [0:0] TL_POSTED_RAM_SIZE = 1'h0;
+    parameter TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE = "FALSE";
+    parameter TL_RX_COMPLETION_TO_RAM_READ_PIPELINE = "FALSE";
+    parameter TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE = "FALSE";
+    parameter TL_RX_POSTED_FROM_RAM_READ_PIPELINE = "FALSE";
+    parameter TL_RX_POSTED_TO_RAM_READ_PIPELINE = "FALSE";
+    parameter TL_RX_POSTED_TO_RAM_WRITE_PIPELINE = "FALSE";
+    parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE";
+    parameter TL_TX_TLP_STRADDLE_ENABLE = "FALSE";
+    parameter TL_TX_TLP_TERMINATE_PARITY = "FALSE";
+    parameter [15:0] TL_USER_SPARE = 16'h0000;
+    parameter TPH_FROM_RAM_PIPELINE = "FALSE";
+    parameter TPH_TO_RAM_PIPELINE = "FALSE";
+    parameter [7:0] VF0_CAPABILITY_POINTER = 8'h80;
+    parameter [11:0] VFG0_ARI_CAP_NEXTPTR = 12'h000;
+    parameter [4:0] VFG0_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
+    parameter [11:0] VFG0_ATS_CAP_NEXTPTR = 12'h000;
+    parameter VFG0_ATS_CAP_ON = "FALSE";
+    parameter [7:0] VFG0_MSIX_CAP_NEXTPTR = 8'h00;
+    parameter integer VFG0_MSIX_CAP_PBA_BIR = 0;
+    parameter [28:0] VFG0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+    parameter integer VFG0_MSIX_CAP_TABLE_BIR = 0;
+    parameter [28:0] VFG0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+    parameter [10:0] VFG0_MSIX_CAP_TABLE_SIZE = 11'h000;
+    parameter [7:0] VFG0_PCIE_CAP_NEXTPTR = 8'h00;
+    parameter [11:0] VFG0_TPHR_CAP_NEXTPTR = 12'h000;
+    parameter [2:0] VFG0_TPHR_CAP_ST_MODE_SEL = 3'h0;
+    parameter [11:0] VFG1_ARI_CAP_NEXTPTR = 12'h000;
+    parameter [4:0] VFG1_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
+    parameter [11:0] VFG1_ATS_CAP_NEXTPTR = 12'h000;
+    parameter VFG1_ATS_CAP_ON = "FALSE";
+    parameter [7:0] VFG1_MSIX_CAP_NEXTPTR = 8'h00;
+    parameter integer VFG1_MSIX_CAP_PBA_BIR = 0;
+    parameter [28:0] VFG1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+    parameter integer VFG1_MSIX_CAP_TABLE_BIR = 0;
+    parameter [28:0] VFG1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+    parameter [10:0] VFG1_MSIX_CAP_TABLE_SIZE = 11'h000;
+    parameter [7:0] VFG1_PCIE_CAP_NEXTPTR = 8'h00;
+    parameter [11:0] VFG1_TPHR_CAP_NEXTPTR = 12'h000;
+    parameter [2:0] VFG1_TPHR_CAP_ST_MODE_SEL = 3'h0;
+    parameter [11:0] VFG2_ARI_CAP_NEXTPTR = 12'h000;
+    parameter [4:0] VFG2_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
+    parameter [11:0] VFG2_ATS_CAP_NEXTPTR = 12'h000;
+    parameter VFG2_ATS_CAP_ON = "FALSE";
+    parameter [7:0] VFG2_MSIX_CAP_NEXTPTR = 8'h00;
+    parameter integer VFG2_MSIX_CAP_PBA_BIR = 0;
+    parameter [28:0] VFG2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+    parameter integer VFG2_MSIX_CAP_TABLE_BIR = 0;
+    parameter [28:0] VFG2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+    parameter [10:0] VFG2_MSIX_CAP_TABLE_SIZE = 11'h000;
+    parameter [7:0] VFG2_PCIE_CAP_NEXTPTR = 8'h00;
+    parameter [11:0] VFG2_TPHR_CAP_NEXTPTR = 12'h000;
+    parameter [2:0] VFG2_TPHR_CAP_ST_MODE_SEL = 3'h0;
+    parameter [11:0] VFG3_ARI_CAP_NEXTPTR = 12'h000;
+    parameter [4:0] VFG3_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
+    parameter [11:0] VFG3_ATS_CAP_NEXTPTR = 12'h000;
+    parameter VFG3_ATS_CAP_ON = "FALSE";
+    parameter [7:0] VFG3_MSIX_CAP_NEXTPTR = 8'h00;
+    parameter integer VFG3_MSIX_CAP_PBA_BIR = 0;
+    parameter [28:0] VFG3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+    parameter integer VFG3_MSIX_CAP_TABLE_BIR = 0;
+    parameter [28:0] VFG3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+    parameter [10:0] VFG3_MSIX_CAP_TABLE_SIZE = 11'h000;
+    parameter [7:0] VFG3_PCIE_CAP_NEXTPTR = 8'h00;
+    parameter [11:0] VFG3_TPHR_CAP_NEXTPTR = 12'h000;
+    parameter [2:0] VFG3_TPHR_CAP_ST_MODE_SEL = 3'h0;
+    output [7:0] AXIUSEROUT;
+    output CCIXTXCREDIT;
+    output [7:0] CFGBUSNUMBER;
+    output [1:0] CFGCURRENTSPEED;
+    output CFGERRCOROUT;
+    output CFGERRFATALOUT;
+    output CFGERRNONFATALOUT;
+    output [7:0] CFGEXTFUNCTIONNUMBER;
+    output CFGEXTREADRECEIVED;
+    output [9:0] CFGEXTREGISTERNUMBER;
+    output [3:0] CFGEXTWRITEBYTEENABLE;
+    output [31:0] CFGEXTWRITEDATA;
+    output CFGEXTWRITERECEIVED;
+    output [11:0] CFGFCCPLD;
+    output [7:0] CFGFCCPLH;
+    output [11:0] CFGFCNPD;
+    output [7:0] CFGFCNPH;
+    output [11:0] CFGFCPD;
+    output [7:0] CFGFCPH;
+    output [3:0] CFGFLRINPROCESS;
+    output [11:0] CFGFUNCTIONPOWERSTATE;
+    output [15:0] CFGFUNCTIONSTATUS;
+    output CFGHOTRESETOUT;
+    output [31:0] CFGINTERRUPTMSIDATA;
+    output [3:0] CFGINTERRUPTMSIENABLE;
+    output CFGINTERRUPTMSIFAIL;
+    output CFGINTERRUPTMSIMASKUPDATE;
+    output [11:0] CFGINTERRUPTMSIMMENABLE;
+    output CFGINTERRUPTMSISENT;
+    output [3:0] CFGINTERRUPTMSIXENABLE;
+    output [3:0] CFGINTERRUPTMSIXMASK;
+    output CFGINTERRUPTMSIXVECPENDINGSTATUS;
+    output CFGINTERRUPTSENT;
+    output [1:0] CFGLINKPOWERSTATE;
+    output [4:0] CFGLOCALERROROUT;
+    output CFGLOCALERRORVALID;
+    output CFGLTRENABLE;
+    output [5:0] CFGLTSSMSTATE;
+    output [1:0] CFGMAXPAYLOAD;
+    output [2:0] CFGMAXREADREQ;
+    output [31:0] CFGMGMTREADDATA;
+    output CFGMGMTREADWRITEDONE;
+    output CFGMSGRECEIVED;
+    output [7:0] CFGMSGRECEIVEDDATA;
+    output [4:0] CFGMSGRECEIVEDTYPE;
+    output CFGMSGTRANSMITDONE;
+    output [12:0] CFGMSIXRAMADDRESS;
+    output CFGMSIXRAMREADENABLE;
+    output [3:0] CFGMSIXRAMWRITEBYTEENABLE;
+    output [35:0] CFGMSIXRAMWRITEDATA;
+    output [2:0] CFGNEGOTIATEDWIDTH;
+    output [1:0] CFGOBFFENABLE;
+    output CFGPHYLINKDOWN;
+    output [1:0] CFGPHYLINKSTATUS;
+    output CFGPLSTATUSCHANGE;
+    output CFGPOWERSTATECHANGEINTERRUPT;
+    output [3:0] CFGRCBSTATUS;
+    output [1:0] CFGRXPMSTATE;
+    output [11:0] CFGTPHRAMADDRESS;
+    output CFGTPHRAMREADENABLE;
+    output [3:0] CFGTPHRAMWRITEBYTEENABLE;
+    output [35:0] CFGTPHRAMWRITEDATA;
+    output [3:0] CFGTPHREQUESTERENABLE;
+    output [11:0] CFGTPHSTMODE;
+    output [1:0] CFGTXPMSTATE;
+    output CFGVC1ENABLE;
+    output CFGVC1NEGOTIATIONPENDING;
+    output CONFMCAPDESIGNSWITCH;
+    output CONFMCAPEOS;
+    output CONFMCAPINUSEBYPCIE;
+    output CONFREQREADY;
+    output [31:0] CONFRESPRDATA;
+    output CONFRESPVALID;
+    output [129:0] DBGCCIXOUT;
+    output [31:0] DBGCTRL0OUT;
+    output [31:0] DBGCTRL1OUT;
+    output [255:0] DBGDATA0OUT;
+    output [255:0] DBGDATA1OUT;
+    output [15:0] DRPDO;
+    output DRPRDY;
+    output [45:0] MAXISCCIXRXTUSER;
+    output MAXISCCIXRXTVALID;
+    output [255:0] MAXISCQTDATA;
+    output [7:0] MAXISCQTKEEP;
+    output MAXISCQTLAST;
+    output [87:0] MAXISCQTUSER;
+    output MAXISCQTVALID;
+    output [255:0] MAXISRCTDATA;
+    output [7:0] MAXISRCTKEEP;
+    output MAXISRCTLAST;
+    output [74:0] MAXISRCTUSER;
+    output MAXISRCTVALID;
+    output [8:0] MIREPLAYRAMADDRESS0;
+    output [8:0] MIREPLAYRAMADDRESS1;
+    output MIREPLAYRAMREADENABLE0;
+    output MIREPLAYRAMREADENABLE1;
+    output [127:0] MIREPLAYRAMWRITEDATA0;
+    output [127:0] MIREPLAYRAMWRITEDATA1;
+    output MIREPLAYRAMWRITEENABLE0;
+    output MIREPLAYRAMWRITEENABLE1;
+    output [8:0] MIRXCOMPLETIONRAMREADADDRESS0;
+    output [8:0] MIRXCOMPLETIONRAMREADADDRESS1;
+    output [1:0] MIRXCOMPLETIONRAMREADENABLE0;
+    output [1:0] MIRXCOMPLETIONRAMREADENABLE1;
+    output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0;
+    output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1;
+    output [143:0] MIRXCOMPLETIONRAMWRITEDATA0;
+    output [143:0] MIRXCOMPLETIONRAMWRITEDATA1;
+    output [1:0] MIRXCOMPLETIONRAMWRITEENABLE0;
+    output [1:0] MIRXCOMPLETIONRAMWRITEENABLE1;
+    output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0;
+    output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1;
+    output MIRXPOSTEDREQUESTRAMREADENABLE0;
+    output MIRXPOSTEDREQUESTRAMREADENABLE1;
+    output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0;
+    output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1;
+    output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0;
+    output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1;
+    output MIRXPOSTEDREQUESTRAMWRITEENABLE0;
+    output MIRXPOSTEDREQUESTRAMWRITEENABLE1;
+    output [5:0] PCIECQNPREQCOUNT;
+    output PCIEPERST0B;
+    output PCIEPERST1B;
+    output [5:0] PCIERQSEQNUM0;
+    output [5:0] PCIERQSEQNUM1;
+    output PCIERQSEQNUMVLD0;
+    output PCIERQSEQNUMVLD1;
+    output [7:0] PCIERQTAG0;
+    output [7:0] PCIERQTAG1;
+    output [3:0] PCIERQTAGAV;
+    output PCIERQTAGVLD0;
+    output PCIERQTAGVLD1;
+    output [3:0] PCIETFCNPDAV;
+    output [3:0] PCIETFCNPHAV;
+    output [1:0] PIPERX00EQCONTROL;
+    output PIPERX00POLARITY;
+    output [1:0] PIPERX01EQCONTROL;
+    output PIPERX01POLARITY;
+    output [1:0] PIPERX02EQCONTROL;
+    output PIPERX02POLARITY;
+    output [1:0] PIPERX03EQCONTROL;
+    output PIPERX03POLARITY;
+    output [1:0] PIPERX04EQCONTROL;
+    output PIPERX04POLARITY;
+    output [1:0] PIPERX05EQCONTROL;
+    output PIPERX05POLARITY;
+    output [1:0] PIPERX06EQCONTROL;
+    output PIPERX06POLARITY;
+    output [1:0] PIPERX07EQCONTROL;
+    output PIPERX07POLARITY;
+    output [1:0] PIPERX08EQCONTROL;
+    output PIPERX08POLARITY;
+    output [1:0] PIPERX09EQCONTROL;
+    output PIPERX09POLARITY;
+    output [1:0] PIPERX10EQCONTROL;
+    output PIPERX10POLARITY;
+    output [1:0] PIPERX11EQCONTROL;
+    output PIPERX11POLARITY;
+    output [1:0] PIPERX12EQCONTROL;
+    output PIPERX12POLARITY;
+    output [1:0] PIPERX13EQCONTROL;
+    output PIPERX13POLARITY;
+    output [1:0] PIPERX14EQCONTROL;
+    output PIPERX14POLARITY;
+    output [1:0] PIPERX15EQCONTROL;
+    output PIPERX15POLARITY;
+    output [5:0] PIPERXEQLPLFFS;
+    output [3:0] PIPERXEQLPTXPRESET;
+    output [1:0] PIPETX00CHARISK;
+    output PIPETX00COMPLIANCE;
+    output [31:0] PIPETX00DATA;
+    output PIPETX00DATAVALID;
+    output PIPETX00ELECIDLE;
+    output [1:0] PIPETX00EQCONTROL;
+    output [5:0] PIPETX00EQDEEMPH;
+    output [1:0] PIPETX00POWERDOWN;
+    output PIPETX00STARTBLOCK;
+    output [1:0] PIPETX00SYNCHEADER;
+    output [1:0] PIPETX01CHARISK;
+    output PIPETX01COMPLIANCE;
+    output [31:0] PIPETX01DATA;
+    output PIPETX01DATAVALID;
+    output PIPETX01ELECIDLE;
+    output [1:0] PIPETX01EQCONTROL;
+    output [5:0] PIPETX01EQDEEMPH;
+    output [1:0] PIPETX01POWERDOWN;
+    output PIPETX01STARTBLOCK;
+    output [1:0] PIPETX01SYNCHEADER;
+    output [1:0] PIPETX02CHARISK;
+    output PIPETX02COMPLIANCE;
+    output [31:0] PIPETX02DATA;
+    output PIPETX02DATAVALID;
+    output PIPETX02ELECIDLE;
+    output [1:0] PIPETX02EQCONTROL;
+    output [5:0] PIPETX02EQDEEMPH;
+    output [1:0] PIPETX02POWERDOWN;
+    output PIPETX02STARTBLOCK;
+    output [1:0] PIPETX02SYNCHEADER;
+    output [1:0] PIPETX03CHARISK;
+    output PIPETX03COMPLIANCE;
+    output [31:0] PIPETX03DATA;
+    output PIPETX03DATAVALID;
+    output PIPETX03ELECIDLE;
+    output [1:0] PIPETX03EQCONTROL;
+    output [5:0] PIPETX03EQDEEMPH;
+    output [1:0] PIPETX03POWERDOWN;
+    output PIPETX03STARTBLOCK;
+    output [1:0] PIPETX03SYNCHEADER;
+    output [1:0] PIPETX04CHARISK;
+    output PIPETX04COMPLIANCE;
+    output [31:0] PIPETX04DATA;
+    output PIPETX04DATAVALID;
+    output PIPETX04ELECIDLE;
+    output [1:0] PIPETX04EQCONTROL;
+    output [5:0] PIPETX04EQDEEMPH;
+    output [1:0] PIPETX04POWERDOWN;
+    output PIPETX04STARTBLOCK;
+    output [1:0] PIPETX04SYNCHEADER;
+    output [1:0] PIPETX05CHARISK;
+    output PIPETX05COMPLIANCE;
+    output [31:0] PIPETX05DATA;
+    output PIPETX05DATAVALID;
+    output PIPETX05ELECIDLE;
+    output [1:0] PIPETX05EQCONTROL;
+    output [5:0] PIPETX05EQDEEMPH;
+    output [1:0] PIPETX05POWERDOWN;
+    output PIPETX05STARTBLOCK;
+    output [1:0] PIPETX05SYNCHEADER;
+    output [1:0] PIPETX06CHARISK;
+    output PIPETX06COMPLIANCE;
+    output [31:0] PIPETX06DATA;
+    output PIPETX06DATAVALID;
+    output PIPETX06ELECIDLE;
+    output [1:0] PIPETX06EQCONTROL;
+    output [5:0] PIPETX06EQDEEMPH;
+    output [1:0] PIPETX06POWERDOWN;
+    output PIPETX06STARTBLOCK;
+    output [1:0] PIPETX06SYNCHEADER;
+    output [1:0] PIPETX07CHARISK;
+    output PIPETX07COMPLIANCE;
+    output [31:0] PIPETX07DATA;
+    output PIPETX07DATAVALID;
+    output PIPETX07ELECIDLE;
+    output [1:0] PIPETX07EQCONTROL;
+    output [5:0] PIPETX07EQDEEMPH;
+    output [1:0] PIPETX07POWERDOWN;
+    output PIPETX07STARTBLOCK;
+    output [1:0] PIPETX07SYNCHEADER;
+    output [1:0] PIPETX08CHARISK;
+    output PIPETX08COMPLIANCE;
+    output [31:0] PIPETX08DATA;
+    output PIPETX08DATAVALID;
+    output PIPETX08ELECIDLE;
+    output [1:0] PIPETX08EQCONTROL;
+    output [5:0] PIPETX08EQDEEMPH;
+    output [1:0] PIPETX08POWERDOWN;
+    output PIPETX08STARTBLOCK;
+    output [1:0] PIPETX08SYNCHEADER;
+    output [1:0] PIPETX09CHARISK;
+    output PIPETX09COMPLIANCE;
+    output [31:0] PIPETX09DATA;
+    output PIPETX09DATAVALID;
+    output PIPETX09ELECIDLE;
+    output [1:0] PIPETX09EQCONTROL;
+    output [5:0] PIPETX09EQDEEMPH;
+    output [1:0] PIPETX09POWERDOWN;
+    output PIPETX09STARTBLOCK;
+    output [1:0] PIPETX09SYNCHEADER;
+    output [1:0] PIPETX10CHARISK;
+    output PIPETX10COMPLIANCE;
+    output [31:0] PIPETX10DATA;
+    output PIPETX10DATAVALID;
+    output PIPETX10ELECIDLE;
+    output [1:0] PIPETX10EQCONTROL;
+    output [5:0] PIPETX10EQDEEMPH;
+    output [1:0] PIPETX10POWERDOWN;
+    output PIPETX10STARTBLOCK;
+    output [1:0] PIPETX10SYNCHEADER;
+    output [1:0] PIPETX11CHARISK;
+    output PIPETX11COMPLIANCE;
+    output [31:0] PIPETX11DATA;
+    output PIPETX11DATAVALID;
+    output PIPETX11ELECIDLE;
+    output [1:0] PIPETX11EQCONTROL;
+    output [5:0] PIPETX11EQDEEMPH;
+    output [1:0] PIPETX11POWERDOWN;
+    output PIPETX11STARTBLOCK;
+    output [1:0] PIPETX11SYNCHEADER;
+    output [1:0] PIPETX12CHARISK;
+    output PIPETX12COMPLIANCE;
+    output [31:0] PIPETX12DATA;
+    output PIPETX12DATAVALID;
+    output PIPETX12ELECIDLE;
+    output [1:0] PIPETX12EQCONTROL;
+    output [5:0] PIPETX12EQDEEMPH;
+    output [1:0] PIPETX12POWERDOWN;
+    output PIPETX12STARTBLOCK;
+    output [1:0] PIPETX12SYNCHEADER;
+    output [1:0] PIPETX13CHARISK;
+    output PIPETX13COMPLIANCE;
+    output [31:0] PIPETX13DATA;
+    output PIPETX13DATAVALID;
+    output PIPETX13ELECIDLE;
+    output [1:0] PIPETX13EQCONTROL;
+    output [5:0] PIPETX13EQDEEMPH;
+    output [1:0] PIPETX13POWERDOWN;
+    output PIPETX13STARTBLOCK;
+    output [1:0] PIPETX13SYNCHEADER;
+    output [1:0] PIPETX14CHARISK;
+    output PIPETX14COMPLIANCE;
+    output [31:0] PIPETX14DATA;
+    output PIPETX14DATAVALID;
+    output PIPETX14ELECIDLE;
+    output [1:0] PIPETX14EQCONTROL;
+    output [5:0] PIPETX14EQDEEMPH;
+    output [1:0] PIPETX14POWERDOWN;
+    output PIPETX14STARTBLOCK;
+    output [1:0] PIPETX14SYNCHEADER;
+    output [1:0] PIPETX15CHARISK;
+    output PIPETX15COMPLIANCE;
+    output [31:0] PIPETX15DATA;
+    output PIPETX15DATAVALID;
+    output PIPETX15ELECIDLE;
+    output [1:0] PIPETX15EQCONTROL;
+    output [5:0] PIPETX15EQDEEMPH;
+    output [1:0] PIPETX15POWERDOWN;
+    output PIPETX15STARTBLOCK;
+    output [1:0] PIPETX15SYNCHEADER;
+    output PIPETXDEEMPH;
+    output [2:0] PIPETXMARGIN;
+    output [1:0] PIPETXRATE;
+    output PIPETXRCVRDET;
+    output PIPETXRESET;
+    output PIPETXSWING;
+    output PLEQINPROGRESS;
+    output [1:0] PLEQPHASE;
+    output PLGEN34EQMISMATCH;
+    output [3:0] SAXISCCTREADY;
+    output [3:0] SAXISRQTREADY;
+    output [23:0] USERSPAREOUT;
+    input [7:0] AXIUSERIN;
+    input CCIXOPTIMIZEDTLPTXANDRXENABLE;
+    input CCIXRXCORRECTABLEERRORDETECTED;
+    input CCIXRXFIFOOVERFLOW;
+    input CCIXRXTLPFORWARDED0;
+    input CCIXRXTLPFORWARDED1;
+    input [5:0] CCIXRXTLPFORWARDEDLENGTH0;
+    input [5:0] CCIXRXTLPFORWARDEDLENGTH1;
+    input CCIXRXUNCORRECTABLEERRORDETECTED;
+    input CFGCONFIGSPACEENABLE;
+    input [15:0] CFGDEVIDPF0;
+    input [15:0] CFGDEVIDPF1;
+    input [15:0] CFGDEVIDPF2;
+    input [15:0] CFGDEVIDPF3;
+    input [7:0] CFGDSBUSNUMBER;
+    input [4:0] CFGDSDEVICENUMBER;
+    input [2:0] CFGDSFUNCTIONNUMBER;
+    input [63:0] CFGDSN;
+    input [7:0] CFGDSPORTNUMBER;
+    input CFGERRCORIN;
+    input CFGERRUNCORIN;
+    input [31:0] CFGEXTREADDATA;
+    input CFGEXTREADDATAVALID;
+    input [2:0] CFGFCSEL;
+    input CFGFCVCSEL;
+    input [3:0] CFGFLRDONE;
+    input CFGHOTRESETIN;
+    input [3:0] CFGINTERRUPTINT;
+    input [2:0] CFGINTERRUPTMSIATTR;
+    input [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER;
+    input [31:0] CFGINTERRUPTMSIINT;
+    input [31:0] CFGINTERRUPTMSIPENDINGSTATUS;
+    input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE;
+    input [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM;
+    input [1:0] CFGINTERRUPTMSISELECT;
+    input CFGINTERRUPTMSITPHPRESENT;
+    input [7:0] CFGINTERRUPTMSITPHSTTAG;
+    input [1:0] CFGINTERRUPTMSITPHTYPE;
+    input [63:0] CFGINTERRUPTMSIXADDRESS;
+    input [31:0] CFGINTERRUPTMSIXDATA;
+    input CFGINTERRUPTMSIXINT;
+    input [1:0] CFGINTERRUPTMSIXVECPENDING;
+    input [3:0] CFGINTERRUPTPENDING;
+    input CFGLINKTRAININGENABLE;
+    input [9:0] CFGMGMTADDR;
+    input [3:0] CFGMGMTBYTEENABLE;
+    input CFGMGMTDEBUGACCESS;
+    input [7:0] CFGMGMTFUNCTIONNUMBER;
+    input CFGMGMTREAD;
+    input CFGMGMTWRITE;
+    input [31:0] CFGMGMTWRITEDATA;
+    input CFGMSGTRANSMIT;
+    input [31:0] CFGMSGTRANSMITDATA;
+    input [2:0] CFGMSGTRANSMITTYPE;
+    input [35:0] CFGMSIXRAMREADDATA;
+    input CFGPMASPML1ENTRYREJECT;
+    input CFGPMASPMTXL0SENTRYDISABLE;
+    input CFGPOWERSTATECHANGEACK;
+    input CFGREQPMTRANSITIONL23READY;
+    input [7:0] CFGREVIDPF0;
+    input [7:0] CFGREVIDPF1;
+    input [7:0] CFGREVIDPF2;
+    input [7:0] CFGREVIDPF3;
+    input [15:0] CFGSUBSYSIDPF0;
+    input [15:0] CFGSUBSYSIDPF1;
+    input [15:0] CFGSUBSYSIDPF2;
+    input [15:0] CFGSUBSYSIDPF3;
+    input [15:0] CFGSUBSYSVENDID;
+    input [35:0] CFGTPHRAMREADDATA;
+    input [15:0] CFGVENDID;
+    input CFGVFFLRDONE;
+    input [7:0] CFGVFFLRFUNCNUM;
+    input CONFMCAPREQUESTBYCONF;
+    input [31:0] CONFREQDATA;
+    input [3:0] CONFREQREGNUM;
+    input [1:0] CONFREQTYPE;
+    input CONFREQVALID;
+    input CORECLK;
+    input CORECLKCCIX;
+    input CORECLKMIREPLAYRAM0;
+    input CORECLKMIREPLAYRAM1;
+    input CORECLKMIRXCOMPLETIONRAM0;
+    input CORECLKMIRXCOMPLETIONRAM1;
+    input CORECLKMIRXPOSTEDREQUESTRAM0;
+    input CORECLKMIRXPOSTEDREQUESTRAM1;
+    input [5:0] DBGSEL0;
+    input [5:0] DBGSEL1;
+    input [9:0] DRPADDR;
+    input DRPCLK;
+    input [15:0] DRPDI;
+    input DRPEN;
+    input DRPWE;
+    input [21:0] MAXISCQTREADY;
+    input [21:0] MAXISRCTREADY;
+    input MCAPCLK;
+    input MCAPPERST0B;
+    input MCAPPERST1B;
+    input MGMTRESETN;
+    input MGMTSTICKYRESETN;
+    input [5:0] MIREPLAYRAMERRCOR;
+    input [5:0] MIREPLAYRAMERRUNCOR;
+    input [127:0] MIREPLAYRAMREADDATA0;
+    input [127:0] MIREPLAYRAMREADDATA1;
+    input [11:0] MIRXCOMPLETIONRAMERRCOR;
+    input [11:0] MIRXCOMPLETIONRAMERRUNCOR;
+    input [143:0] MIRXCOMPLETIONRAMREADDATA0;
+    input [143:0] MIRXCOMPLETIONRAMREADDATA1;
+    input [5:0] MIRXPOSTEDREQUESTRAMERRCOR;
+    input [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR;
+    input [143:0] MIRXPOSTEDREQUESTRAMREADDATA0;
+    input [143:0] MIRXPOSTEDREQUESTRAMREADDATA1;
+    input [1:0] PCIECOMPLDELIVERED;
+    input [7:0] PCIECOMPLDELIVEREDTAG0;
+    input [7:0] PCIECOMPLDELIVEREDTAG1;
+    input [1:0] PCIECQNPREQ;
+    input PCIECQNPUSERCREDITRCVD;
+    input PCIECQPIPELINEEMPTY;
+    input PCIEPOSTEDREQDELIVERED;
+    input PIPECLK;
+    input PIPECLKEN;
+    input [5:0] PIPEEQFS;
+    input [5:0] PIPEEQLF;
+    input PIPERESETN;
+    input [1:0] PIPERX00CHARISK;
+    input [31:0] PIPERX00DATA;
+    input PIPERX00DATAVALID;
+    input PIPERX00ELECIDLE;
+    input PIPERX00EQDONE;
+    input PIPERX00EQLPADAPTDONE;
+    input PIPERX00EQLPLFFSSEL;
+    input [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET;
+    input PIPERX00PHYSTATUS;
+    input [1:0] PIPERX00STARTBLOCK;
+    input [2:0] PIPERX00STATUS;
+    input [1:0] PIPERX00SYNCHEADER;
+    input PIPERX00VALID;
+    input [1:0] PIPERX01CHARISK;
+    input [31:0] PIPERX01DATA;
+    input PIPERX01DATAVALID;
+    input PIPERX01ELECIDLE;
+    input PIPERX01EQDONE;
+    input PIPERX01EQLPADAPTDONE;
+    input PIPERX01EQLPLFFSSEL;
+    input [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET;
+    input PIPERX01PHYSTATUS;
+    input [1:0] PIPERX01STARTBLOCK;
+    input [2:0] PIPERX01STATUS;
+    input [1:0] PIPERX01SYNCHEADER;
+    input PIPERX01VALID;
+    input [1:0] PIPERX02CHARISK;
+    input [31:0] PIPERX02DATA;
+    input PIPERX02DATAVALID;
+    input PIPERX02ELECIDLE;
+    input PIPERX02EQDONE;
+    input PIPERX02EQLPADAPTDONE;
+    input PIPERX02EQLPLFFSSEL;
+    input [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET;
+    input PIPERX02PHYSTATUS;
+    input [1:0] PIPERX02STARTBLOCK;
+    input [2:0] PIPERX02STATUS;
+    input [1:0] PIPERX02SYNCHEADER;
+    input PIPERX02VALID;
+    input [1:0] PIPERX03CHARISK;
+    input [31:0] PIPERX03DATA;
+    input PIPERX03DATAVALID;
+    input PIPERX03ELECIDLE;
+    input PIPERX03EQDONE;
+    input PIPERX03EQLPADAPTDONE;
+    input PIPERX03EQLPLFFSSEL;
+    input [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET;
+    input PIPERX03PHYSTATUS;
+    input [1:0] PIPERX03STARTBLOCK;
+    input [2:0] PIPERX03STATUS;
+    input [1:0] PIPERX03SYNCHEADER;
+    input PIPERX03VALID;
+    input [1:0] PIPERX04CHARISK;
+    input [31:0] PIPERX04DATA;
+    input PIPERX04DATAVALID;
+    input PIPERX04ELECIDLE;
+    input PIPERX04EQDONE;
+    input PIPERX04EQLPADAPTDONE;
+    input PIPERX04EQLPLFFSSEL;
+    input [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET;
+    input PIPERX04PHYSTATUS;
+    input [1:0] PIPERX04STARTBLOCK;
+    input [2:0] PIPERX04STATUS;
+    input [1:0] PIPERX04SYNCHEADER;
+    input PIPERX04VALID;
+    input [1:0] PIPERX05CHARISK;
+    input [31:0] PIPERX05DATA;
+    input PIPERX05DATAVALID;
+    input PIPERX05ELECIDLE;
+    input PIPERX05EQDONE;
+    input PIPERX05EQLPADAPTDONE;
+    input PIPERX05EQLPLFFSSEL;
+    input [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET;
+    input PIPERX05PHYSTATUS;
+    input [1:0] PIPERX05STARTBLOCK;
+    input [2:0] PIPERX05STATUS;
+    input [1:0] PIPERX05SYNCHEADER;
+    input PIPERX05VALID;
+    input [1:0] PIPERX06CHARISK;
+    input [31:0] PIPERX06DATA;
+    input PIPERX06DATAVALID;
+    input PIPERX06ELECIDLE;
+    input PIPERX06EQDONE;
+    input PIPERX06EQLPADAPTDONE;
+    input PIPERX06EQLPLFFSSEL;
+    input [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET;
+    input PIPERX06PHYSTATUS;
+    input [1:0] PIPERX06STARTBLOCK;
+    input [2:0] PIPERX06STATUS;
+    input [1:0] PIPERX06SYNCHEADER;
+    input PIPERX06VALID;
+    input [1:0] PIPERX07CHARISK;
+    input [31:0] PIPERX07DATA;
+    input PIPERX07DATAVALID;
+    input PIPERX07ELECIDLE;
+    input PIPERX07EQDONE;
+    input PIPERX07EQLPADAPTDONE;
+    input PIPERX07EQLPLFFSSEL;
+    input [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET;
+    input PIPERX07PHYSTATUS;
+    input [1:0] PIPERX07STARTBLOCK;
+    input [2:0] PIPERX07STATUS;
+    input [1:0] PIPERX07SYNCHEADER;
+    input PIPERX07VALID;
+    input [1:0] PIPERX08CHARISK;
+    input [31:0] PIPERX08DATA;
+    input PIPERX08DATAVALID;
+    input PIPERX08ELECIDLE;
+    input PIPERX08EQDONE;
+    input PIPERX08EQLPADAPTDONE;
+    input PIPERX08EQLPLFFSSEL;
+    input [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET;
+    input PIPERX08PHYSTATUS;
+    input [1:0] PIPERX08STARTBLOCK;
+    input [2:0] PIPERX08STATUS;
+    input [1:0] PIPERX08SYNCHEADER;
+    input PIPERX08VALID;
+    input [1:0] PIPERX09CHARISK;
+    input [31:0] PIPERX09DATA;
+    input PIPERX09DATAVALID;
+    input PIPERX09ELECIDLE;
+    input PIPERX09EQDONE;
+    input PIPERX09EQLPADAPTDONE;
+    input PIPERX09EQLPLFFSSEL;
+    input [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET;
+    input PIPERX09PHYSTATUS;
+    input [1:0] PIPERX09STARTBLOCK;
+    input [2:0] PIPERX09STATUS;
+    input [1:0] PIPERX09SYNCHEADER;
+    input PIPERX09VALID;
+    input [1:0] PIPERX10CHARISK;
+    input [31:0] PIPERX10DATA;
+    input PIPERX10DATAVALID;
+    input PIPERX10ELECIDLE;
+    input PIPERX10EQDONE;
+    input PIPERX10EQLPADAPTDONE;
+    input PIPERX10EQLPLFFSSEL;
+    input [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET;
+    input PIPERX10PHYSTATUS;
+    input [1:0] PIPERX10STARTBLOCK;
+    input [2:0] PIPERX10STATUS;
+    input [1:0] PIPERX10SYNCHEADER;
+    input PIPERX10VALID;
+    input [1:0] PIPERX11CHARISK;
+    input [31:0] PIPERX11DATA;
+    input PIPERX11DATAVALID;
+    input PIPERX11ELECIDLE;
+    input PIPERX11EQDONE;
+    input PIPERX11EQLPADAPTDONE;
+    input PIPERX11EQLPLFFSSEL;
+    input [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET;
+    input PIPERX11PHYSTATUS;
+    input [1:0] PIPERX11STARTBLOCK;
+    input [2:0] PIPERX11STATUS;
+    input [1:0] PIPERX11SYNCHEADER;
+    input PIPERX11VALID;
+    input [1:0] PIPERX12CHARISK;
+    input [31:0] PIPERX12DATA;
+    input PIPERX12DATAVALID;
+    input PIPERX12ELECIDLE;
+    input PIPERX12EQDONE;
+    input PIPERX12EQLPADAPTDONE;
+    input PIPERX12EQLPLFFSSEL;
+    input [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET;
+    input PIPERX12PHYSTATUS;
+    input [1:0] PIPERX12STARTBLOCK;
+    input [2:0] PIPERX12STATUS;
+    input [1:0] PIPERX12SYNCHEADER;
+    input PIPERX12VALID;
+    input [1:0] PIPERX13CHARISK;
+    input [31:0] PIPERX13DATA;
+    input PIPERX13DATAVALID;
+    input PIPERX13ELECIDLE;
+    input PIPERX13EQDONE;
+    input PIPERX13EQLPADAPTDONE;
+    input PIPERX13EQLPLFFSSEL;
+    input [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET;
+    input PIPERX13PHYSTATUS;
+    input [1:0] PIPERX13STARTBLOCK;
+    input [2:0] PIPERX13STATUS;
+    input [1:0] PIPERX13SYNCHEADER;
+    input PIPERX13VALID;
+    input [1:0] PIPERX14CHARISK;
+    input [31:0] PIPERX14DATA;
+    input PIPERX14DATAVALID;
+    input PIPERX14ELECIDLE;
+    input PIPERX14EQDONE;
+    input PIPERX14EQLPADAPTDONE;
+    input PIPERX14EQLPLFFSSEL;
+    input [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET;
+    input PIPERX14PHYSTATUS;
+    input [1:0] PIPERX14STARTBLOCK;
+    input [2:0] PIPERX14STATUS;
+    input [1:0] PIPERX14SYNCHEADER;
+    input PIPERX14VALID;
+    input [1:0] PIPERX15CHARISK;
+    input [31:0] PIPERX15DATA;
+    input PIPERX15DATAVALID;
+    input PIPERX15ELECIDLE;
+    input PIPERX15EQDONE;
+    input PIPERX15EQLPADAPTDONE;
+    input PIPERX15EQLPLFFSSEL;
+    input [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET;
+    input PIPERX15PHYSTATUS;
+    input [1:0] PIPERX15STARTBLOCK;
+    input [2:0] PIPERX15STATUS;
+    input [1:0] PIPERX15SYNCHEADER;
+    input PIPERX15VALID;
+    input [17:0] PIPETX00EQCOEFF;
+    input PIPETX00EQDONE;
+    input [17:0] PIPETX01EQCOEFF;
+    input PIPETX01EQDONE;
+    input [17:0] PIPETX02EQCOEFF;
+    input PIPETX02EQDONE;
+    input [17:0] PIPETX03EQCOEFF;
+    input PIPETX03EQDONE;
+    input [17:0] PIPETX04EQCOEFF;
+    input PIPETX04EQDONE;
+    input [17:0] PIPETX05EQCOEFF;
+    input PIPETX05EQDONE;
+    input [17:0] PIPETX06EQCOEFF;
+    input PIPETX06EQDONE;
+    input [17:0] PIPETX07EQCOEFF;
+    input PIPETX07EQDONE;
+    input [17:0] PIPETX08EQCOEFF;
+    input PIPETX08EQDONE;
+    input [17:0] PIPETX09EQCOEFF;
+    input PIPETX09EQDONE;
+    input [17:0] PIPETX10EQCOEFF;
+    input PIPETX10EQDONE;
+    input [17:0] PIPETX11EQCOEFF;
+    input PIPETX11EQDONE;
+    input [17:0] PIPETX12EQCOEFF;
+    input PIPETX12EQDONE;
+    input [17:0] PIPETX13EQCOEFF;
+    input PIPETX13EQDONE;
+    input [17:0] PIPETX14EQCOEFF;
+    input PIPETX14EQDONE;
+    input [17:0] PIPETX15EQCOEFF;
+    input PIPETX15EQDONE;
+    input PLEQRESETEIEOSCOUNT;
+    input PLGEN2UPSTREAMPREFERDEEMPH;
+    input PLGEN34REDOEQSPEED;
+    input PLGEN34REDOEQUALIZATION;
+    input RESETN;
+    input [255:0] SAXISCCIXTXTDATA;
+    input [45:0] SAXISCCIXTXTUSER;
+    input SAXISCCIXTXTVALID;
+    input [255:0] SAXISCCTDATA;
+    input [7:0] SAXISCCTKEEP;
+    input SAXISCCTLAST;
+    input [32:0] SAXISCCTUSER;
+    input SAXISCCTVALID;
+    input [255:0] SAXISRQTDATA;
+    input [7:0] SAXISRQTKEEP;
+    input SAXISRQTLAST;
+    input [61:0] SAXISRQTUSER;
+    input SAXISRQTVALID;
+    input USERCLK;
+    input USERCLK2;
+    input USERCLKEN;
+    input [31:0] USERSPAREIN;
+endmodule
+
+module EMAC (...);
+    parameter EMAC0_MODE = "RGMII";
+    parameter EMAC1_MODE = "RGMII";
+    output DCRHOSTDONEIR;
+    output EMAC0CLIENTANINTERRUPT;
+    output EMAC0CLIENTRXBADFRAME;
+    output EMAC0CLIENTRXCLIENTCLKOUT;
+    output EMAC0CLIENTRXDVLD;
+    output EMAC0CLIENTRXDVLDMSW;
+    output EMAC0CLIENTRXDVREG6;
+    output EMAC0CLIENTRXFRAMEDROP;
+    output EMAC0CLIENTRXGOODFRAME;
+    output EMAC0CLIENTRXSTATSBYTEVLD;
+    output EMAC0CLIENTRXSTATSVLD;
+    output EMAC0CLIENTTXACK;
+    output EMAC0CLIENTTXCLIENTCLKOUT;
+    output EMAC0CLIENTTXCOLLISION;
+    output EMAC0CLIENTTXGMIIMIICLKOUT;
+    output EMAC0CLIENTTXRETRANSMIT;
+    output EMAC0CLIENTTXSTATS;
+    output EMAC0CLIENTTXSTATSBYTEVLD;
+    output EMAC0CLIENTTXSTATSVLD;
+    output EMAC0PHYENCOMMAALIGN;
+    output EMAC0PHYLOOPBACKMSB;
+    output EMAC0PHYMCLKOUT;
+    output EMAC0PHYMDOUT;
+    output EMAC0PHYMDTRI;
+    output EMAC0PHYMGTRXRESET;
+    output EMAC0PHYMGTTXRESET;
+    output EMAC0PHYPOWERDOWN;
+    output EMAC0PHYSYNCACQSTATUS;
+    output EMAC0PHYTXCHARDISPMODE;
+    output EMAC0PHYTXCHARDISPVAL;
+    output EMAC0PHYTXCHARISK;
+    output EMAC0PHYTXCLK;
+    output EMAC0PHYTXEN;
+    output EMAC0PHYTXER;
+    output EMAC1CLIENTANINTERRUPT;
+    output EMAC1CLIENTRXBADFRAME;
+    output EMAC1CLIENTRXCLIENTCLKOUT;
+    output EMAC1CLIENTRXDVLD;
+    output EMAC1CLIENTRXDVLDMSW;
+    output EMAC1CLIENTRXDVREG6;
+    output EMAC1CLIENTRXFRAMEDROP;
+    output EMAC1CLIENTRXGOODFRAME;
+    output EMAC1CLIENTRXSTATSBYTEVLD;
+    output EMAC1CLIENTRXSTATSVLD;
+    output EMAC1CLIENTTXACK;
+    output EMAC1CLIENTTXCLIENTCLKOUT;
+    output EMAC1CLIENTTXCOLLISION;
+    output EMAC1CLIENTTXGMIIMIICLKOUT;
+    output EMAC1CLIENTTXRETRANSMIT;
+    output EMAC1CLIENTTXSTATS;
+    output EMAC1CLIENTTXSTATSBYTEVLD;
+    output EMAC1CLIENTTXSTATSVLD;
+    output EMAC1PHYENCOMMAALIGN;
+    output EMAC1PHYLOOPBACKMSB;
+    output EMAC1PHYMCLKOUT;
+    output EMAC1PHYMDOUT;
+    output EMAC1PHYMDTRI;
+    output EMAC1PHYMGTRXRESET;
+    output EMAC1PHYMGTTXRESET;
+    output EMAC1PHYPOWERDOWN;
+    output EMAC1PHYSYNCACQSTATUS;
+    output EMAC1PHYTXCHARDISPMODE;
+    output EMAC1PHYTXCHARDISPVAL;
+    output EMAC1PHYTXCHARISK;
+    output EMAC1PHYTXCLK;
+    output EMAC1PHYTXEN;
+    output EMAC1PHYTXER;
+    output EMACDCRACK;
+    output HOSTMIIMRDY;
+    output [0:31] EMACDCRDBUS;
+    output [15:0] EMAC0CLIENTRXD;
+    output [15:0] EMAC1CLIENTRXD;
+    output [31:0] HOSTRDDATA;
+    output [6:0] EMAC0CLIENTRXSTATS;
+    output [6:0] EMAC1CLIENTRXSTATS;
+    output [7:0] EMAC0PHYTXD;
+    output [7:0] EMAC1PHYTXD;
+    input CLIENTEMAC0DCMLOCKED;
+    input CLIENTEMAC0PAUSEREQ;
+    input CLIENTEMAC0RXCLIENTCLKIN;
+    input CLIENTEMAC0TXCLIENTCLKIN;
+    input CLIENTEMAC0TXDVLD;
+    input CLIENTEMAC0TXDVLDMSW;
+    input CLIENTEMAC0TXFIRSTBYTE;
+    input CLIENTEMAC0TXGMIIMIICLKIN;
+    input CLIENTEMAC0TXUNDERRUN;
+    input CLIENTEMAC1DCMLOCKED;
+    input CLIENTEMAC1PAUSEREQ;
+    input CLIENTEMAC1RXCLIENTCLKIN;
+    input CLIENTEMAC1TXCLIENTCLKIN;
+    input CLIENTEMAC1TXDVLD;
+    input CLIENTEMAC1TXDVLDMSW;
+    input CLIENTEMAC1TXFIRSTBYTE;
+    input CLIENTEMAC1TXGMIIMIICLKIN;
+    input CLIENTEMAC1TXUNDERRUN;
+    input DCREMACCLK;
+    input DCREMACENABLE;
+    input DCREMACREAD;
+    input DCREMACWRITE;
+    input HOSTCLK;
+    input HOSTEMAC1SEL;
+    input HOSTMIIMSEL;
+    input HOSTREQ;
+    input PHYEMAC0COL;
+    input PHYEMAC0CRS;
+    input PHYEMAC0GTXCLK;
+    input PHYEMAC0MCLKIN;
+    input PHYEMAC0MDIN;
+    input PHYEMAC0MIITXCLK;
+    input PHYEMAC0RXBUFERR;
+    input PHYEMAC0RXCHARISCOMMA;
+    input PHYEMAC0RXCHARISK;
+    input PHYEMAC0RXCHECKINGCRC;
+    input PHYEMAC0RXCLK;
+    input PHYEMAC0RXCOMMADET;
+    input PHYEMAC0RXDISPERR;
+    input PHYEMAC0RXDV;
+    input PHYEMAC0RXER;
+    input PHYEMAC0RXNOTINTABLE;
+    input PHYEMAC0RXRUNDISP;
+    input PHYEMAC0SIGNALDET;
+    input PHYEMAC0TXBUFERR;
+    input PHYEMAC1COL;
+    input PHYEMAC1CRS;
+    input PHYEMAC1GTXCLK;
+    input PHYEMAC1MCLKIN;
+    input PHYEMAC1MDIN;
+    input PHYEMAC1MIITXCLK;
+    input PHYEMAC1RXBUFERR;
+    input PHYEMAC1RXCHARISCOMMA;
+    input PHYEMAC1RXCHARISK;
+    input PHYEMAC1RXCHECKINGCRC;
+    input PHYEMAC1RXCLK;
+    input PHYEMAC1RXCOMMADET;
+    input PHYEMAC1RXDISPERR;
+    input PHYEMAC1RXDV;
+    input PHYEMAC1RXER;
+    input PHYEMAC1RXNOTINTABLE;
+    input PHYEMAC1RXRUNDISP;
+    input PHYEMAC1SIGNALDET;
+    input PHYEMAC1TXBUFERR;
+    input RESET;
+    input [0:31] DCREMACDBUS;
+    input [15:0] CLIENTEMAC0PAUSEVAL;
+    input [15:0] CLIENTEMAC0TXD;
+    input [15:0] CLIENTEMAC1PAUSEVAL;
+    input [15:0] CLIENTEMAC1TXD;
+    input [1:0] HOSTOPCODE;
+    input [1:0] PHYEMAC0RXBUFSTATUS;
+    input [1:0] PHYEMAC0RXLOSSOFSYNC;
+    input [1:0] PHYEMAC1RXBUFSTATUS;
+    input [1:0] PHYEMAC1RXLOSSOFSYNC;
+    input [2:0] PHYEMAC0RXCLKCORCNT;
+    input [2:0] PHYEMAC1RXCLKCORCNT;
+    input [31:0] HOSTWRDATA;
+    input [47:0] TIEEMAC0UNICASTADDR;
+    input [47:0] TIEEMAC1UNICASTADDR;
+    input [4:0] PHYEMAC0PHYAD;
+    input [4:0] PHYEMAC1PHYAD;
+    input [79:0] TIEEMAC0CONFIGVEC;
+    input [79:0] TIEEMAC1CONFIGVEC;
+    input [7:0] CLIENTEMAC0TXIFGDELAY;
+    input [7:0] CLIENTEMAC1TXIFGDELAY;
+    input [7:0] PHYEMAC0RXD;
+    input [7:0] PHYEMAC1RXD;
+    input [8:9] DCREMACABUS;
+    input [9:0] HOSTADDR;
+endmodule
+
+module TEMAC (...);
+    parameter EMAC0_1000BASEX_ENABLE = "FALSE";
+    parameter EMAC0_ADDRFILTER_ENABLE = "FALSE";
+    parameter EMAC0_BYTEPHY = "FALSE";
+    parameter EMAC0_CONFIGVEC_79 = "FALSE";
+    parameter EMAC0_GTLOOPBACK = "FALSE";
+    parameter EMAC0_HOST_ENABLE = "FALSE";
+    parameter EMAC0_LTCHECK_DISABLE = "FALSE";
+    parameter EMAC0_MDIO_ENABLE = "FALSE";
+    parameter EMAC0_PHYINITAUTONEG_ENABLE = "FALSE";
+    parameter EMAC0_PHYISOLATE = "FALSE";
+    parameter EMAC0_PHYLOOPBACKMSB = "FALSE";
+    parameter EMAC0_PHYPOWERDOWN = "FALSE";
+    parameter EMAC0_PHYRESET = "FALSE";
+    parameter EMAC0_RGMII_ENABLE = "FALSE";
+    parameter EMAC0_RX16BITCLIENT_ENABLE = "FALSE";
+    parameter EMAC0_RXFLOWCTRL_ENABLE = "FALSE";
+    parameter EMAC0_RXHALFDUPLEX = "FALSE";
+    parameter EMAC0_RXINBANDFCS_ENABLE = "FALSE";
+    parameter EMAC0_RXJUMBOFRAME_ENABLE = "FALSE";
+    parameter EMAC0_RXRESET = "FALSE";
+    parameter EMAC0_RXVLAN_ENABLE = "FALSE";
+    parameter EMAC0_RX_ENABLE = "FALSE";
+    parameter EMAC0_SGMII_ENABLE = "FALSE";
+    parameter EMAC0_SPEED_LSB = "FALSE";
+    parameter EMAC0_SPEED_MSB = "FALSE";
+    parameter EMAC0_TX16BITCLIENT_ENABLE = "FALSE";
+    parameter EMAC0_TXFLOWCTRL_ENABLE = "FALSE";
+    parameter EMAC0_TXHALFDUPLEX = "FALSE";
+    parameter EMAC0_TXIFGADJUST_ENABLE = "FALSE";
+    parameter EMAC0_TXINBANDFCS_ENABLE = "FALSE";
+    parameter EMAC0_TXJUMBOFRAME_ENABLE = "FALSE";
+    parameter EMAC0_TXRESET = "FALSE";
+    parameter EMAC0_TXVLAN_ENABLE = "FALSE";
+    parameter EMAC0_TX_ENABLE = "FALSE";
+    parameter EMAC0_UNIDIRECTION_ENABLE = "FALSE";
+    parameter EMAC0_USECLKEN = "FALSE";
+    parameter EMAC1_1000BASEX_ENABLE = "FALSE";
+    parameter EMAC1_ADDRFILTER_ENABLE = "FALSE";
+    parameter EMAC1_BYTEPHY = "FALSE";
+    parameter EMAC1_CONFIGVEC_79 = "FALSE";
+    parameter EMAC1_GTLOOPBACK = "FALSE";
+    parameter EMAC1_HOST_ENABLE = "FALSE";
+    parameter EMAC1_LTCHECK_DISABLE = "FALSE";
+    parameter EMAC1_MDIO_ENABLE = "FALSE";
+    parameter EMAC1_PHYINITAUTONEG_ENABLE = "FALSE";
+    parameter EMAC1_PHYISOLATE = "FALSE";
+    parameter EMAC1_PHYLOOPBACKMSB = "FALSE";
+    parameter EMAC1_PHYPOWERDOWN = "FALSE";
+    parameter EMAC1_PHYRESET = "FALSE";
+    parameter EMAC1_RGMII_ENABLE = "FALSE";
+    parameter EMAC1_RX16BITCLIENT_ENABLE = "FALSE";
+    parameter EMAC1_RXFLOWCTRL_ENABLE = "FALSE";
+    parameter EMAC1_RXHALFDUPLEX = "FALSE";
+    parameter EMAC1_RXINBANDFCS_ENABLE = "FALSE";
+    parameter EMAC1_RXJUMBOFRAME_ENABLE = "FALSE";
+    parameter EMAC1_RXRESET = "FALSE";
+    parameter EMAC1_RXVLAN_ENABLE = "FALSE";
+    parameter EMAC1_RX_ENABLE = "FALSE";
+    parameter EMAC1_SGMII_ENABLE = "FALSE";
+    parameter EMAC1_SPEED_LSB = "FALSE";
+    parameter EMAC1_SPEED_MSB = "FALSE";
+    parameter EMAC1_TX16BITCLIENT_ENABLE = "FALSE";
+    parameter EMAC1_TXFLOWCTRL_ENABLE = "FALSE";
+    parameter EMAC1_TXHALFDUPLEX = "FALSE";
+    parameter EMAC1_TXIFGADJUST_ENABLE = "FALSE";
+    parameter EMAC1_TXINBANDFCS_ENABLE = "FALSE";
+    parameter EMAC1_TXJUMBOFRAME_ENABLE = "FALSE";
+    parameter EMAC1_TXRESET = "FALSE";
+    parameter EMAC1_TXVLAN_ENABLE = "FALSE";
+    parameter EMAC1_TX_ENABLE = "FALSE";
+    parameter EMAC1_UNIDIRECTION_ENABLE = "FALSE";
+    parameter EMAC1_USECLKEN = "FALSE";
+    parameter [0:7] EMAC0_DCRBASEADDR = 8'h00;
+    parameter [0:7] EMAC1_DCRBASEADDR = 8'h00;
+    parameter [47:0] EMAC0_PAUSEADDR = 48'h000000000000;
+    parameter [47:0] EMAC0_UNICASTADDR = 48'h000000000000;
+    parameter [47:0] EMAC1_PAUSEADDR = 48'h000000000000;
+    parameter [47:0] EMAC1_UNICASTADDR = 48'h000000000000;
+    parameter [8:0] EMAC0_LINKTIMERVAL = 9'h000;
+    parameter [8:0] EMAC1_LINKTIMERVAL = 9'h000;
+    output DCRHOSTDONEIR;
+    output EMAC0CLIENTANINTERRUPT;
+    output EMAC0CLIENTRXBADFRAME;
+    output EMAC0CLIENTRXCLIENTCLKOUT;
+    output EMAC0CLIENTRXDVLD;
+    output EMAC0CLIENTRXDVLDMSW;
+    output EMAC0CLIENTRXFRAMEDROP;
+    output EMAC0CLIENTRXGOODFRAME;
+    output EMAC0CLIENTRXSTATSBYTEVLD;
+    output EMAC0CLIENTRXSTATSVLD;
+    output EMAC0CLIENTTXACK;
+    output EMAC0CLIENTTXCLIENTCLKOUT;
+    output EMAC0CLIENTTXCOLLISION;
+    output EMAC0CLIENTTXRETRANSMIT;
+    output EMAC0CLIENTTXSTATS;
+    output EMAC0CLIENTTXSTATSBYTEVLD;
+    output EMAC0CLIENTTXSTATSVLD;
+    output EMAC0PHYENCOMMAALIGN;
+    output EMAC0PHYLOOPBACKMSB;
+    output EMAC0PHYMCLKOUT;
+    output EMAC0PHYMDOUT;
+    output EMAC0PHYMDTRI;
+    output EMAC0PHYMGTRXRESET;
+    output EMAC0PHYMGTTXRESET;
+    output EMAC0PHYPOWERDOWN;
+    output EMAC0PHYSYNCACQSTATUS;
+    output EMAC0PHYTXCHARDISPMODE;
+    output EMAC0PHYTXCHARDISPVAL;
+    output EMAC0PHYTXCHARISK;
+    output EMAC0PHYTXCLK;
+    output EMAC0PHYTXEN;
+    output EMAC0PHYTXER;
+    output EMAC0PHYTXGMIIMIICLKOUT;
+    output EMAC0SPEEDIS10100;
+    output EMAC1CLIENTANINTERRUPT;
+    output EMAC1CLIENTRXBADFRAME;
+    output EMAC1CLIENTRXCLIENTCLKOUT;
+    output EMAC1CLIENTRXDVLD;
+    output EMAC1CLIENTRXDVLDMSW;
+    output EMAC1CLIENTRXFRAMEDROP;
+    output EMAC1CLIENTRXGOODFRAME;
+    output EMAC1CLIENTRXSTATSBYTEVLD;
+    output EMAC1CLIENTRXSTATSVLD;
+    output EMAC1CLIENTTXACK;
+    output EMAC1CLIENTTXCLIENTCLKOUT;
+    output EMAC1CLIENTTXCOLLISION;
+    output EMAC1CLIENTTXRETRANSMIT;
+    output EMAC1CLIENTTXSTATS;
+    output EMAC1CLIENTTXSTATSBYTEVLD;
+    output EMAC1CLIENTTXSTATSVLD;
+    output EMAC1PHYENCOMMAALIGN;
+    output EMAC1PHYLOOPBACKMSB;
+    output EMAC1PHYMCLKOUT;
+    output EMAC1PHYMDOUT;
+    output EMAC1PHYMDTRI;
+    output EMAC1PHYMGTRXRESET;
+    output EMAC1PHYMGTTXRESET;
+    output EMAC1PHYPOWERDOWN;
+    output EMAC1PHYSYNCACQSTATUS;
+    output EMAC1PHYTXCHARDISPMODE;
+    output EMAC1PHYTXCHARDISPVAL;
+    output EMAC1PHYTXCHARISK;
+    output EMAC1PHYTXCLK;
+    output EMAC1PHYTXEN;
+    output EMAC1PHYTXER;
+    output EMAC1PHYTXGMIIMIICLKOUT;
+    output EMAC1SPEEDIS10100;
+    output EMACDCRACK;
+    output HOSTMIIMRDY;
+    output [0:31] EMACDCRDBUS;
+    output [15:0] EMAC0CLIENTRXD;
+    output [15:0] EMAC1CLIENTRXD;
+    output [31:0] HOSTRDDATA;
+    output [6:0] EMAC0CLIENTRXSTATS;
+    output [6:0] EMAC1CLIENTRXSTATS;
+    output [7:0] EMAC0PHYTXD;
+    output [7:0] EMAC1PHYTXD;
+    input CLIENTEMAC0DCMLOCKED;
+    input CLIENTEMAC0PAUSEREQ;
+    input CLIENTEMAC0RXCLIENTCLKIN;
+    input CLIENTEMAC0TXCLIENTCLKIN;
+    input CLIENTEMAC0TXDVLD;
+    input CLIENTEMAC0TXDVLDMSW;
+    input CLIENTEMAC0TXFIRSTBYTE;
+    input CLIENTEMAC0TXUNDERRUN;
+    input CLIENTEMAC1DCMLOCKED;
+    input CLIENTEMAC1PAUSEREQ;
+    input CLIENTEMAC1RXCLIENTCLKIN;
+    input CLIENTEMAC1TXCLIENTCLKIN;
+    input CLIENTEMAC1TXDVLD;
+    input CLIENTEMAC1TXDVLDMSW;
+    input CLIENTEMAC1TXFIRSTBYTE;
+    input CLIENTEMAC1TXUNDERRUN;
+    input DCREMACCLK;
+    input DCREMACENABLE;
+    input DCREMACREAD;
+    input DCREMACWRITE;
+    input HOSTCLK;
+    input HOSTEMAC1SEL;
+    input HOSTMIIMSEL;
+    input HOSTREQ;
+    input PHYEMAC0COL;
+    input PHYEMAC0CRS;
+    input PHYEMAC0GTXCLK;
+    input PHYEMAC0MCLKIN;
+    input PHYEMAC0MDIN;
+    input PHYEMAC0MIITXCLK;
+    input PHYEMAC0RXBUFERR;
+    input PHYEMAC0RXCHARISCOMMA;
+    input PHYEMAC0RXCHARISK;
+    input PHYEMAC0RXCHECKINGCRC;
+    input PHYEMAC0RXCLK;
+    input PHYEMAC0RXCOMMADET;
+    input PHYEMAC0RXDISPERR;
+    input PHYEMAC0RXDV;
+    input PHYEMAC0RXER;
+    input PHYEMAC0RXNOTINTABLE;
+    input PHYEMAC0RXRUNDISP;
+    input PHYEMAC0SIGNALDET;
+    input PHYEMAC0TXBUFERR;
+    input PHYEMAC0TXGMIIMIICLKIN;
+    input PHYEMAC1COL;
+    input PHYEMAC1CRS;
+    input PHYEMAC1GTXCLK;
+    input PHYEMAC1MCLKIN;
+    input PHYEMAC1MDIN;
+    input PHYEMAC1MIITXCLK;
+    input PHYEMAC1RXBUFERR;
+    input PHYEMAC1RXCHARISCOMMA;
+    input PHYEMAC1RXCHARISK;
+    input PHYEMAC1RXCHECKINGCRC;
+    input PHYEMAC1RXCLK;
+    input PHYEMAC1RXCOMMADET;
+    input PHYEMAC1RXDISPERR;
+    input PHYEMAC1RXDV;
+    input PHYEMAC1RXER;
+    input PHYEMAC1RXNOTINTABLE;
+    input PHYEMAC1RXRUNDISP;
+    input PHYEMAC1SIGNALDET;
+    input PHYEMAC1TXBUFERR;
+    input PHYEMAC1TXGMIIMIICLKIN;
+    input RESET;
+    input [0:31] DCREMACDBUS;
+    input [0:9] DCREMACABUS;
+    input [15:0] CLIENTEMAC0PAUSEVAL;
+    input [15:0] CLIENTEMAC0TXD;
+    input [15:0] CLIENTEMAC1PAUSEVAL;
+    input [15:0] CLIENTEMAC1TXD;
+    input [1:0] HOSTOPCODE;
+    input [1:0] PHYEMAC0RXBUFSTATUS;
+    input [1:0] PHYEMAC0RXLOSSOFSYNC;
+    input [1:0] PHYEMAC1RXBUFSTATUS;
+    input [1:0] PHYEMAC1RXLOSSOFSYNC;
+    input [2:0] PHYEMAC0RXCLKCORCNT;
+    input [2:0] PHYEMAC1RXCLKCORCNT;
+    input [31:0] HOSTWRDATA;
+    input [4:0] PHYEMAC0PHYAD;
+    input [4:0] PHYEMAC1PHYAD;
+    input [7:0] CLIENTEMAC0TXIFGDELAY;
+    input [7:0] CLIENTEMAC1TXIFGDELAY;
+    input [7:0] PHYEMAC0RXD;
+    input [7:0] PHYEMAC1RXD;
+    input [9:0] HOSTADDR;
+endmodule
+
+module TEMAC_SINGLE (...);
+    parameter EMAC_1000BASEX_ENABLE = "FALSE";
+    parameter EMAC_ADDRFILTER_ENABLE = "FALSE";
+    parameter EMAC_BYTEPHY = "FALSE";
+    parameter EMAC_CTRLLENCHECK_DISABLE = "FALSE";
+    parameter [0:7] EMAC_DCRBASEADDR = 8'h00;
+    parameter EMAC_GTLOOPBACK = "FALSE";
+    parameter EMAC_HOST_ENABLE = "FALSE";
+    parameter [8:0] EMAC_LINKTIMERVAL = 9'h000;
+    parameter EMAC_LTCHECK_DISABLE = "FALSE";
+    parameter EMAC_MDIO_ENABLE = "FALSE";
+    parameter EMAC_MDIO_IGNORE_PHYADZERO = "FALSE";
+    parameter [47:0] EMAC_PAUSEADDR = 48'h000000000000;
+    parameter EMAC_PHYINITAUTONEG_ENABLE = "FALSE";
+    parameter EMAC_PHYISOLATE = "FALSE";
+    parameter EMAC_PHYLOOPBACKMSB = "FALSE";
+    parameter EMAC_PHYPOWERDOWN = "FALSE";
+    parameter EMAC_PHYRESET = "FALSE";
+    parameter EMAC_RGMII_ENABLE = "FALSE";
+    parameter EMAC_RX16BITCLIENT_ENABLE = "FALSE";
+    parameter EMAC_RXFLOWCTRL_ENABLE = "FALSE";
+    parameter EMAC_RXHALFDUPLEX = "FALSE";
+    parameter EMAC_RXINBANDFCS_ENABLE = "FALSE";
+    parameter EMAC_RXJUMBOFRAME_ENABLE = "FALSE";
+    parameter EMAC_RXRESET = "FALSE";
+    parameter EMAC_RXVLAN_ENABLE = "FALSE";
+    parameter EMAC_RX_ENABLE = "TRUE";
+    parameter EMAC_SGMII_ENABLE = "FALSE";
+    parameter EMAC_SPEED_LSB = "FALSE";
+    parameter EMAC_SPEED_MSB = "FALSE";
+    parameter EMAC_TX16BITCLIENT_ENABLE = "FALSE";
+    parameter EMAC_TXFLOWCTRL_ENABLE = "FALSE";
+    parameter EMAC_TXHALFDUPLEX = "FALSE";
+    parameter EMAC_TXIFGADJUST_ENABLE = "FALSE";
+    parameter EMAC_TXINBANDFCS_ENABLE = "FALSE";
+    parameter EMAC_TXJUMBOFRAME_ENABLE = "FALSE";
+    parameter EMAC_TXRESET = "FALSE";
+    parameter EMAC_TXVLAN_ENABLE = "FALSE";
+    parameter EMAC_TX_ENABLE = "TRUE";
+    parameter [47:0] EMAC_UNICASTADDR = 48'h000000000000;
+    parameter EMAC_UNIDIRECTION_ENABLE = "FALSE";
+    parameter EMAC_USECLKEN = "FALSE";
+    parameter SIM_VERSION = "1.0";
+    output DCRHOSTDONEIR;
+    output EMACCLIENTANINTERRUPT;
+    output EMACCLIENTRXBADFRAME;
+    output EMACCLIENTRXCLIENTCLKOUT;
+    output EMACCLIENTRXDVLD;
+    output EMACCLIENTRXDVLDMSW;
+    output EMACCLIENTRXFRAMEDROP;
+    output EMACCLIENTRXGOODFRAME;
+    output EMACCLIENTRXSTATSBYTEVLD;
+    output EMACCLIENTRXSTATSVLD;
+    output EMACCLIENTTXACK;
+    output EMACCLIENTTXCLIENTCLKOUT;
+    output EMACCLIENTTXCOLLISION;
+    output EMACCLIENTTXRETRANSMIT;
+    output EMACCLIENTTXSTATS;
+    output EMACCLIENTTXSTATSBYTEVLD;
+    output EMACCLIENTTXSTATSVLD;
+    output EMACDCRACK;
+    output EMACPHYENCOMMAALIGN;
+    output EMACPHYLOOPBACKMSB;
+    output EMACPHYMCLKOUT;
+    output EMACPHYMDOUT;
+    output EMACPHYMDTRI;
+    output EMACPHYMGTRXRESET;
+    output EMACPHYMGTTXRESET;
+    output EMACPHYPOWERDOWN;
+    output EMACPHYSYNCACQSTATUS;
+    output EMACPHYTXCHARDISPMODE;
+    output EMACPHYTXCHARDISPVAL;
+    output EMACPHYTXCHARISK;
+    output EMACPHYTXCLK;
+    output EMACPHYTXEN;
+    output EMACPHYTXER;
+    output EMACPHYTXGMIIMIICLKOUT;
+    output EMACSPEEDIS10100;
+    output HOSTMIIMRDY;
+    output [0:31] EMACDCRDBUS;
+    output [15:0] EMACCLIENTRXD;
+    output [31:0] HOSTRDDATA;
+    output [6:0] EMACCLIENTRXSTATS;
+    output [7:0] EMACPHYTXD;
+    input CLIENTEMACDCMLOCKED;
+    input CLIENTEMACPAUSEREQ;
+    input CLIENTEMACRXCLIENTCLKIN;
+    input CLIENTEMACTXCLIENTCLKIN;
+    input CLIENTEMACTXDVLD;
+    input CLIENTEMACTXDVLDMSW;
+    input CLIENTEMACTXFIRSTBYTE;
+    input CLIENTEMACTXUNDERRUN;
+    input DCREMACCLK;
+    input DCREMACENABLE;
+    input DCREMACREAD;
+    input DCREMACWRITE;
+    input HOSTCLK;
+    input HOSTMIIMSEL;
+    input HOSTREQ;
+    input PHYEMACCOL;
+    input PHYEMACCRS;
+    input PHYEMACGTXCLK;
+    input PHYEMACMCLKIN;
+    input PHYEMACMDIN;
+    input PHYEMACMIITXCLK;
+    input PHYEMACRXCHARISCOMMA;
+    input PHYEMACRXCHARISK;
+    input PHYEMACRXCLK;
+    input PHYEMACRXDISPERR;
+    input PHYEMACRXDV;
+    input PHYEMACRXER;
+    input PHYEMACRXNOTINTABLE;
+    input PHYEMACRXRUNDISP;
+    input PHYEMACSIGNALDET;
+    input PHYEMACTXBUFERR;
+    input PHYEMACTXGMIIMIICLKIN;
+    input RESET;
+    input [0:31] DCREMACDBUS;
+    input [0:9] DCREMACABUS;
+    input [15:0] CLIENTEMACPAUSEVAL;
+    input [15:0] CLIENTEMACTXD;
+    input [1:0] HOSTOPCODE;
+    input [1:0] PHYEMACRXBUFSTATUS;
+    input [2:0] PHYEMACRXCLKCORCNT;
+    input [31:0] HOSTWRDATA;
+    input [4:0] PHYEMACPHYAD;
+    input [7:0] CLIENTEMACTXIFGDELAY;
+    input [7:0] PHYEMACRXD;
+    input [9:0] HOSTADDR;
+endmodule
+
+module CMAC (...);
+    parameter CTL_PTP_TRANSPCLK_MODE = "FALSE";
+    parameter CTL_RX_CHECK_ACK = "TRUE";
+    parameter CTL_RX_CHECK_PREAMBLE = "FALSE";
+    parameter CTL_RX_CHECK_SFD = "FALSE";
+    parameter CTL_RX_DELETE_FCS = "TRUE";
+    parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808;
+    parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808;
+    parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808;
+    parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808;
+    parameter CTL_RX_FORWARD_CONTROL = "FALSE";
+    parameter CTL_RX_IGNORE_FCS = "FALSE";
+    parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580;
+    parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40;
+    parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001;
+    parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF;
+    parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF;
+    parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000;
+    parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000;
+    parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001;
+    parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001;
+    parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000;
+    parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000;
+    parameter CTL_RX_PROCESS_LFI = "FALSE";
+    parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF;
+    parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
+    parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
+    parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600;
+    parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
+    parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
+    parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
+    parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
+    parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
+    parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
+    parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800;
+    parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
+    parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
+    parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
+    parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
+    parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
+    parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
+    parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
+    parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
+    parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
+    parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
+    parameter CTL_TEST_MODE_PIN_CHAR = "FALSE";
+    parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001;
+    parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001;
+    parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808;
+    parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808;
+    parameter CTL_TX_FCS_INS_ENABLE = "TRUE";
+    parameter CTL_TX_IGNORE_FCS = "FALSE";
+    parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001;
+    parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001;
+    parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE";
+    parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1;
+    parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000;
+    parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000;
+    parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF;
+    parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
+    parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
+    parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600;
+    parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
+    parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
+    parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
+    parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
+    parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
+    parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
+    parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800;
+    parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
+    parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
+    parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
+    parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
+    parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
+    parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
+    parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
+    parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
+    parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
+    parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
+    parameter SIM_VERSION = "2.0";
+    parameter TEST_MODE_PIN_CHAR = "FALSE";
+    output [15:0] DRP_DO;
+    output DRP_RDY;
+    output [127:0] RX_DATAOUT0;
+    output [127:0] RX_DATAOUT1;
+    output [127:0] RX_DATAOUT2;
+    output [127:0] RX_DATAOUT3;
+    output RX_ENAOUT0;
+    output RX_ENAOUT1;
+    output RX_ENAOUT2;
+    output RX_ENAOUT3;
+    output RX_EOPOUT0;
+    output RX_EOPOUT1;
+    output RX_EOPOUT2;
+    output RX_EOPOUT3;
+    output RX_ERROUT0;
+    output RX_ERROUT1;
+    output RX_ERROUT2;
+    output RX_ERROUT3;
+    output [6:0] RX_LANE_ALIGNER_FILL_0;
+    output [6:0] RX_LANE_ALIGNER_FILL_1;
+    output [6:0] RX_LANE_ALIGNER_FILL_10;
+    output [6:0] RX_LANE_ALIGNER_FILL_11;
+    output [6:0] RX_LANE_ALIGNER_FILL_12;
+    output [6:0] RX_LANE_ALIGNER_FILL_13;
+    output [6:0] RX_LANE_ALIGNER_FILL_14;
+    output [6:0] RX_LANE_ALIGNER_FILL_15;
+    output [6:0] RX_LANE_ALIGNER_FILL_16;
+    output [6:0] RX_LANE_ALIGNER_FILL_17;
+    output [6:0] RX_LANE_ALIGNER_FILL_18;
+    output [6:0] RX_LANE_ALIGNER_FILL_19;
+    output [6:0] RX_LANE_ALIGNER_FILL_2;
+    output [6:0] RX_LANE_ALIGNER_FILL_3;
+    output [6:0] RX_LANE_ALIGNER_FILL_4;
+    output [6:0] RX_LANE_ALIGNER_FILL_5;
+    output [6:0] RX_LANE_ALIGNER_FILL_6;
+    output [6:0] RX_LANE_ALIGNER_FILL_7;
+    output [6:0] RX_LANE_ALIGNER_FILL_8;
+    output [6:0] RX_LANE_ALIGNER_FILL_9;
+    output [3:0] RX_MTYOUT0;
+    output [3:0] RX_MTYOUT1;
+    output [3:0] RX_MTYOUT2;
+    output [3:0] RX_MTYOUT3;
+    output [4:0] RX_PTP_PCSLANE_OUT;
+    output [79:0] RX_PTP_TSTAMP_OUT;
+    output RX_SOPOUT0;
+    output RX_SOPOUT1;
+    output RX_SOPOUT2;
+    output RX_SOPOUT3;
+    output STAT_RX_ALIGNED;
+    output STAT_RX_ALIGNED_ERR;
+    output [6:0] STAT_RX_BAD_CODE;
+    output [3:0] STAT_RX_BAD_FCS;
+    output STAT_RX_BAD_PREAMBLE;
+    output STAT_RX_BAD_SFD;
+    output STAT_RX_BIP_ERR_0;
+    output STAT_RX_BIP_ERR_1;
+    output STAT_RX_BIP_ERR_10;
+    output STAT_RX_BIP_ERR_11;
+    output STAT_RX_BIP_ERR_12;
+    output STAT_RX_BIP_ERR_13;
+    output STAT_RX_BIP_ERR_14;
+    output STAT_RX_BIP_ERR_15;
+    output STAT_RX_BIP_ERR_16;
+    output STAT_RX_BIP_ERR_17;
+    output STAT_RX_BIP_ERR_18;
+    output STAT_RX_BIP_ERR_19;
+    output STAT_RX_BIP_ERR_2;
+    output STAT_RX_BIP_ERR_3;
+    output STAT_RX_BIP_ERR_4;
+    output STAT_RX_BIP_ERR_5;
+    output STAT_RX_BIP_ERR_6;
+    output STAT_RX_BIP_ERR_7;
+    output STAT_RX_BIP_ERR_8;
+    output STAT_RX_BIP_ERR_9;
+    output [19:0] STAT_RX_BLOCK_LOCK;
+    output STAT_RX_BROADCAST;
+    output [3:0] STAT_RX_FRAGMENT;
+    output [3:0] STAT_RX_FRAMING_ERR_0;
+    output [3:0] STAT_RX_FRAMING_ERR_1;
+    output [3:0] STAT_RX_FRAMING_ERR_10;
+    output [3:0] STAT_RX_FRAMING_ERR_11;
+    output [3:0] STAT_RX_FRAMING_ERR_12;
+    output [3:0] STAT_RX_FRAMING_ERR_13;
+    output [3:0] STAT_RX_FRAMING_ERR_14;
+    output [3:0] STAT_RX_FRAMING_ERR_15;
+    output [3:0] STAT_RX_FRAMING_ERR_16;
+    output [3:0] STAT_RX_FRAMING_ERR_17;
+    output [3:0] STAT_RX_FRAMING_ERR_18;
+    output [3:0] STAT_RX_FRAMING_ERR_19;
+    output [3:0] STAT_RX_FRAMING_ERR_2;
+    output [3:0] STAT_RX_FRAMING_ERR_3;
+    output [3:0] STAT_RX_FRAMING_ERR_4;
+    output [3:0] STAT_RX_FRAMING_ERR_5;
+    output [3:0] STAT_RX_FRAMING_ERR_6;
+    output [3:0] STAT_RX_FRAMING_ERR_7;
+    output [3:0] STAT_RX_FRAMING_ERR_8;
+    output [3:0] STAT_RX_FRAMING_ERR_9;
+    output STAT_RX_FRAMING_ERR_VALID_0;
+    output STAT_RX_FRAMING_ERR_VALID_1;
+    output STAT_RX_FRAMING_ERR_VALID_10;
+    output STAT_RX_FRAMING_ERR_VALID_11;
+    output STAT_RX_FRAMING_ERR_VALID_12;
+    output STAT_RX_FRAMING_ERR_VALID_13;
+    output STAT_RX_FRAMING_ERR_VALID_14;
+    output STAT_RX_FRAMING_ERR_VALID_15;
+    output STAT_RX_FRAMING_ERR_VALID_16;
+    output STAT_RX_FRAMING_ERR_VALID_17;
+    output STAT_RX_FRAMING_ERR_VALID_18;
+    output STAT_RX_FRAMING_ERR_VALID_19;
+    output STAT_RX_FRAMING_ERR_VALID_2;
+    output STAT_RX_FRAMING_ERR_VALID_3;
+    output STAT_RX_FRAMING_ERR_VALID_4;
+    output STAT_RX_FRAMING_ERR_VALID_5;
+    output STAT_RX_FRAMING_ERR_VALID_6;
+    output STAT_RX_FRAMING_ERR_VALID_7;
+    output STAT_RX_FRAMING_ERR_VALID_8;
+    output STAT_RX_FRAMING_ERR_VALID_9;
+    output STAT_RX_GOT_SIGNAL_OS;
+    output STAT_RX_HI_BER;
+    output STAT_RX_INRANGEERR;
+    output STAT_RX_INTERNAL_LOCAL_FAULT;
+    output STAT_RX_JABBER;
+    output [7:0] STAT_RX_LANE0_VLM_BIP7;
+    output STAT_RX_LANE0_VLM_BIP7_VALID;
+    output STAT_RX_LOCAL_FAULT;
+    output [19:0] STAT_RX_MF_ERR;
+    output [19:0] STAT_RX_MF_LEN_ERR;
+    output [19:0] STAT_RX_MF_REPEAT_ERR;
+    output STAT_RX_MISALIGNED;
+    output STAT_RX_MULTICAST;
+    output STAT_RX_OVERSIZE;
+    output STAT_RX_PACKET_1024_1518_BYTES;
+    output STAT_RX_PACKET_128_255_BYTES;
+    output STAT_RX_PACKET_1519_1522_BYTES;
+    output STAT_RX_PACKET_1523_1548_BYTES;
+    output STAT_RX_PACKET_1549_2047_BYTES;
+    output STAT_RX_PACKET_2048_4095_BYTES;
+    output STAT_RX_PACKET_256_511_BYTES;
+    output STAT_RX_PACKET_4096_8191_BYTES;
+    output STAT_RX_PACKET_512_1023_BYTES;
+    output STAT_RX_PACKET_64_BYTES;
+    output STAT_RX_PACKET_65_127_BYTES;
+    output STAT_RX_PACKET_8192_9215_BYTES;
+    output STAT_RX_PACKET_BAD_FCS;
+    output STAT_RX_PACKET_LARGE;
+    output [3:0] STAT_RX_PACKET_SMALL;
+    output STAT_RX_PAUSE;
+    output [15:0] STAT_RX_PAUSE_QUANTA0;
+    output [15:0] STAT_RX_PAUSE_QUANTA1;
+    output [15:0] STAT_RX_PAUSE_QUANTA2;
+    output [15:0] STAT_RX_PAUSE_QUANTA3;
+    output [15:0] STAT_RX_PAUSE_QUANTA4;
+    output [15:0] STAT_RX_PAUSE_QUANTA5;
+    output [15:0] STAT_RX_PAUSE_QUANTA6;
+    output [15:0] STAT_RX_PAUSE_QUANTA7;
+    output [15:0] STAT_RX_PAUSE_QUANTA8;
+    output [8:0] STAT_RX_PAUSE_REQ;
+    output [8:0] STAT_RX_PAUSE_VALID;
+    output STAT_RX_RECEIVED_LOCAL_FAULT;
+    output STAT_RX_REMOTE_FAULT;
+    output STAT_RX_STATUS;
+    output [3:0] STAT_RX_STOMPED_FCS;
+    output [19:0] STAT_RX_SYNCED;
+    output [19:0] STAT_RX_SYNCED_ERR;
+    output [2:0] STAT_RX_TEST_PATTERN_MISMATCH;
+    output STAT_RX_TOOLONG;
+    output [7:0] STAT_RX_TOTAL_BYTES;
+    output [13:0] STAT_RX_TOTAL_GOOD_BYTES;
+    output STAT_RX_TOTAL_GOOD_PACKETS;
+    output [3:0] STAT_RX_TOTAL_PACKETS;
+    output STAT_RX_TRUNCATED;
+    output [3:0] STAT_RX_UNDERSIZE;
+    output STAT_RX_UNICAST;
+    output STAT_RX_USER_PAUSE;
+    output STAT_RX_VLAN;
+    output [19:0] STAT_RX_VL_DEMUXED;
+    output [4:0] STAT_RX_VL_NUMBER_0;
+    output [4:0] STAT_RX_VL_NUMBER_1;
+    output [4:0] STAT_RX_VL_NUMBER_10;
+    output [4:0] STAT_RX_VL_NUMBER_11;
+    output [4:0] STAT_RX_VL_NUMBER_12;
+    output [4:0] STAT_RX_VL_NUMBER_13;
+    output [4:0] STAT_RX_VL_NUMBER_14;
+    output [4:0] STAT_RX_VL_NUMBER_15;
+    output [4:0] STAT_RX_VL_NUMBER_16;
+    output [4:0] STAT_RX_VL_NUMBER_17;
+    output [4:0] STAT_RX_VL_NUMBER_18;
+    output [4:0] STAT_RX_VL_NUMBER_19;
+    output [4:0] STAT_RX_VL_NUMBER_2;
+    output [4:0] STAT_RX_VL_NUMBER_3;
+    output [4:0] STAT_RX_VL_NUMBER_4;
+    output [4:0] STAT_RX_VL_NUMBER_5;
+    output [4:0] STAT_RX_VL_NUMBER_6;
+    output [4:0] STAT_RX_VL_NUMBER_7;
+    output [4:0] STAT_RX_VL_NUMBER_8;
+    output [4:0] STAT_RX_VL_NUMBER_9;
+    output STAT_TX_BAD_FCS;
+    output STAT_TX_BROADCAST;
+    output STAT_TX_FRAME_ERROR;
+    output STAT_TX_LOCAL_FAULT;
+    output STAT_TX_MULTICAST;
+    output STAT_TX_PACKET_1024_1518_BYTES;
+    output STAT_TX_PACKET_128_255_BYTES;
+    output STAT_TX_PACKET_1519_1522_BYTES;
+    output STAT_TX_PACKET_1523_1548_BYTES;
+    output STAT_TX_PACKET_1549_2047_BYTES;
+    output STAT_TX_PACKET_2048_4095_BYTES;
+    output STAT_TX_PACKET_256_511_BYTES;
+    output STAT_TX_PACKET_4096_8191_BYTES;
+    output STAT_TX_PACKET_512_1023_BYTES;
+    output STAT_TX_PACKET_64_BYTES;
+    output STAT_TX_PACKET_65_127_BYTES;
+    output STAT_TX_PACKET_8192_9215_BYTES;
+    output STAT_TX_PACKET_LARGE;
+    output STAT_TX_PACKET_SMALL;
+    output STAT_TX_PAUSE;
+    output [8:0] STAT_TX_PAUSE_VALID;
+    output STAT_TX_PTP_FIFO_READ_ERROR;
+    output STAT_TX_PTP_FIFO_WRITE_ERROR;
+    output [6:0] STAT_TX_TOTAL_BYTES;
+    output [13:0] STAT_TX_TOTAL_GOOD_BYTES;
+    output STAT_TX_TOTAL_GOOD_PACKETS;
+    output STAT_TX_TOTAL_PACKETS;
+    output STAT_TX_UNICAST;
+    output STAT_TX_USER_PAUSE;
+    output STAT_TX_VLAN;
+    output TX_OVFOUT;
+    output [4:0] TX_PTP_PCSLANE_OUT;
+    output [79:0] TX_PTP_TSTAMP_OUT;
+    output [15:0] TX_PTP_TSTAMP_TAG_OUT;
+    output TX_PTP_TSTAMP_VALID_OUT;
+    output TX_RDYOUT;
+    output [15:0] TX_SERDES_ALT_DATA0;
+    output [15:0] TX_SERDES_ALT_DATA1;
+    output [15:0] TX_SERDES_ALT_DATA2;
+    output [15:0] TX_SERDES_ALT_DATA3;
+    output [63:0] TX_SERDES_DATA0;
+    output [63:0] TX_SERDES_DATA1;
+    output [63:0] TX_SERDES_DATA2;
+    output [63:0] TX_SERDES_DATA3;
+    output [31:0] TX_SERDES_DATA4;
+    output [31:0] TX_SERDES_DATA5;
+    output [31:0] TX_SERDES_DATA6;
+    output [31:0] TX_SERDES_DATA7;
+    output [31:0] TX_SERDES_DATA8;
+    output [31:0] TX_SERDES_DATA9;
+    output TX_UNFOUT;
+    input CTL_CAUI4_MODE;
+    input CTL_RX_CHECK_ETYPE_GCP;
+    input CTL_RX_CHECK_ETYPE_GPP;
+    input CTL_RX_CHECK_ETYPE_PCP;
+    input CTL_RX_CHECK_ETYPE_PPP;
+    input CTL_RX_CHECK_MCAST_GCP;
+    input CTL_RX_CHECK_MCAST_GPP;
+    input CTL_RX_CHECK_MCAST_PCP;
+    input CTL_RX_CHECK_MCAST_PPP;
+    input CTL_RX_CHECK_OPCODE_GCP;
+    input CTL_RX_CHECK_OPCODE_GPP;
+    input CTL_RX_CHECK_OPCODE_PCP;
+    input CTL_RX_CHECK_OPCODE_PPP;
+    input CTL_RX_CHECK_SA_GCP;
+    input CTL_RX_CHECK_SA_GPP;
+    input CTL_RX_CHECK_SA_PCP;
+    input CTL_RX_CHECK_SA_PPP;
+    input CTL_RX_CHECK_UCAST_GCP;
+    input CTL_RX_CHECK_UCAST_GPP;
+    input CTL_RX_CHECK_UCAST_PCP;
+    input CTL_RX_CHECK_UCAST_PPP;
+    input CTL_RX_ENABLE;
+    input CTL_RX_ENABLE_GCP;
+    input CTL_RX_ENABLE_GPP;
+    input CTL_RX_ENABLE_PCP;
+    input CTL_RX_ENABLE_PPP;
+    input CTL_RX_FORCE_RESYNC;
+    input [8:0] CTL_RX_PAUSE_ACK;
+    input [8:0] CTL_RX_PAUSE_ENABLE;
+    input [79:0] CTL_RX_SYSTEMTIMERIN;
+    input CTL_RX_TEST_PATTERN;
+    input CTL_TX_ENABLE;
+    input CTL_TX_LANE0_VLM_BIP7_OVERRIDE;
+    input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE;
+    input [8:0] CTL_TX_PAUSE_ENABLE;
+    input [15:0] CTL_TX_PAUSE_QUANTA0;
+    input [15:0] CTL_TX_PAUSE_QUANTA1;
+    input [15:0] CTL_TX_PAUSE_QUANTA2;
+    input [15:0] CTL_TX_PAUSE_QUANTA3;
+    input [15:0] CTL_TX_PAUSE_QUANTA4;
+    input [15:0] CTL_TX_PAUSE_QUANTA5;
+    input [15:0] CTL_TX_PAUSE_QUANTA6;
+    input [15:0] CTL_TX_PAUSE_QUANTA7;
+    input [15:0] CTL_TX_PAUSE_QUANTA8;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8;
+    input [8:0] CTL_TX_PAUSE_REQ;
+    input CTL_TX_PTP_VLANE_ADJUST_MODE;
+    input CTL_TX_RESEND_PAUSE;
+    input CTL_TX_SEND_IDLE;
+    input CTL_TX_SEND_RFI;
+    input [79:0] CTL_TX_SYSTEMTIMERIN;
+    input CTL_TX_TEST_PATTERN;
+    input [9:0] DRP_ADDR;
+    input DRP_CLK;
+    input [15:0] DRP_DI;
+    input DRP_EN;
+    input DRP_WE;
+    input RX_CLK;
+    input RX_RESET;
+    input [15:0] RX_SERDES_ALT_DATA0;
+    input [15:0] RX_SERDES_ALT_DATA1;
+    input [15:0] RX_SERDES_ALT_DATA2;
+    input [15:0] RX_SERDES_ALT_DATA3;
+    input [9:0] RX_SERDES_CLK;
+    input [63:0] RX_SERDES_DATA0;
+    input [63:0] RX_SERDES_DATA1;
+    input [63:0] RX_SERDES_DATA2;
+    input [63:0] RX_SERDES_DATA3;
+    input [31:0] RX_SERDES_DATA4;
+    input [31:0] RX_SERDES_DATA5;
+    input [31:0] RX_SERDES_DATA6;
+    input [31:0] RX_SERDES_DATA7;
+    input [31:0] RX_SERDES_DATA8;
+    input [31:0] RX_SERDES_DATA9;
+    input [9:0] RX_SERDES_RESET;
+    input TX_CLK;
+    input [127:0] TX_DATAIN0;
+    input [127:0] TX_DATAIN1;
+    input [127:0] TX_DATAIN2;
+    input [127:0] TX_DATAIN3;
+    input TX_ENAIN0;
+    input TX_ENAIN1;
+    input TX_ENAIN2;
+    input TX_ENAIN3;
+    input TX_EOPIN0;
+    input TX_EOPIN1;
+    input TX_EOPIN2;
+    input TX_EOPIN3;
+    input TX_ERRIN0;
+    input TX_ERRIN1;
+    input TX_ERRIN2;
+    input TX_ERRIN3;
+    input [3:0] TX_MTYIN0;
+    input [3:0] TX_MTYIN1;
+    input [3:0] TX_MTYIN2;
+    input [3:0] TX_MTYIN3;
+    input [1:0] TX_PTP_1588OP_IN;
+    input [15:0] TX_PTP_CHKSUM_OFFSET_IN;
+    input [63:0] TX_PTP_RXTSTAMP_IN;
+    input [15:0] TX_PTP_TAG_FIELD_IN;
+    input [15:0] TX_PTP_TSTAMP_OFFSET_IN;
+    input TX_PTP_UPD_CHKSUM_IN;
+    input TX_RESET;
+    input TX_SOPIN0;
+    input TX_SOPIN1;
+    input TX_SOPIN2;
+    input TX_SOPIN3;
+endmodule
+
+module CMACE4 (...);
+    parameter CTL_PTP_TRANSPCLK_MODE = "FALSE";
+    parameter CTL_RX_CHECK_ACK = "TRUE";
+    parameter CTL_RX_CHECK_PREAMBLE = "FALSE";
+    parameter CTL_RX_CHECK_SFD = "FALSE";
+    parameter CTL_RX_DELETE_FCS = "TRUE";
+    parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808;
+    parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808;
+    parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808;
+    parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808;
+    parameter CTL_RX_FORWARD_CONTROL = "FALSE";
+    parameter CTL_RX_IGNORE_FCS = "FALSE";
+    parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580;
+    parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40;
+    parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001;
+    parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF;
+    parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF;
+    parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000;
+    parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000;
+    parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001;
+    parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001;
+    parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000;
+    parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000;
+    parameter CTL_RX_PROCESS_LFI = "FALSE";
+    parameter [8:0] CTL_RX_RSFEC_AM_THRESHOLD = 9'h046;
+    parameter [1:0] CTL_RX_RSFEC_FILL_ADJUST = 2'h0;
+    parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF;
+    parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
+    parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
+    parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600;
+    parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
+    parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
+    parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
+    parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
+    parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
+    parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
+    parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800;
+    parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
+    parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
+    parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
+    parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
+    parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
+    parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
+    parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
+    parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
+    parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
+    parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
+    parameter CTL_TEST_MODE_PIN_CHAR = "FALSE";
+    parameter CTL_TX_CUSTOM_PREAMBLE_ENABLE = "FALSE";
+    parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001;
+    parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001;
+    parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808;
+    parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808;
+    parameter CTL_TX_FCS_INS_ENABLE = "TRUE";
+    parameter CTL_TX_IGNORE_FCS = "FALSE";
+    parameter [3:0] CTL_TX_IPG_VALUE = 4'hC;
+    parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001;
+    parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001;
+    parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE";
+    parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1;
+    parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000;
+    parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000;
+    parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF;
+    parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
+    parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
+    parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600;
+    parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
+    parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
+    parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
+    parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
+    parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
+    parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
+    parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800;
+    parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
+    parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
+    parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
+    parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
+    parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
+    parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
+    parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
+    parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
+    parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
+    parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
+    parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+    parameter TEST_MODE_PIN_CHAR = "FALSE";
+    output [15:0] DRP_DO;
+    output DRP_RDY;
+    output [329:0] RSFEC_BYPASS_RX_DOUT;
+    output RSFEC_BYPASS_RX_DOUT_CW_START;
+    output RSFEC_BYPASS_RX_DOUT_VALID;
+    output [329:0] RSFEC_BYPASS_TX_DOUT;
+    output RSFEC_BYPASS_TX_DOUT_CW_START;
+    output RSFEC_BYPASS_TX_DOUT_VALID;
+    output [127:0] RX_DATAOUT0;
+    output [127:0] RX_DATAOUT1;
+    output [127:0] RX_DATAOUT2;
+    output [127:0] RX_DATAOUT3;
+    output RX_ENAOUT0;
+    output RX_ENAOUT1;
+    output RX_ENAOUT2;
+    output RX_ENAOUT3;
+    output RX_EOPOUT0;
+    output RX_EOPOUT1;
+    output RX_EOPOUT2;
+    output RX_EOPOUT3;
+    output RX_ERROUT0;
+    output RX_ERROUT1;
+    output RX_ERROUT2;
+    output RX_ERROUT3;
+    output [6:0] RX_LANE_ALIGNER_FILL_0;
+    output [6:0] RX_LANE_ALIGNER_FILL_1;
+    output [6:0] RX_LANE_ALIGNER_FILL_10;
+    output [6:0] RX_LANE_ALIGNER_FILL_11;
+    output [6:0] RX_LANE_ALIGNER_FILL_12;
+    output [6:0] RX_LANE_ALIGNER_FILL_13;
+    output [6:0] RX_LANE_ALIGNER_FILL_14;
+    output [6:0] RX_LANE_ALIGNER_FILL_15;
+    output [6:0] RX_LANE_ALIGNER_FILL_16;
+    output [6:0] RX_LANE_ALIGNER_FILL_17;
+    output [6:0] RX_LANE_ALIGNER_FILL_18;
+    output [6:0] RX_LANE_ALIGNER_FILL_19;
+    output [6:0] RX_LANE_ALIGNER_FILL_2;
+    output [6:0] RX_LANE_ALIGNER_FILL_3;
+    output [6:0] RX_LANE_ALIGNER_FILL_4;
+    output [6:0] RX_LANE_ALIGNER_FILL_5;
+    output [6:0] RX_LANE_ALIGNER_FILL_6;
+    output [6:0] RX_LANE_ALIGNER_FILL_7;
+    output [6:0] RX_LANE_ALIGNER_FILL_8;
+    output [6:0] RX_LANE_ALIGNER_FILL_9;
+    output [3:0] RX_MTYOUT0;
+    output [3:0] RX_MTYOUT1;
+    output [3:0] RX_MTYOUT2;
+    output [3:0] RX_MTYOUT3;
+    output [7:0] RX_OTN_BIP8_0;
+    output [7:0] RX_OTN_BIP8_1;
+    output [7:0] RX_OTN_BIP8_2;
+    output [7:0] RX_OTN_BIP8_3;
+    output [7:0] RX_OTN_BIP8_4;
+    output [65:0] RX_OTN_DATA_0;
+    output [65:0] RX_OTN_DATA_1;
+    output [65:0] RX_OTN_DATA_2;
+    output [65:0] RX_OTN_DATA_3;
+    output [65:0] RX_OTN_DATA_4;
+    output RX_OTN_ENA;
+    output RX_OTN_LANE0;
+    output RX_OTN_VLMARKER;
+    output [55:0] RX_PREOUT;
+    output [4:0] RX_PTP_PCSLANE_OUT;
+    output [79:0] RX_PTP_TSTAMP_OUT;
+    output RX_SOPOUT0;
+    output RX_SOPOUT1;
+    output RX_SOPOUT2;
+    output RX_SOPOUT3;
+    output STAT_RX_ALIGNED;
+    output STAT_RX_ALIGNED_ERR;
+    output [2:0] STAT_RX_BAD_CODE;
+    output [2:0] STAT_RX_BAD_FCS;
+    output STAT_RX_BAD_PREAMBLE;
+    output STAT_RX_BAD_SFD;
+    output STAT_RX_BIP_ERR_0;
+    output STAT_RX_BIP_ERR_1;
+    output STAT_RX_BIP_ERR_10;
+    output STAT_RX_BIP_ERR_11;
+    output STAT_RX_BIP_ERR_12;
+    output STAT_RX_BIP_ERR_13;
+    output STAT_RX_BIP_ERR_14;
+    output STAT_RX_BIP_ERR_15;
+    output STAT_RX_BIP_ERR_16;
+    output STAT_RX_BIP_ERR_17;
+    output STAT_RX_BIP_ERR_18;
+    output STAT_RX_BIP_ERR_19;
+    output STAT_RX_BIP_ERR_2;
+    output STAT_RX_BIP_ERR_3;
+    output STAT_RX_BIP_ERR_4;
+    output STAT_RX_BIP_ERR_5;
+    output STAT_RX_BIP_ERR_6;
+    output STAT_RX_BIP_ERR_7;
+    output STAT_RX_BIP_ERR_8;
+    output STAT_RX_BIP_ERR_9;
+    output [19:0] STAT_RX_BLOCK_LOCK;
+    output STAT_RX_BROADCAST;
+    output [2:0] STAT_RX_FRAGMENT;
+    output [1:0] STAT_RX_FRAMING_ERR_0;
+    output [1:0] STAT_RX_FRAMING_ERR_1;
+    output [1:0] STAT_RX_FRAMING_ERR_10;
+    output [1:0] STAT_RX_FRAMING_ERR_11;
+    output [1:0] STAT_RX_FRAMING_ERR_12;
+    output [1:0] STAT_RX_FRAMING_ERR_13;
+    output [1:0] STAT_RX_FRAMING_ERR_14;
+    output [1:0] STAT_RX_FRAMING_ERR_15;
+    output [1:0] STAT_RX_FRAMING_ERR_16;
+    output [1:0] STAT_RX_FRAMING_ERR_17;
+    output [1:0] STAT_RX_FRAMING_ERR_18;
+    output [1:0] STAT_RX_FRAMING_ERR_19;
+    output [1:0] STAT_RX_FRAMING_ERR_2;
+    output [1:0] STAT_RX_FRAMING_ERR_3;
+    output [1:0] STAT_RX_FRAMING_ERR_4;
+    output [1:0] STAT_RX_FRAMING_ERR_5;
+    output [1:0] STAT_RX_FRAMING_ERR_6;
+    output [1:0] STAT_RX_FRAMING_ERR_7;
+    output [1:0] STAT_RX_FRAMING_ERR_8;
+    output [1:0] STAT_RX_FRAMING_ERR_9;
+    output STAT_RX_FRAMING_ERR_VALID_0;
+    output STAT_RX_FRAMING_ERR_VALID_1;
+    output STAT_RX_FRAMING_ERR_VALID_10;
+    output STAT_RX_FRAMING_ERR_VALID_11;
+    output STAT_RX_FRAMING_ERR_VALID_12;
+    output STAT_RX_FRAMING_ERR_VALID_13;
+    output STAT_RX_FRAMING_ERR_VALID_14;
+    output STAT_RX_FRAMING_ERR_VALID_15;
+    output STAT_RX_FRAMING_ERR_VALID_16;
+    output STAT_RX_FRAMING_ERR_VALID_17;
+    output STAT_RX_FRAMING_ERR_VALID_18;
+    output STAT_RX_FRAMING_ERR_VALID_19;
+    output STAT_RX_FRAMING_ERR_VALID_2;
+    output STAT_RX_FRAMING_ERR_VALID_3;
+    output STAT_RX_FRAMING_ERR_VALID_4;
+    output STAT_RX_FRAMING_ERR_VALID_5;
+    output STAT_RX_FRAMING_ERR_VALID_6;
+    output STAT_RX_FRAMING_ERR_VALID_7;
+    output STAT_RX_FRAMING_ERR_VALID_8;
+    output STAT_RX_FRAMING_ERR_VALID_9;
+    output STAT_RX_GOT_SIGNAL_OS;
+    output STAT_RX_HI_BER;
+    output STAT_RX_INRANGEERR;
+    output STAT_RX_INTERNAL_LOCAL_FAULT;
+    output STAT_RX_JABBER;
+    output [7:0] STAT_RX_LANE0_VLM_BIP7;
+    output STAT_RX_LANE0_VLM_BIP7_VALID;
+    output STAT_RX_LOCAL_FAULT;
+    output [19:0] STAT_RX_MF_ERR;
+    output [19:0] STAT_RX_MF_LEN_ERR;
+    output [19:0] STAT_RX_MF_REPEAT_ERR;
+    output STAT_RX_MISALIGNED;
+    output STAT_RX_MULTICAST;
+    output STAT_RX_OVERSIZE;
+    output STAT_RX_PACKET_1024_1518_BYTES;
+    output STAT_RX_PACKET_128_255_BYTES;
+    output STAT_RX_PACKET_1519_1522_BYTES;
+    output STAT_RX_PACKET_1523_1548_BYTES;
+    output STAT_RX_PACKET_1549_2047_BYTES;
+    output STAT_RX_PACKET_2048_4095_BYTES;
+    output STAT_RX_PACKET_256_511_BYTES;
+    output STAT_RX_PACKET_4096_8191_BYTES;
+    output STAT_RX_PACKET_512_1023_BYTES;
+    output STAT_RX_PACKET_64_BYTES;
+    output STAT_RX_PACKET_65_127_BYTES;
+    output STAT_RX_PACKET_8192_9215_BYTES;
+    output STAT_RX_PACKET_BAD_FCS;
+    output STAT_RX_PACKET_LARGE;
+    output [2:0] STAT_RX_PACKET_SMALL;
+    output STAT_RX_PAUSE;
+    output [15:0] STAT_RX_PAUSE_QUANTA0;
+    output [15:0] STAT_RX_PAUSE_QUANTA1;
+    output [15:0] STAT_RX_PAUSE_QUANTA2;
+    output [15:0] STAT_RX_PAUSE_QUANTA3;
+    output [15:0] STAT_RX_PAUSE_QUANTA4;
+    output [15:0] STAT_RX_PAUSE_QUANTA5;
+    output [15:0] STAT_RX_PAUSE_QUANTA6;
+    output [15:0] STAT_RX_PAUSE_QUANTA7;
+    output [15:0] STAT_RX_PAUSE_QUANTA8;
+    output [8:0] STAT_RX_PAUSE_REQ;
+    output [8:0] STAT_RX_PAUSE_VALID;
+    output STAT_RX_RECEIVED_LOCAL_FAULT;
+    output STAT_RX_REMOTE_FAULT;
+    output STAT_RX_RSFEC_AM_LOCK0;
+    output STAT_RX_RSFEC_AM_LOCK1;
+    output STAT_RX_RSFEC_AM_LOCK2;
+    output STAT_RX_RSFEC_AM_LOCK3;
+    output STAT_RX_RSFEC_CORRECTED_CW_INC;
+    output STAT_RX_RSFEC_CW_INC;
+    output [2:0] STAT_RX_RSFEC_ERR_COUNT0_INC;
+    output [2:0] STAT_RX_RSFEC_ERR_COUNT1_INC;
+    output [2:0] STAT_RX_RSFEC_ERR_COUNT2_INC;
+    output [2:0] STAT_RX_RSFEC_ERR_COUNT3_INC;
+    output STAT_RX_RSFEC_HI_SER;
+    output STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS;
+    output [13:0] STAT_RX_RSFEC_LANE_FILL_0;
+    output [13:0] STAT_RX_RSFEC_LANE_FILL_1;
+    output [13:0] STAT_RX_RSFEC_LANE_FILL_2;
+    output [13:0] STAT_RX_RSFEC_LANE_FILL_3;
+    output [7:0] STAT_RX_RSFEC_LANE_MAPPING;
+    output [31:0] STAT_RX_RSFEC_RSVD;
+    output STAT_RX_RSFEC_UNCORRECTED_CW_INC;
+    output STAT_RX_STATUS;
+    output [2:0] STAT_RX_STOMPED_FCS;
+    output [19:0] STAT_RX_SYNCED;
+    output [19:0] STAT_RX_SYNCED_ERR;
+    output [2:0] STAT_RX_TEST_PATTERN_MISMATCH;
+    output STAT_RX_TOOLONG;
+    output [6:0] STAT_RX_TOTAL_BYTES;
+    output [13:0] STAT_RX_TOTAL_GOOD_BYTES;
+    output STAT_RX_TOTAL_GOOD_PACKETS;
+    output [2:0] STAT_RX_TOTAL_PACKETS;
+    output STAT_RX_TRUNCATED;
+    output [2:0] STAT_RX_UNDERSIZE;
+    output STAT_RX_UNICAST;
+    output STAT_RX_USER_PAUSE;
+    output STAT_RX_VLAN;
+    output [19:0] STAT_RX_VL_DEMUXED;
+    output [4:0] STAT_RX_VL_NUMBER_0;
+    output [4:0] STAT_RX_VL_NUMBER_1;
+    output [4:0] STAT_RX_VL_NUMBER_10;
+    output [4:0] STAT_RX_VL_NUMBER_11;
+    output [4:0] STAT_RX_VL_NUMBER_12;
+    output [4:0] STAT_RX_VL_NUMBER_13;
+    output [4:0] STAT_RX_VL_NUMBER_14;
+    output [4:0] STAT_RX_VL_NUMBER_15;
+    output [4:0] STAT_RX_VL_NUMBER_16;
+    output [4:0] STAT_RX_VL_NUMBER_17;
+    output [4:0] STAT_RX_VL_NUMBER_18;
+    output [4:0] STAT_RX_VL_NUMBER_19;
+    output [4:0] STAT_RX_VL_NUMBER_2;
+    output [4:0] STAT_RX_VL_NUMBER_3;
+    output [4:0] STAT_RX_VL_NUMBER_4;
+    output [4:0] STAT_RX_VL_NUMBER_5;
+    output [4:0] STAT_RX_VL_NUMBER_6;
+    output [4:0] STAT_RX_VL_NUMBER_7;
+    output [4:0] STAT_RX_VL_NUMBER_8;
+    output [4:0] STAT_RX_VL_NUMBER_9;
+    output STAT_TX_BAD_FCS;
+    output STAT_TX_BROADCAST;
+    output STAT_TX_FRAME_ERROR;
+    output STAT_TX_LOCAL_FAULT;
+    output STAT_TX_MULTICAST;
+    output STAT_TX_PACKET_1024_1518_BYTES;
+    output STAT_TX_PACKET_128_255_BYTES;
+    output STAT_TX_PACKET_1519_1522_BYTES;
+    output STAT_TX_PACKET_1523_1548_BYTES;
+    output STAT_TX_PACKET_1549_2047_BYTES;
+    output STAT_TX_PACKET_2048_4095_BYTES;
+    output STAT_TX_PACKET_256_511_BYTES;
+    output STAT_TX_PACKET_4096_8191_BYTES;
+    output STAT_TX_PACKET_512_1023_BYTES;
+    output STAT_TX_PACKET_64_BYTES;
+    output STAT_TX_PACKET_65_127_BYTES;
+    output STAT_TX_PACKET_8192_9215_BYTES;
+    output STAT_TX_PACKET_LARGE;
+    output STAT_TX_PACKET_SMALL;
+    output STAT_TX_PAUSE;
+    output [8:0] STAT_TX_PAUSE_VALID;
+    output STAT_TX_PTP_FIFO_READ_ERROR;
+    output STAT_TX_PTP_FIFO_WRITE_ERROR;
+    output [5:0] STAT_TX_TOTAL_BYTES;
+    output [13:0] STAT_TX_TOTAL_GOOD_BYTES;
+    output STAT_TX_TOTAL_GOOD_PACKETS;
+    output STAT_TX_TOTAL_PACKETS;
+    output STAT_TX_UNICAST;
+    output STAT_TX_USER_PAUSE;
+    output STAT_TX_VLAN;
+    output TX_OVFOUT;
+    output [4:0] TX_PTP_PCSLANE_OUT;
+    output [79:0] TX_PTP_TSTAMP_OUT;
+    output [15:0] TX_PTP_TSTAMP_TAG_OUT;
+    output TX_PTP_TSTAMP_VALID_OUT;
+    output TX_RDYOUT;
+    output [15:0] TX_SERDES_ALT_DATA0;
+    output [15:0] TX_SERDES_ALT_DATA1;
+    output [15:0] TX_SERDES_ALT_DATA2;
+    output [15:0] TX_SERDES_ALT_DATA3;
+    output [63:0] TX_SERDES_DATA0;
+    output [63:0] TX_SERDES_DATA1;
+    output [63:0] TX_SERDES_DATA2;
+    output [63:0] TX_SERDES_DATA3;
+    output [31:0] TX_SERDES_DATA4;
+    output [31:0] TX_SERDES_DATA5;
+    output [31:0] TX_SERDES_DATA6;
+    output [31:0] TX_SERDES_DATA7;
+    output [31:0] TX_SERDES_DATA8;
+    output [31:0] TX_SERDES_DATA9;
+    output TX_UNFOUT;
+    input CTL_CAUI4_MODE;
+    input CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE;
+    input CTL_RSFEC_IEEE_ERROR_INDICATION_MODE;
+    input CTL_RX_CHECK_ETYPE_GCP;
+    input CTL_RX_CHECK_ETYPE_GPP;
+    input CTL_RX_CHECK_ETYPE_PCP;
+    input CTL_RX_CHECK_ETYPE_PPP;
+    input CTL_RX_CHECK_MCAST_GCP;
+    input CTL_RX_CHECK_MCAST_GPP;
+    input CTL_RX_CHECK_MCAST_PCP;
+    input CTL_RX_CHECK_MCAST_PPP;
+    input CTL_RX_CHECK_OPCODE_GCP;
+    input CTL_RX_CHECK_OPCODE_GPP;
+    input CTL_RX_CHECK_OPCODE_PCP;
+    input CTL_RX_CHECK_OPCODE_PPP;
+    input CTL_RX_CHECK_SA_GCP;
+    input CTL_RX_CHECK_SA_GPP;
+    input CTL_RX_CHECK_SA_PCP;
+    input CTL_RX_CHECK_SA_PPP;
+    input CTL_RX_CHECK_UCAST_GCP;
+    input CTL_RX_CHECK_UCAST_GPP;
+    input CTL_RX_CHECK_UCAST_PCP;
+    input CTL_RX_CHECK_UCAST_PPP;
+    input CTL_RX_ENABLE;
+    input CTL_RX_ENABLE_GCP;
+    input CTL_RX_ENABLE_GPP;
+    input CTL_RX_ENABLE_PCP;
+    input CTL_RX_ENABLE_PPP;
+    input CTL_RX_FORCE_RESYNC;
+    input [8:0] CTL_RX_PAUSE_ACK;
+    input [8:0] CTL_RX_PAUSE_ENABLE;
+    input CTL_RX_RSFEC_ENABLE;
+    input CTL_RX_RSFEC_ENABLE_CORRECTION;
+    input CTL_RX_RSFEC_ENABLE_INDICATION;
+    input [79:0] CTL_RX_SYSTEMTIMERIN;
+    input CTL_RX_TEST_PATTERN;
+    input CTL_TX_ENABLE;
+    input CTL_TX_LANE0_VLM_BIP7_OVERRIDE;
+    input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE;
+    input [8:0] CTL_TX_PAUSE_ENABLE;
+    input [15:0] CTL_TX_PAUSE_QUANTA0;
+    input [15:0] CTL_TX_PAUSE_QUANTA1;
+    input [15:0] CTL_TX_PAUSE_QUANTA2;
+    input [15:0] CTL_TX_PAUSE_QUANTA3;
+    input [15:0] CTL_TX_PAUSE_QUANTA4;
+    input [15:0] CTL_TX_PAUSE_QUANTA5;
+    input [15:0] CTL_TX_PAUSE_QUANTA6;
+    input [15:0] CTL_TX_PAUSE_QUANTA7;
+    input [15:0] CTL_TX_PAUSE_QUANTA8;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7;
+    input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8;
+    input [8:0] CTL_TX_PAUSE_REQ;
+    input CTL_TX_PTP_VLANE_ADJUST_MODE;
+    input CTL_TX_RESEND_PAUSE;
+    input CTL_TX_RSFEC_ENABLE;
+    input CTL_TX_SEND_IDLE;
+    input CTL_TX_SEND_LFI;
+    input CTL_TX_SEND_RFI;
+    input [79:0] CTL_TX_SYSTEMTIMERIN;
+    input CTL_TX_TEST_PATTERN;
+    input [9:0] DRP_ADDR;
+    input DRP_CLK;
+    input [15:0] DRP_DI;
+    input DRP_EN;
+    input DRP_WE;
+    input [329:0] RSFEC_BYPASS_RX_DIN;
+    input RSFEC_BYPASS_RX_DIN_CW_START;
+    input [329:0] RSFEC_BYPASS_TX_DIN;
+    input RSFEC_BYPASS_TX_DIN_CW_START;
+    input RX_CLK;
+    input RX_RESET;
+    input [15:0] RX_SERDES_ALT_DATA0;
+    input [15:0] RX_SERDES_ALT_DATA1;
+    input [15:0] RX_SERDES_ALT_DATA2;
+    input [15:0] RX_SERDES_ALT_DATA3;
+    input [9:0] RX_SERDES_CLK;
+    input [63:0] RX_SERDES_DATA0;
+    input [63:0] RX_SERDES_DATA1;
+    input [63:0] RX_SERDES_DATA2;
+    input [63:0] RX_SERDES_DATA3;
+    input [31:0] RX_SERDES_DATA4;
+    input [31:0] RX_SERDES_DATA5;
+    input [31:0] RX_SERDES_DATA6;
+    input [31:0] RX_SERDES_DATA7;
+    input [31:0] RX_SERDES_DATA8;
+    input [31:0] RX_SERDES_DATA9;
+    input [9:0] RX_SERDES_RESET;
+    input TX_CLK;
+    input [127:0] TX_DATAIN0;
+    input [127:0] TX_DATAIN1;
+    input [127:0] TX_DATAIN2;
+    input [127:0] TX_DATAIN3;
+    input TX_ENAIN0;
+    input TX_ENAIN1;
+    input TX_ENAIN2;
+    input TX_ENAIN3;
+    input TX_EOPIN0;
+    input TX_EOPIN1;
+    input TX_EOPIN2;
+    input TX_EOPIN3;
+    input TX_ERRIN0;
+    input TX_ERRIN1;
+    input TX_ERRIN2;
+    input TX_ERRIN3;
+    input [3:0] TX_MTYIN0;
+    input [3:0] TX_MTYIN1;
+    input [3:0] TX_MTYIN2;
+    input [3:0] TX_MTYIN3;
+    input [55:0] TX_PREIN;
+    input [1:0] TX_PTP_1588OP_IN;
+    input [15:0] TX_PTP_CHKSUM_OFFSET_IN;
+    input [63:0] TX_PTP_RXTSTAMP_IN;
+    input [15:0] TX_PTP_TAG_FIELD_IN;
+    input [15:0] TX_PTP_TSTAMP_OFFSET_IN;
+    input TX_PTP_UPD_CHKSUM_IN;
+    input TX_RESET;
+    input TX_SOPIN0;
+    input TX_SOPIN1;
+    input TX_SOPIN2;
+    input TX_SOPIN3;
 endmodule
 
 module MCB (...);
@@ -25955,6 +27616,3401 @@ module MCB (...);
     input [5:0] P5CMDBL;
 endmodule
 
+(* keep *)
+module HBM_REF_CLK (...);
+    input REF_CLK;
+endmodule
+
+(* keep *)
+module HBM_SNGLBLI_INTF_APB (...);
+    parameter CLK_SEL = "FALSE";
+    parameter [0:0] IS_PCLK_INVERTED = 1'b0;
+    parameter [0:0] IS_PRESET_N_INVERTED = 1'b0;
+    parameter MC_ENABLE = "FALSE";
+    parameter PHY_ENABLE = "FALSE";
+    parameter PHY_PCLK_INVERT = "FALSE";
+    parameter SWITCH_ENABLE = "FALSE";
+    output CATTRIP_PIPE;
+    output [31:0] PRDATA_PIPE;
+    output PREADY_PIPE;
+    output PSLVERR_PIPE;
+    output [2:0] TEMP_PIPE;
+    input [21:0] PADDR;
+    (* invertible_pin = "IS_PCLK_INVERTED" *)
+    input PCLK;
+    input PENABLE;
+    (* invertible_pin = "IS_PRESET_N_INVERTED" *)
+    input PRESET_N;
+    input PSEL;
+    input [31:0] PWDATA;
+    input PWRITE;
+endmodule
+
+(* keep *)
+module HBM_SNGLBLI_INTF_AXI (...);
+    parameter CLK_SEL = "FALSE";
+    parameter integer DATARATE = 1800;
+    parameter [0:0] IS_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_ARESET_N_INVERTED = 1'b0;
+    parameter MC_ENABLE = "FALSE";
+    parameter integer PAGEHIT_PERCENT = 75;
+    parameter PHY_ENABLE = "FALSE";
+    parameter integer READ_PERCENT = 50;
+    parameter SWITCH_ENABLE = "FALSE";
+    parameter integer WRITE_PERCENT = 50;
+    output ARREADY_PIPE;
+    output AWREADY_PIPE;
+    output [5:0] BID_PIPE;
+    output [1:0] BRESP_PIPE;
+    output BVALID_PIPE;
+    output [1:0] DFI_AW_AERR_N_PIPE;
+    output DFI_CLK_BUF;
+    output DFI_CTRLUPD_ACK_PIPE;
+    output [7:0] DFI_DBI_BYTE_DISABLE_PIPE;
+    output [20:0] DFI_DW_RDDATA_DBI_PIPE;
+    output [7:0] DFI_DW_RDDATA_DERR_PIPE;
+    output [1:0] DFI_DW_RDDATA_PAR_VALID_PIPE;
+    output [1:0] DFI_DW_RDDATA_VALID_PIPE;
+    output DFI_INIT_COMPLETE_PIPE;
+    output DFI_PHYUPD_REQ_PIPE;
+    output DFI_PHYUPD_TYPE_PIPE;
+    output DFI_PHY_LP_STATE_PIPE;
+    output DFI_RST_N_BUF;
+    output [5:0] MC_STATUS;
+    output [7:0] PHY_STATUS;
+    output [31:0] RDATA_PARITY_PIPE;
+    output [255:0] RDATA_PIPE;
+    output [5:0] RID_PIPE;
+    output RLAST_PIPE;
+    output [1:0] RRESP_PIPE;
+    output RVALID_PIPE;
+    output [5:0] STATUS;
+    output WREADY_PIPE;
+    (* invertible_pin = "IS_ACLK_INVERTED" *)
+    input ACLK;
+    input [36:0] ARADDR;
+    input [1:0] ARBURST;
+    (* invertible_pin = "IS_ARESET_N_INVERTED" *)
+    input ARESET_N;
+    input [5:0] ARID;
+    input [3:0] ARLEN;
+    input [2:0] ARSIZE;
+    input ARVALID;
+    input [36:0] AWADDR;
+    input [1:0] AWBURST;
+    input [5:0] AWID;
+    input [3:0] AWLEN;
+    input [2:0] AWSIZE;
+    input AWVALID;
+    input BREADY;
+    input BSCAN_CK;
+    input DFI_LP_PWR_X_REQ;
+    input MBIST_EN;
+    input RREADY;
+    input [255:0] WDATA;
+    input [31:0] WDATA_PARITY;
+    input WLAST;
+    input [31:0] WSTRB;
+    input WVALID;
+endmodule
+
+(* keep *)
+module HBM_ONE_STACK_INTF (...);
+    parameter CLK_SEL_00 = "FALSE";
+    parameter CLK_SEL_01 = "FALSE";
+    parameter CLK_SEL_02 = "FALSE";
+    parameter CLK_SEL_03 = "FALSE";
+    parameter CLK_SEL_04 = "FALSE";
+    parameter CLK_SEL_05 = "FALSE";
+    parameter CLK_SEL_06 = "FALSE";
+    parameter CLK_SEL_07 = "FALSE";
+    parameter CLK_SEL_08 = "FALSE";
+    parameter CLK_SEL_09 = "FALSE";
+    parameter CLK_SEL_10 = "FALSE";
+    parameter CLK_SEL_11 = "FALSE";
+    parameter CLK_SEL_12 = "FALSE";
+    parameter CLK_SEL_13 = "FALSE";
+    parameter CLK_SEL_14 = "FALSE";
+    parameter CLK_SEL_15 = "FALSE";
+    parameter integer DATARATE_00 = 1800;
+    parameter integer DATARATE_01 = 1800;
+    parameter integer DATARATE_02 = 1800;
+    parameter integer DATARATE_03 = 1800;
+    parameter integer DATARATE_04 = 1800;
+    parameter integer DATARATE_05 = 1800;
+    parameter integer DATARATE_06 = 1800;
+    parameter integer DATARATE_07 = 1800;
+    parameter DA_LOCKOUT = "FALSE";
+    parameter [0:0] IS_APB_0_PCLK_INVERTED = 1'b0;
+    parameter [0:0] IS_APB_0_PRESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_00_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_00_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_01_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_01_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_02_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_02_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_03_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_03_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_04_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_04_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_05_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_05_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_06_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_06_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_07_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_07_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_08_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_08_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_09_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_09_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_10_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_10_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_11_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_11_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_12_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_12_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_13_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_13_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_14_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_14_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_15_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_15_ARESET_N_INVERTED = 1'b0;
+    parameter MC_ENABLE_0 = "FALSE";
+    parameter MC_ENABLE_1 = "FALSE";
+    parameter MC_ENABLE_2 = "FALSE";
+    parameter MC_ENABLE_3 = "FALSE";
+    parameter MC_ENABLE_4 = "FALSE";
+    parameter MC_ENABLE_5 = "FALSE";
+    parameter MC_ENABLE_6 = "FALSE";
+    parameter MC_ENABLE_7 = "FALSE";
+    parameter MC_ENABLE_APB = "FALSE";
+    parameter integer PAGEHIT_PERCENT_00 = 75;
+    parameter PHY_ENABLE_00 = "FALSE";
+    parameter PHY_ENABLE_01 = "FALSE";
+    parameter PHY_ENABLE_02 = "FALSE";
+    parameter PHY_ENABLE_03 = "FALSE";
+    parameter PHY_ENABLE_04 = "FALSE";
+    parameter PHY_ENABLE_05 = "FALSE";
+    parameter PHY_ENABLE_06 = "FALSE";
+    parameter PHY_ENABLE_07 = "FALSE";
+    parameter PHY_ENABLE_08 = "FALSE";
+    parameter PHY_ENABLE_09 = "FALSE";
+    parameter PHY_ENABLE_10 = "FALSE";
+    parameter PHY_ENABLE_11 = "FALSE";
+    parameter PHY_ENABLE_12 = "FALSE";
+    parameter PHY_ENABLE_13 = "FALSE";
+    parameter PHY_ENABLE_14 = "FALSE";
+    parameter PHY_ENABLE_15 = "FALSE";
+    parameter PHY_ENABLE_APB = "FALSE";
+    parameter PHY_PCLK_INVERT_01 = "FALSE";
+    parameter integer READ_PERCENT_00 = 50;
+    parameter integer READ_PERCENT_01 = 50;
+    parameter integer READ_PERCENT_02 = 50;
+    parameter integer READ_PERCENT_03 = 50;
+    parameter integer READ_PERCENT_04 = 50;
+    parameter integer READ_PERCENT_05 = 50;
+    parameter integer READ_PERCENT_06 = 50;
+    parameter integer READ_PERCENT_07 = 50;
+    parameter integer READ_PERCENT_08 = 50;
+    parameter integer READ_PERCENT_09 = 50;
+    parameter integer READ_PERCENT_10 = 50;
+    parameter integer READ_PERCENT_11 = 50;
+    parameter integer READ_PERCENT_12 = 50;
+    parameter integer READ_PERCENT_13 = 50;
+    parameter integer READ_PERCENT_14 = 50;
+    parameter integer READ_PERCENT_15 = 50;
+    parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+    parameter integer STACK_LOCATION = 0;
+    parameter SWITCH_ENABLE = "FALSE";
+    parameter integer WRITE_PERCENT_00 = 50;
+    parameter integer WRITE_PERCENT_01 = 50;
+    parameter integer WRITE_PERCENT_02 = 50;
+    parameter integer WRITE_PERCENT_03 = 50;
+    parameter integer WRITE_PERCENT_04 = 50;
+    parameter integer WRITE_PERCENT_05 = 50;
+    parameter integer WRITE_PERCENT_06 = 50;
+    parameter integer WRITE_PERCENT_07 = 50;
+    parameter integer WRITE_PERCENT_08 = 50;
+    parameter integer WRITE_PERCENT_09 = 50;
+    parameter integer WRITE_PERCENT_10 = 50;
+    parameter integer WRITE_PERCENT_11 = 50;
+    parameter integer WRITE_PERCENT_12 = 50;
+    parameter integer WRITE_PERCENT_13 = 50;
+    parameter integer WRITE_PERCENT_14 = 50;
+    parameter integer WRITE_PERCENT_15 = 50;
+    output [31:0] APB_0_PRDATA;
+    output APB_0_PREADY;
+    output APB_0_PSLVERR;
+    output AXI_00_ARREADY;
+    output AXI_00_AWREADY;
+    output [5:0] AXI_00_BID;
+    output [1:0] AXI_00_BRESP;
+    output AXI_00_BVALID;
+    output [1:0] AXI_00_DFI_AW_AERR_N;
+    output AXI_00_DFI_CLK_BUF;
+    output [7:0] AXI_00_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_00_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_00_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_00_DFI_DW_RDDATA_VALID;
+    output AXI_00_DFI_INIT_COMPLETE;
+    output AXI_00_DFI_PHYUPD_REQ;
+    output AXI_00_DFI_PHY_LP_STATE;
+    output AXI_00_DFI_RST_N_BUF;
+    output [5:0] AXI_00_MC_STATUS;
+    output [7:0] AXI_00_PHY_STATUS;
+    output [255:0] AXI_00_RDATA;
+    output [31:0] AXI_00_RDATA_PARITY;
+    output [5:0] AXI_00_RID;
+    output AXI_00_RLAST;
+    output [1:0] AXI_00_RRESP;
+    output AXI_00_RVALID;
+    output AXI_00_WREADY;
+    output AXI_01_ARREADY;
+    output AXI_01_AWREADY;
+    output [5:0] AXI_01_BID;
+    output [1:0] AXI_01_BRESP;
+    output AXI_01_BVALID;
+    output [1:0] AXI_01_DFI_AW_AERR_N;
+    output AXI_01_DFI_CLK_BUF;
+    output [7:0] AXI_01_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_01_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_01_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_01_DFI_DW_RDDATA_VALID;
+    output AXI_01_DFI_INIT_COMPLETE;
+    output AXI_01_DFI_PHYUPD_REQ;
+    output AXI_01_DFI_PHY_LP_STATE;
+    output AXI_01_DFI_RST_N_BUF;
+    output [255:0] AXI_01_RDATA;
+    output [31:0] AXI_01_RDATA_PARITY;
+    output [5:0] AXI_01_RID;
+    output AXI_01_RLAST;
+    output [1:0] AXI_01_RRESP;
+    output AXI_01_RVALID;
+    output AXI_01_WREADY;
+    output AXI_02_ARREADY;
+    output AXI_02_AWREADY;
+    output [5:0] AXI_02_BID;
+    output [1:0] AXI_02_BRESP;
+    output AXI_02_BVALID;
+    output [1:0] AXI_02_DFI_AW_AERR_N;
+    output AXI_02_DFI_CLK_BUF;
+    output [7:0] AXI_02_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_02_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_02_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_02_DFI_DW_RDDATA_VALID;
+    output AXI_02_DFI_INIT_COMPLETE;
+    output AXI_02_DFI_PHYUPD_REQ;
+    output AXI_02_DFI_PHY_LP_STATE;
+    output AXI_02_DFI_RST_N_BUF;
+    output [5:0] AXI_02_MC_STATUS;
+    output [7:0] AXI_02_PHY_STATUS;
+    output [255:0] AXI_02_RDATA;
+    output [31:0] AXI_02_RDATA_PARITY;
+    output [5:0] AXI_02_RID;
+    output AXI_02_RLAST;
+    output [1:0] AXI_02_RRESP;
+    output AXI_02_RVALID;
+    output AXI_02_WREADY;
+    output AXI_03_ARREADY;
+    output AXI_03_AWREADY;
+    output [5:0] AXI_03_BID;
+    output [1:0] AXI_03_BRESP;
+    output AXI_03_BVALID;
+    output [1:0] AXI_03_DFI_AW_AERR_N;
+    output AXI_03_DFI_CLK_BUF;
+    output [7:0] AXI_03_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_03_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_03_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_03_DFI_DW_RDDATA_VALID;
+    output AXI_03_DFI_INIT_COMPLETE;
+    output AXI_03_DFI_PHYUPD_REQ;
+    output AXI_03_DFI_PHY_LP_STATE;
+    output AXI_03_DFI_RST_N_BUF;
+    output [255:0] AXI_03_RDATA;
+    output [31:0] AXI_03_RDATA_PARITY;
+    output [5:0] AXI_03_RID;
+    output AXI_03_RLAST;
+    output [1:0] AXI_03_RRESP;
+    output AXI_03_RVALID;
+    output AXI_03_WREADY;
+    output AXI_04_ARREADY;
+    output AXI_04_AWREADY;
+    output [5:0] AXI_04_BID;
+    output [1:0] AXI_04_BRESP;
+    output AXI_04_BVALID;
+    output [1:0] AXI_04_DFI_AW_AERR_N;
+    output AXI_04_DFI_CLK_BUF;
+    output [7:0] AXI_04_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_04_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_04_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_04_DFI_DW_RDDATA_VALID;
+    output AXI_04_DFI_INIT_COMPLETE;
+    output AXI_04_DFI_PHYUPD_REQ;
+    output AXI_04_DFI_PHY_LP_STATE;
+    output AXI_04_DFI_RST_N_BUF;
+    output [5:0] AXI_04_MC_STATUS;
+    output [7:0] AXI_04_PHY_STATUS;
+    output [255:0] AXI_04_RDATA;
+    output [31:0] AXI_04_RDATA_PARITY;
+    output [5:0] AXI_04_RID;
+    output AXI_04_RLAST;
+    output [1:0] AXI_04_RRESP;
+    output AXI_04_RVALID;
+    output AXI_04_WREADY;
+    output AXI_05_ARREADY;
+    output AXI_05_AWREADY;
+    output [5:0] AXI_05_BID;
+    output [1:0] AXI_05_BRESP;
+    output AXI_05_BVALID;
+    output [1:0] AXI_05_DFI_AW_AERR_N;
+    output AXI_05_DFI_CLK_BUF;
+    output [7:0] AXI_05_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_05_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_05_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_05_DFI_DW_RDDATA_VALID;
+    output AXI_05_DFI_INIT_COMPLETE;
+    output AXI_05_DFI_PHYUPD_REQ;
+    output AXI_05_DFI_PHY_LP_STATE;
+    output AXI_05_DFI_RST_N_BUF;
+    output [255:0] AXI_05_RDATA;
+    output [31:0] AXI_05_RDATA_PARITY;
+    output [5:0] AXI_05_RID;
+    output AXI_05_RLAST;
+    output [1:0] AXI_05_RRESP;
+    output AXI_05_RVALID;
+    output AXI_05_WREADY;
+    output AXI_06_ARREADY;
+    output AXI_06_AWREADY;
+    output [5:0] AXI_06_BID;
+    output [1:0] AXI_06_BRESP;
+    output AXI_06_BVALID;
+    output [1:0] AXI_06_DFI_AW_AERR_N;
+    output AXI_06_DFI_CLK_BUF;
+    output [7:0] AXI_06_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_06_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_06_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_06_DFI_DW_RDDATA_VALID;
+    output AXI_06_DFI_INIT_COMPLETE;
+    output AXI_06_DFI_PHYUPD_REQ;
+    output AXI_06_DFI_PHY_LP_STATE;
+    output AXI_06_DFI_RST_N_BUF;
+    output [5:0] AXI_06_MC_STATUS;
+    output [7:0] AXI_06_PHY_STATUS;
+    output [255:0] AXI_06_RDATA;
+    output [31:0] AXI_06_RDATA_PARITY;
+    output [5:0] AXI_06_RID;
+    output AXI_06_RLAST;
+    output [1:0] AXI_06_RRESP;
+    output AXI_06_RVALID;
+    output AXI_06_WREADY;
+    output AXI_07_ARREADY;
+    output AXI_07_AWREADY;
+    output [5:0] AXI_07_BID;
+    output [1:0] AXI_07_BRESP;
+    output AXI_07_BVALID;
+    output [1:0] AXI_07_DFI_AW_AERR_N;
+    output AXI_07_DFI_CLK_BUF;
+    output [7:0] AXI_07_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_07_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_07_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_07_DFI_DW_RDDATA_VALID;
+    output AXI_07_DFI_INIT_COMPLETE;
+    output AXI_07_DFI_PHYUPD_REQ;
+    output AXI_07_DFI_PHY_LP_STATE;
+    output AXI_07_DFI_RST_N_BUF;
+    output [255:0] AXI_07_RDATA;
+    output [31:0] AXI_07_RDATA_PARITY;
+    output [5:0] AXI_07_RID;
+    output AXI_07_RLAST;
+    output [1:0] AXI_07_RRESP;
+    output AXI_07_RVALID;
+    output AXI_07_WREADY;
+    output AXI_08_ARREADY;
+    output AXI_08_AWREADY;
+    output [5:0] AXI_08_BID;
+    output [1:0] AXI_08_BRESP;
+    output AXI_08_BVALID;
+    output [1:0] AXI_08_DFI_AW_AERR_N;
+    output AXI_08_DFI_CLK_BUF;
+    output [7:0] AXI_08_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_08_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_08_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_08_DFI_DW_RDDATA_VALID;
+    output AXI_08_DFI_INIT_COMPLETE;
+    output AXI_08_DFI_PHYUPD_REQ;
+    output AXI_08_DFI_PHY_LP_STATE;
+    output AXI_08_DFI_RST_N_BUF;
+    output [5:0] AXI_08_MC_STATUS;
+    output [7:0] AXI_08_PHY_STATUS;
+    output [255:0] AXI_08_RDATA;
+    output [31:0] AXI_08_RDATA_PARITY;
+    output [5:0] AXI_08_RID;
+    output AXI_08_RLAST;
+    output [1:0] AXI_08_RRESP;
+    output AXI_08_RVALID;
+    output AXI_08_WREADY;
+    output AXI_09_ARREADY;
+    output AXI_09_AWREADY;
+    output [5:0] AXI_09_BID;
+    output [1:0] AXI_09_BRESP;
+    output AXI_09_BVALID;
+    output [1:0] AXI_09_DFI_AW_AERR_N;
+    output AXI_09_DFI_CLK_BUF;
+    output [7:0] AXI_09_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_09_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_09_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_09_DFI_DW_RDDATA_VALID;
+    output AXI_09_DFI_INIT_COMPLETE;
+    output AXI_09_DFI_PHYUPD_REQ;
+    output AXI_09_DFI_PHY_LP_STATE;
+    output AXI_09_DFI_RST_N_BUF;
+    output [255:0] AXI_09_RDATA;
+    output [31:0] AXI_09_RDATA_PARITY;
+    output [5:0] AXI_09_RID;
+    output AXI_09_RLAST;
+    output [1:0] AXI_09_RRESP;
+    output AXI_09_RVALID;
+    output AXI_09_WREADY;
+    output AXI_10_ARREADY;
+    output AXI_10_AWREADY;
+    output [5:0] AXI_10_BID;
+    output [1:0] AXI_10_BRESP;
+    output AXI_10_BVALID;
+    output [1:0] AXI_10_DFI_AW_AERR_N;
+    output AXI_10_DFI_CLK_BUF;
+    output [7:0] AXI_10_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_10_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_10_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_10_DFI_DW_RDDATA_VALID;
+    output AXI_10_DFI_INIT_COMPLETE;
+    output AXI_10_DFI_PHYUPD_REQ;
+    output AXI_10_DFI_PHY_LP_STATE;
+    output AXI_10_DFI_RST_N_BUF;
+    output [5:0] AXI_10_MC_STATUS;
+    output [7:0] AXI_10_PHY_STATUS;
+    output [255:0] AXI_10_RDATA;
+    output [31:0] AXI_10_RDATA_PARITY;
+    output [5:0] AXI_10_RID;
+    output AXI_10_RLAST;
+    output [1:0] AXI_10_RRESP;
+    output AXI_10_RVALID;
+    output AXI_10_WREADY;
+    output AXI_11_ARREADY;
+    output AXI_11_AWREADY;
+    output [5:0] AXI_11_BID;
+    output [1:0] AXI_11_BRESP;
+    output AXI_11_BVALID;
+    output [1:0] AXI_11_DFI_AW_AERR_N;
+    output AXI_11_DFI_CLK_BUF;
+    output [7:0] AXI_11_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_11_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_11_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_11_DFI_DW_RDDATA_VALID;
+    output AXI_11_DFI_INIT_COMPLETE;
+    output AXI_11_DFI_PHYUPD_REQ;
+    output AXI_11_DFI_PHY_LP_STATE;
+    output AXI_11_DFI_RST_N_BUF;
+    output [255:0] AXI_11_RDATA;
+    output [31:0] AXI_11_RDATA_PARITY;
+    output [5:0] AXI_11_RID;
+    output AXI_11_RLAST;
+    output [1:0] AXI_11_RRESP;
+    output AXI_11_RVALID;
+    output AXI_11_WREADY;
+    output AXI_12_ARREADY;
+    output AXI_12_AWREADY;
+    output [5:0] AXI_12_BID;
+    output [1:0] AXI_12_BRESP;
+    output AXI_12_BVALID;
+    output [1:0] AXI_12_DFI_AW_AERR_N;
+    output AXI_12_DFI_CLK_BUF;
+    output [7:0] AXI_12_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_12_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_12_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_12_DFI_DW_RDDATA_VALID;
+    output AXI_12_DFI_INIT_COMPLETE;
+    output AXI_12_DFI_PHYUPD_REQ;
+    output AXI_12_DFI_PHY_LP_STATE;
+    output AXI_12_DFI_RST_N_BUF;
+    output [5:0] AXI_12_MC_STATUS;
+    output [7:0] AXI_12_PHY_STATUS;
+    output [255:0] AXI_12_RDATA;
+    output [31:0] AXI_12_RDATA_PARITY;
+    output [5:0] AXI_12_RID;
+    output AXI_12_RLAST;
+    output [1:0] AXI_12_RRESP;
+    output AXI_12_RVALID;
+    output AXI_12_WREADY;
+    output AXI_13_ARREADY;
+    output AXI_13_AWREADY;
+    output [5:0] AXI_13_BID;
+    output [1:0] AXI_13_BRESP;
+    output AXI_13_BVALID;
+    output [1:0] AXI_13_DFI_AW_AERR_N;
+    output AXI_13_DFI_CLK_BUF;
+    output [7:0] AXI_13_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_13_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_13_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_13_DFI_DW_RDDATA_VALID;
+    output AXI_13_DFI_INIT_COMPLETE;
+    output AXI_13_DFI_PHYUPD_REQ;
+    output AXI_13_DFI_PHY_LP_STATE;
+    output AXI_13_DFI_RST_N_BUF;
+    output [255:0] AXI_13_RDATA;
+    output [31:0] AXI_13_RDATA_PARITY;
+    output [5:0] AXI_13_RID;
+    output AXI_13_RLAST;
+    output [1:0] AXI_13_RRESP;
+    output AXI_13_RVALID;
+    output AXI_13_WREADY;
+    output AXI_14_ARREADY;
+    output AXI_14_AWREADY;
+    output [5:0] AXI_14_BID;
+    output [1:0] AXI_14_BRESP;
+    output AXI_14_BVALID;
+    output [1:0] AXI_14_DFI_AW_AERR_N;
+    output AXI_14_DFI_CLK_BUF;
+    output [7:0] AXI_14_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_14_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_14_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_14_DFI_DW_RDDATA_VALID;
+    output AXI_14_DFI_INIT_COMPLETE;
+    output AXI_14_DFI_PHYUPD_REQ;
+    output AXI_14_DFI_PHY_LP_STATE;
+    output AXI_14_DFI_RST_N_BUF;
+    output [5:0] AXI_14_MC_STATUS;
+    output [7:0] AXI_14_PHY_STATUS;
+    output [255:0] AXI_14_RDATA;
+    output [31:0] AXI_14_RDATA_PARITY;
+    output [5:0] AXI_14_RID;
+    output AXI_14_RLAST;
+    output [1:0] AXI_14_RRESP;
+    output AXI_14_RVALID;
+    output AXI_14_WREADY;
+    output AXI_15_ARREADY;
+    output AXI_15_AWREADY;
+    output [5:0] AXI_15_BID;
+    output [1:0] AXI_15_BRESP;
+    output AXI_15_BVALID;
+    output [1:0] AXI_15_DFI_AW_AERR_N;
+    output AXI_15_DFI_CLK_BUF;
+    output [7:0] AXI_15_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_15_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_15_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_15_DFI_DW_RDDATA_VALID;
+    output AXI_15_DFI_INIT_COMPLETE;
+    output AXI_15_DFI_PHYUPD_REQ;
+    output AXI_15_DFI_PHY_LP_STATE;
+    output AXI_15_DFI_RST_N_BUF;
+    output [255:0] AXI_15_RDATA;
+    output [31:0] AXI_15_RDATA_PARITY;
+    output [5:0] AXI_15_RID;
+    output AXI_15_RLAST;
+    output [1:0] AXI_15_RRESP;
+    output AXI_15_RVALID;
+    output AXI_15_WREADY;
+    output DRAM_0_STAT_CATTRIP;
+    output [2:0] DRAM_0_STAT_TEMP;
+    input [21:0] APB_0_PADDR;
+    (* invertible_pin = "IS_APB_0_PCLK_INVERTED" *)
+    input APB_0_PCLK;
+    input APB_0_PENABLE;
+    (* invertible_pin = "IS_APB_0_PRESET_N_INVERTED" *)
+    input APB_0_PRESET_N;
+    input APB_0_PSEL;
+    input [31:0] APB_0_PWDATA;
+    input APB_0_PWRITE;
+    (* invertible_pin = "IS_AXI_00_ACLK_INVERTED" *)
+    input AXI_00_ACLK;
+    input [36:0] AXI_00_ARADDR;
+    input [1:0] AXI_00_ARBURST;
+    (* invertible_pin = "IS_AXI_00_ARESET_N_INVERTED" *)
+    input AXI_00_ARESET_N;
+    input [5:0] AXI_00_ARID;
+    input [3:0] AXI_00_ARLEN;
+    input [2:0] AXI_00_ARSIZE;
+    input AXI_00_ARVALID;
+    input [36:0] AXI_00_AWADDR;
+    input [1:0] AXI_00_AWBURST;
+    input [5:0] AXI_00_AWID;
+    input [3:0] AXI_00_AWLEN;
+    input [2:0] AXI_00_AWSIZE;
+    input AXI_00_AWVALID;
+    input AXI_00_BREADY;
+    input AXI_00_DFI_LP_PWR_X_REQ;
+    input AXI_00_RREADY;
+    input [255:0] AXI_00_WDATA;
+    input [31:0] AXI_00_WDATA_PARITY;
+    input AXI_00_WLAST;
+    input [31:0] AXI_00_WSTRB;
+    input AXI_00_WVALID;
+    (* invertible_pin = "IS_AXI_01_ACLK_INVERTED" *)
+    input AXI_01_ACLK;
+    input [36:0] AXI_01_ARADDR;
+    input [1:0] AXI_01_ARBURST;
+    (* invertible_pin = "IS_AXI_01_ARESET_N_INVERTED" *)
+    input AXI_01_ARESET_N;
+    input [5:0] AXI_01_ARID;
+    input [3:0] AXI_01_ARLEN;
+    input [2:0] AXI_01_ARSIZE;
+    input AXI_01_ARVALID;
+    input [36:0] AXI_01_AWADDR;
+    input [1:0] AXI_01_AWBURST;
+    input [5:0] AXI_01_AWID;
+    input [3:0] AXI_01_AWLEN;
+    input [2:0] AXI_01_AWSIZE;
+    input AXI_01_AWVALID;
+    input AXI_01_BREADY;
+    input AXI_01_DFI_LP_PWR_X_REQ;
+    input AXI_01_RREADY;
+    input [255:0] AXI_01_WDATA;
+    input [31:0] AXI_01_WDATA_PARITY;
+    input AXI_01_WLAST;
+    input [31:0] AXI_01_WSTRB;
+    input AXI_01_WVALID;
+    (* invertible_pin = "IS_AXI_02_ACLK_INVERTED" *)
+    input AXI_02_ACLK;
+    input [36:0] AXI_02_ARADDR;
+    input [1:0] AXI_02_ARBURST;
+    (* invertible_pin = "IS_AXI_02_ARESET_N_INVERTED" *)
+    input AXI_02_ARESET_N;
+    input [5:0] AXI_02_ARID;
+    input [3:0] AXI_02_ARLEN;
+    input [2:0] AXI_02_ARSIZE;
+    input AXI_02_ARVALID;
+    input [36:0] AXI_02_AWADDR;
+    input [1:0] AXI_02_AWBURST;
+    input [5:0] AXI_02_AWID;
+    input [3:0] AXI_02_AWLEN;
+    input [2:0] AXI_02_AWSIZE;
+    input AXI_02_AWVALID;
+    input AXI_02_BREADY;
+    input AXI_02_DFI_LP_PWR_X_REQ;
+    input AXI_02_RREADY;
+    input [255:0] AXI_02_WDATA;
+    input [31:0] AXI_02_WDATA_PARITY;
+    input AXI_02_WLAST;
+    input [31:0] AXI_02_WSTRB;
+    input AXI_02_WVALID;
+    (* invertible_pin = "IS_AXI_03_ACLK_INVERTED" *)
+    input AXI_03_ACLK;
+    input [36:0] AXI_03_ARADDR;
+    input [1:0] AXI_03_ARBURST;
+    (* invertible_pin = "IS_AXI_03_ARESET_N_INVERTED" *)
+    input AXI_03_ARESET_N;
+    input [5:0] AXI_03_ARID;
+    input [3:0] AXI_03_ARLEN;
+    input [2:0] AXI_03_ARSIZE;
+    input AXI_03_ARVALID;
+    input [36:0] AXI_03_AWADDR;
+    input [1:0] AXI_03_AWBURST;
+    input [5:0] AXI_03_AWID;
+    input [3:0] AXI_03_AWLEN;
+    input [2:0] AXI_03_AWSIZE;
+    input AXI_03_AWVALID;
+    input AXI_03_BREADY;
+    input AXI_03_DFI_LP_PWR_X_REQ;
+    input AXI_03_RREADY;
+    input [255:0] AXI_03_WDATA;
+    input [31:0] AXI_03_WDATA_PARITY;
+    input AXI_03_WLAST;
+    input [31:0] AXI_03_WSTRB;
+    input AXI_03_WVALID;
+    (* invertible_pin = "IS_AXI_04_ACLK_INVERTED" *)
+    input AXI_04_ACLK;
+    input [36:0] AXI_04_ARADDR;
+    input [1:0] AXI_04_ARBURST;
+    (* invertible_pin = "IS_AXI_04_ARESET_N_INVERTED" *)
+    input AXI_04_ARESET_N;
+    input [5:0] AXI_04_ARID;
+    input [3:0] AXI_04_ARLEN;
+    input [2:0] AXI_04_ARSIZE;
+    input AXI_04_ARVALID;
+    input [36:0] AXI_04_AWADDR;
+    input [1:0] AXI_04_AWBURST;
+    input [5:0] AXI_04_AWID;
+    input [3:0] AXI_04_AWLEN;
+    input [2:0] AXI_04_AWSIZE;
+    input AXI_04_AWVALID;
+    input AXI_04_BREADY;
+    input AXI_04_DFI_LP_PWR_X_REQ;
+    input AXI_04_RREADY;
+    input [255:0] AXI_04_WDATA;
+    input [31:0] AXI_04_WDATA_PARITY;
+    input AXI_04_WLAST;
+    input [31:0] AXI_04_WSTRB;
+    input AXI_04_WVALID;
+    (* invertible_pin = "IS_AXI_05_ACLK_INVERTED" *)
+    input AXI_05_ACLK;
+    input [36:0] AXI_05_ARADDR;
+    input [1:0] AXI_05_ARBURST;
+    (* invertible_pin = "IS_AXI_05_ARESET_N_INVERTED" *)
+    input AXI_05_ARESET_N;
+    input [5:0] AXI_05_ARID;
+    input [3:0] AXI_05_ARLEN;
+    input [2:0] AXI_05_ARSIZE;
+    input AXI_05_ARVALID;
+    input [36:0] AXI_05_AWADDR;
+    input [1:0] AXI_05_AWBURST;
+    input [5:0] AXI_05_AWID;
+    input [3:0] AXI_05_AWLEN;
+    input [2:0] AXI_05_AWSIZE;
+    input AXI_05_AWVALID;
+    input AXI_05_BREADY;
+    input AXI_05_DFI_LP_PWR_X_REQ;
+    input AXI_05_RREADY;
+    input [255:0] AXI_05_WDATA;
+    input [31:0] AXI_05_WDATA_PARITY;
+    input AXI_05_WLAST;
+    input [31:0] AXI_05_WSTRB;
+    input AXI_05_WVALID;
+    (* invertible_pin = "IS_AXI_06_ACLK_INVERTED" *)
+    input AXI_06_ACLK;
+    input [36:0] AXI_06_ARADDR;
+    input [1:0] AXI_06_ARBURST;
+    (* invertible_pin = "IS_AXI_06_ARESET_N_INVERTED" *)
+    input AXI_06_ARESET_N;
+    input [5:0] AXI_06_ARID;
+    input [3:0] AXI_06_ARLEN;
+    input [2:0] AXI_06_ARSIZE;
+    input AXI_06_ARVALID;
+    input [36:0] AXI_06_AWADDR;
+    input [1:0] AXI_06_AWBURST;
+    input [5:0] AXI_06_AWID;
+    input [3:0] AXI_06_AWLEN;
+    input [2:0] AXI_06_AWSIZE;
+    input AXI_06_AWVALID;
+    input AXI_06_BREADY;
+    input AXI_06_DFI_LP_PWR_X_REQ;
+    input AXI_06_RREADY;
+    input [255:0] AXI_06_WDATA;
+    input [31:0] AXI_06_WDATA_PARITY;
+    input AXI_06_WLAST;
+    input [31:0] AXI_06_WSTRB;
+    input AXI_06_WVALID;
+    (* invertible_pin = "IS_AXI_07_ACLK_INVERTED" *)
+    input AXI_07_ACLK;
+    input [36:0] AXI_07_ARADDR;
+    input [1:0] AXI_07_ARBURST;
+    (* invertible_pin = "IS_AXI_07_ARESET_N_INVERTED" *)
+    input AXI_07_ARESET_N;
+    input [5:0] AXI_07_ARID;
+    input [3:0] AXI_07_ARLEN;
+    input [2:0] AXI_07_ARSIZE;
+    input AXI_07_ARVALID;
+    input [36:0] AXI_07_AWADDR;
+    input [1:0] AXI_07_AWBURST;
+    input [5:0] AXI_07_AWID;
+    input [3:0] AXI_07_AWLEN;
+    input [2:0] AXI_07_AWSIZE;
+    input AXI_07_AWVALID;
+    input AXI_07_BREADY;
+    input AXI_07_DFI_LP_PWR_X_REQ;
+    input AXI_07_RREADY;
+    input [255:0] AXI_07_WDATA;
+    input [31:0] AXI_07_WDATA_PARITY;
+    input AXI_07_WLAST;
+    input [31:0] AXI_07_WSTRB;
+    input AXI_07_WVALID;
+    (* invertible_pin = "IS_AXI_08_ACLK_INVERTED" *)
+    input AXI_08_ACLK;
+    input [36:0] AXI_08_ARADDR;
+    input [1:0] AXI_08_ARBURST;
+    (* invertible_pin = "IS_AXI_08_ARESET_N_INVERTED" *)
+    input AXI_08_ARESET_N;
+    input [5:0] AXI_08_ARID;
+    input [3:0] AXI_08_ARLEN;
+    input [2:0] AXI_08_ARSIZE;
+    input AXI_08_ARVALID;
+    input [36:0] AXI_08_AWADDR;
+    input [1:0] AXI_08_AWBURST;
+    input [5:0] AXI_08_AWID;
+    input [3:0] AXI_08_AWLEN;
+    input [2:0] AXI_08_AWSIZE;
+    input AXI_08_AWVALID;
+    input AXI_08_BREADY;
+    input AXI_08_DFI_LP_PWR_X_REQ;
+    input AXI_08_RREADY;
+    input [255:0] AXI_08_WDATA;
+    input [31:0] AXI_08_WDATA_PARITY;
+    input AXI_08_WLAST;
+    input [31:0] AXI_08_WSTRB;
+    input AXI_08_WVALID;
+    (* invertible_pin = "IS_AXI_09_ACLK_INVERTED" *)
+    input AXI_09_ACLK;
+    input [36:0] AXI_09_ARADDR;
+    input [1:0] AXI_09_ARBURST;
+    (* invertible_pin = "IS_AXI_09_ARESET_N_INVERTED" *)
+    input AXI_09_ARESET_N;
+    input [5:0] AXI_09_ARID;
+    input [3:0] AXI_09_ARLEN;
+    input [2:0] AXI_09_ARSIZE;
+    input AXI_09_ARVALID;
+    input [36:0] AXI_09_AWADDR;
+    input [1:0] AXI_09_AWBURST;
+    input [5:0] AXI_09_AWID;
+    input [3:0] AXI_09_AWLEN;
+    input [2:0] AXI_09_AWSIZE;
+    input AXI_09_AWVALID;
+    input AXI_09_BREADY;
+    input AXI_09_DFI_LP_PWR_X_REQ;
+    input AXI_09_RREADY;
+    input [255:0] AXI_09_WDATA;
+    input [31:0] AXI_09_WDATA_PARITY;
+    input AXI_09_WLAST;
+    input [31:0] AXI_09_WSTRB;
+    input AXI_09_WVALID;
+    (* invertible_pin = "IS_AXI_10_ACLK_INVERTED" *)
+    input AXI_10_ACLK;
+    input [36:0] AXI_10_ARADDR;
+    input [1:0] AXI_10_ARBURST;
+    (* invertible_pin = "IS_AXI_10_ARESET_N_INVERTED" *)
+    input AXI_10_ARESET_N;
+    input [5:0] AXI_10_ARID;
+    input [3:0] AXI_10_ARLEN;
+    input [2:0] AXI_10_ARSIZE;
+    input AXI_10_ARVALID;
+    input [36:0] AXI_10_AWADDR;
+    input [1:0] AXI_10_AWBURST;
+    input [5:0] AXI_10_AWID;
+    input [3:0] AXI_10_AWLEN;
+    input [2:0] AXI_10_AWSIZE;
+    input AXI_10_AWVALID;
+    input AXI_10_BREADY;
+    input AXI_10_DFI_LP_PWR_X_REQ;
+    input AXI_10_RREADY;
+    input [255:0] AXI_10_WDATA;
+    input [31:0] AXI_10_WDATA_PARITY;
+    input AXI_10_WLAST;
+    input [31:0] AXI_10_WSTRB;
+    input AXI_10_WVALID;
+    (* invertible_pin = "IS_AXI_11_ACLK_INVERTED" *)
+    input AXI_11_ACLK;
+    input [36:0] AXI_11_ARADDR;
+    input [1:0] AXI_11_ARBURST;
+    (* invertible_pin = "IS_AXI_11_ARESET_N_INVERTED" *)
+    input AXI_11_ARESET_N;
+    input [5:0] AXI_11_ARID;
+    input [3:0] AXI_11_ARLEN;
+    input [2:0] AXI_11_ARSIZE;
+    input AXI_11_ARVALID;
+    input [36:0] AXI_11_AWADDR;
+    input [1:0] AXI_11_AWBURST;
+    input [5:0] AXI_11_AWID;
+    input [3:0] AXI_11_AWLEN;
+    input [2:0] AXI_11_AWSIZE;
+    input AXI_11_AWVALID;
+    input AXI_11_BREADY;
+    input AXI_11_DFI_LP_PWR_X_REQ;
+    input AXI_11_RREADY;
+    input [255:0] AXI_11_WDATA;
+    input [31:0] AXI_11_WDATA_PARITY;
+    input AXI_11_WLAST;
+    input [31:0] AXI_11_WSTRB;
+    input AXI_11_WVALID;
+    (* invertible_pin = "IS_AXI_12_ACLK_INVERTED" *)
+    input AXI_12_ACLK;
+    input [36:0] AXI_12_ARADDR;
+    input [1:0] AXI_12_ARBURST;
+    (* invertible_pin = "IS_AXI_12_ARESET_N_INVERTED" *)
+    input AXI_12_ARESET_N;
+    input [5:0] AXI_12_ARID;
+    input [3:0] AXI_12_ARLEN;
+    input [2:0] AXI_12_ARSIZE;
+    input AXI_12_ARVALID;
+    input [36:0] AXI_12_AWADDR;
+    input [1:0] AXI_12_AWBURST;
+    input [5:0] AXI_12_AWID;
+    input [3:0] AXI_12_AWLEN;
+    input [2:0] AXI_12_AWSIZE;
+    input AXI_12_AWVALID;
+    input AXI_12_BREADY;
+    input AXI_12_DFI_LP_PWR_X_REQ;
+    input AXI_12_RREADY;
+    input [255:0] AXI_12_WDATA;
+    input [31:0] AXI_12_WDATA_PARITY;
+    input AXI_12_WLAST;
+    input [31:0] AXI_12_WSTRB;
+    input AXI_12_WVALID;
+    (* invertible_pin = "IS_AXI_13_ACLK_INVERTED" *)
+    input AXI_13_ACLK;
+    input [36:0] AXI_13_ARADDR;
+    input [1:0] AXI_13_ARBURST;
+    (* invertible_pin = "IS_AXI_13_ARESET_N_INVERTED" *)
+    input AXI_13_ARESET_N;
+    input [5:0] AXI_13_ARID;
+    input [3:0] AXI_13_ARLEN;
+    input [2:0] AXI_13_ARSIZE;
+    input AXI_13_ARVALID;
+    input [36:0] AXI_13_AWADDR;
+    input [1:0] AXI_13_AWBURST;
+    input [5:0] AXI_13_AWID;
+    input [3:0] AXI_13_AWLEN;
+    input [2:0] AXI_13_AWSIZE;
+    input AXI_13_AWVALID;
+    input AXI_13_BREADY;
+    input AXI_13_DFI_LP_PWR_X_REQ;
+    input AXI_13_RREADY;
+    input [255:0] AXI_13_WDATA;
+    input [31:0] AXI_13_WDATA_PARITY;
+    input AXI_13_WLAST;
+    input [31:0] AXI_13_WSTRB;
+    input AXI_13_WVALID;
+    (* invertible_pin = "IS_AXI_14_ACLK_INVERTED" *)
+    input AXI_14_ACLK;
+    input [36:0] AXI_14_ARADDR;
+    input [1:0] AXI_14_ARBURST;
+    (* invertible_pin = "IS_AXI_14_ARESET_N_INVERTED" *)
+    input AXI_14_ARESET_N;
+    input [5:0] AXI_14_ARID;
+    input [3:0] AXI_14_ARLEN;
+    input [2:0] AXI_14_ARSIZE;
+    input AXI_14_ARVALID;
+    input [36:0] AXI_14_AWADDR;
+    input [1:0] AXI_14_AWBURST;
+    input [5:0] AXI_14_AWID;
+    input [3:0] AXI_14_AWLEN;
+    input [2:0] AXI_14_AWSIZE;
+    input AXI_14_AWVALID;
+    input AXI_14_BREADY;
+    input AXI_14_DFI_LP_PWR_X_REQ;
+    input AXI_14_RREADY;
+    input [255:0] AXI_14_WDATA;
+    input [31:0] AXI_14_WDATA_PARITY;
+    input AXI_14_WLAST;
+    input [31:0] AXI_14_WSTRB;
+    input AXI_14_WVALID;
+    (* invertible_pin = "IS_AXI_15_ACLK_INVERTED" *)
+    input AXI_15_ACLK;
+    input [36:0] AXI_15_ARADDR;
+    input [1:0] AXI_15_ARBURST;
+    (* invertible_pin = "IS_AXI_15_ARESET_N_INVERTED" *)
+    input AXI_15_ARESET_N;
+    input [5:0] AXI_15_ARID;
+    input [3:0] AXI_15_ARLEN;
+    input [2:0] AXI_15_ARSIZE;
+    input AXI_15_ARVALID;
+    input [36:0] AXI_15_AWADDR;
+    input [1:0] AXI_15_AWBURST;
+    input [5:0] AXI_15_AWID;
+    input [3:0] AXI_15_AWLEN;
+    input [2:0] AXI_15_AWSIZE;
+    input AXI_15_AWVALID;
+    input AXI_15_BREADY;
+    input AXI_15_DFI_LP_PWR_X_REQ;
+    input AXI_15_RREADY;
+    input [255:0] AXI_15_WDATA;
+    input [31:0] AXI_15_WDATA_PARITY;
+    input AXI_15_WLAST;
+    input [31:0] AXI_15_WSTRB;
+    input AXI_15_WVALID;
+    input BSCAN_DRCK;
+    input BSCAN_TCK;
+    input HBM_REF_CLK;
+    input MBIST_EN_00;
+    input MBIST_EN_01;
+    input MBIST_EN_02;
+    input MBIST_EN_03;
+    input MBIST_EN_04;
+    input MBIST_EN_05;
+    input MBIST_EN_06;
+    input MBIST_EN_07;
+endmodule
+
+(* keep *)
+module HBM_TWO_STACK_INTF (...);
+    parameter CLK_SEL_00 = "FALSE";
+    parameter CLK_SEL_01 = "FALSE";
+    parameter CLK_SEL_02 = "FALSE";
+    parameter CLK_SEL_03 = "FALSE";
+    parameter CLK_SEL_04 = "FALSE";
+    parameter CLK_SEL_05 = "FALSE";
+    parameter CLK_SEL_06 = "FALSE";
+    parameter CLK_SEL_07 = "FALSE";
+    parameter CLK_SEL_08 = "FALSE";
+    parameter CLK_SEL_09 = "FALSE";
+    parameter CLK_SEL_10 = "FALSE";
+    parameter CLK_SEL_11 = "FALSE";
+    parameter CLK_SEL_12 = "FALSE";
+    parameter CLK_SEL_13 = "FALSE";
+    parameter CLK_SEL_14 = "FALSE";
+    parameter CLK_SEL_15 = "FALSE";
+    parameter CLK_SEL_16 = "FALSE";
+    parameter CLK_SEL_17 = "FALSE";
+    parameter CLK_SEL_18 = "FALSE";
+    parameter CLK_SEL_19 = "FALSE";
+    parameter CLK_SEL_20 = "FALSE";
+    parameter CLK_SEL_21 = "FALSE";
+    parameter CLK_SEL_22 = "FALSE";
+    parameter CLK_SEL_23 = "FALSE";
+    parameter CLK_SEL_24 = "FALSE";
+    parameter CLK_SEL_25 = "FALSE";
+    parameter CLK_SEL_26 = "FALSE";
+    parameter CLK_SEL_27 = "FALSE";
+    parameter CLK_SEL_28 = "FALSE";
+    parameter CLK_SEL_29 = "FALSE";
+    parameter CLK_SEL_30 = "FALSE";
+    parameter CLK_SEL_31 = "FALSE";
+    parameter integer DATARATE_00 = 1800;
+    parameter integer DATARATE_01 = 1800;
+    parameter integer DATARATE_02 = 1800;
+    parameter integer DATARATE_03 = 1800;
+    parameter integer DATARATE_04 = 1800;
+    parameter integer DATARATE_05 = 1800;
+    parameter integer DATARATE_06 = 1800;
+    parameter integer DATARATE_07 = 1800;
+    parameter integer DATARATE_08 = 1800;
+    parameter integer DATARATE_09 = 1800;
+    parameter integer DATARATE_10 = 1800;
+    parameter integer DATARATE_11 = 1800;
+    parameter integer DATARATE_12 = 1800;
+    parameter integer DATARATE_13 = 1800;
+    parameter integer DATARATE_14 = 1800;
+    parameter integer DATARATE_15 = 1800;
+    parameter DA_LOCKOUT_0 = "FALSE";
+    parameter DA_LOCKOUT_1 = "FALSE";
+    parameter [0:0] IS_APB_0_PCLK_INVERTED = 1'b0;
+    parameter [0:0] IS_APB_0_PRESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_APB_1_PCLK_INVERTED = 1'b0;
+    parameter [0:0] IS_APB_1_PRESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_00_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_00_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_01_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_01_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_02_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_02_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_03_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_03_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_04_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_04_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_05_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_05_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_06_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_06_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_07_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_07_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_08_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_08_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_09_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_09_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_10_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_10_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_11_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_11_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_12_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_12_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_13_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_13_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_14_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_14_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_15_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_15_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_16_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_16_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_17_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_17_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_18_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_18_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_19_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_19_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_20_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_20_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_21_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_21_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_22_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_22_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_23_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_23_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_24_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_24_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_25_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_25_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_26_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_26_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_27_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_27_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_28_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_28_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_29_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_29_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_30_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_30_ARESET_N_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_31_ACLK_INVERTED = 1'b0;
+    parameter [0:0] IS_AXI_31_ARESET_N_INVERTED = 1'b0;
+    parameter MC_ENABLE_00 = "FALSE";
+    parameter MC_ENABLE_01 = "FALSE";
+    parameter MC_ENABLE_02 = "FALSE";
+    parameter MC_ENABLE_03 = "FALSE";
+    parameter MC_ENABLE_04 = "FALSE";
+    parameter MC_ENABLE_05 = "FALSE";
+    parameter MC_ENABLE_06 = "FALSE";
+    parameter MC_ENABLE_07 = "FALSE";
+    parameter MC_ENABLE_08 = "FALSE";
+    parameter MC_ENABLE_09 = "FALSE";
+    parameter MC_ENABLE_10 = "FALSE";
+    parameter MC_ENABLE_11 = "FALSE";
+    parameter MC_ENABLE_12 = "FALSE";
+    parameter MC_ENABLE_13 = "FALSE";
+    parameter MC_ENABLE_14 = "FALSE";
+    parameter MC_ENABLE_15 = "FALSE";
+    parameter MC_ENABLE_APB_00 = "FALSE";
+    parameter MC_ENABLE_APB_01 = "FALSE";
+    parameter integer PAGEHIT_PERCENT_00 = 75;
+    parameter integer PAGEHIT_PERCENT_01 = 75;
+    parameter PHY_ENABLE_00 = "FALSE";
+    parameter PHY_ENABLE_01 = "FALSE";
+    parameter PHY_ENABLE_02 = "FALSE";
+    parameter PHY_ENABLE_03 = "FALSE";
+    parameter PHY_ENABLE_04 = "FALSE";
+    parameter PHY_ENABLE_05 = "FALSE";
+    parameter PHY_ENABLE_06 = "FALSE";
+    parameter PHY_ENABLE_07 = "FALSE";
+    parameter PHY_ENABLE_08 = "FALSE";
+    parameter PHY_ENABLE_09 = "FALSE";
+    parameter PHY_ENABLE_10 = "FALSE";
+    parameter PHY_ENABLE_11 = "FALSE";
+    parameter PHY_ENABLE_12 = "FALSE";
+    parameter PHY_ENABLE_13 = "FALSE";
+    parameter PHY_ENABLE_14 = "FALSE";
+    parameter PHY_ENABLE_15 = "FALSE";
+    parameter PHY_ENABLE_16 = "FALSE";
+    parameter PHY_ENABLE_17 = "FALSE";
+    parameter PHY_ENABLE_18 = "FALSE";
+    parameter PHY_ENABLE_19 = "FALSE";
+    parameter PHY_ENABLE_20 = "FALSE";
+    parameter PHY_ENABLE_21 = "FALSE";
+    parameter PHY_ENABLE_22 = "FALSE";
+    parameter PHY_ENABLE_23 = "FALSE";
+    parameter PHY_ENABLE_24 = "FALSE";
+    parameter PHY_ENABLE_25 = "FALSE";
+    parameter PHY_ENABLE_26 = "FALSE";
+    parameter PHY_ENABLE_27 = "FALSE";
+    parameter PHY_ENABLE_28 = "FALSE";
+    parameter PHY_ENABLE_29 = "FALSE";
+    parameter PHY_ENABLE_30 = "FALSE";
+    parameter PHY_ENABLE_31 = "FALSE";
+    parameter PHY_ENABLE_APB_00 = "FALSE";
+    parameter PHY_ENABLE_APB_01 = "FALSE";
+    parameter PHY_PCLK_INVERT_01 = "FALSE";
+    parameter PHY_PCLK_INVERT_02 = "FALSE";
+    parameter integer READ_PERCENT_00 = 50;
+    parameter integer READ_PERCENT_01 = 50;
+    parameter integer READ_PERCENT_02 = 50;
+    parameter integer READ_PERCENT_03 = 50;
+    parameter integer READ_PERCENT_04 = 50;
+    parameter integer READ_PERCENT_05 = 50;
+    parameter integer READ_PERCENT_06 = 50;
+    parameter integer READ_PERCENT_07 = 50;
+    parameter integer READ_PERCENT_08 = 50;
+    parameter integer READ_PERCENT_09 = 50;
+    parameter integer READ_PERCENT_10 = 50;
+    parameter integer READ_PERCENT_11 = 50;
+    parameter integer READ_PERCENT_12 = 50;
+    parameter integer READ_PERCENT_13 = 50;
+    parameter integer READ_PERCENT_14 = 50;
+    parameter integer READ_PERCENT_15 = 50;
+    parameter integer READ_PERCENT_16 = 50;
+    parameter integer READ_PERCENT_17 = 50;
+    parameter integer READ_PERCENT_18 = 50;
+    parameter integer READ_PERCENT_19 = 50;
+    parameter integer READ_PERCENT_20 = 50;
+    parameter integer READ_PERCENT_21 = 50;
+    parameter integer READ_PERCENT_22 = 50;
+    parameter integer READ_PERCENT_23 = 50;
+    parameter integer READ_PERCENT_24 = 50;
+    parameter integer READ_PERCENT_25 = 50;
+    parameter integer READ_PERCENT_26 = 50;
+    parameter integer READ_PERCENT_27 = 50;
+    parameter integer READ_PERCENT_28 = 50;
+    parameter integer READ_PERCENT_29 = 50;
+    parameter integer READ_PERCENT_30 = 50;
+    parameter integer READ_PERCENT_31 = 50;
+    parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+    parameter SWITCH_ENABLE_00 = "FALSE";
+    parameter SWITCH_ENABLE_01 = "FALSE";
+    parameter integer WRITE_PERCENT_00 = 50;
+    parameter integer WRITE_PERCENT_01 = 50;
+    parameter integer WRITE_PERCENT_02 = 50;
+    parameter integer WRITE_PERCENT_03 = 50;
+    parameter integer WRITE_PERCENT_04 = 50;
+    parameter integer WRITE_PERCENT_05 = 50;
+    parameter integer WRITE_PERCENT_06 = 50;
+    parameter integer WRITE_PERCENT_07 = 50;
+    parameter integer WRITE_PERCENT_08 = 50;
+    parameter integer WRITE_PERCENT_09 = 50;
+    parameter integer WRITE_PERCENT_10 = 50;
+    parameter integer WRITE_PERCENT_11 = 50;
+    parameter integer WRITE_PERCENT_12 = 50;
+    parameter integer WRITE_PERCENT_13 = 50;
+    parameter integer WRITE_PERCENT_14 = 50;
+    parameter integer WRITE_PERCENT_15 = 50;
+    parameter integer WRITE_PERCENT_16 = 50;
+    parameter integer WRITE_PERCENT_17 = 50;
+    parameter integer WRITE_PERCENT_18 = 50;
+    parameter integer WRITE_PERCENT_19 = 50;
+    parameter integer WRITE_PERCENT_20 = 50;
+    parameter integer WRITE_PERCENT_21 = 50;
+    parameter integer WRITE_PERCENT_22 = 50;
+    parameter integer WRITE_PERCENT_23 = 50;
+    parameter integer WRITE_PERCENT_24 = 50;
+    parameter integer WRITE_PERCENT_25 = 50;
+    parameter integer WRITE_PERCENT_26 = 50;
+    parameter integer WRITE_PERCENT_27 = 50;
+    parameter integer WRITE_PERCENT_28 = 50;
+    parameter integer WRITE_PERCENT_29 = 50;
+    parameter integer WRITE_PERCENT_30 = 50;
+    parameter integer WRITE_PERCENT_31 = 50;
+    output [31:0] APB_0_PRDATA;
+    output APB_0_PREADY;
+    output APB_0_PSLVERR;
+    output [31:0] APB_1_PRDATA;
+    output APB_1_PREADY;
+    output APB_1_PSLVERR;
+    output AXI_00_ARREADY;
+    output AXI_00_AWREADY;
+    output [5:0] AXI_00_BID;
+    output [1:0] AXI_00_BRESP;
+    output AXI_00_BVALID;
+    output [1:0] AXI_00_DFI_AW_AERR_N;
+    output AXI_00_DFI_CLK_BUF;
+    output [7:0] AXI_00_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_00_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_00_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_00_DFI_DW_RDDATA_VALID;
+    output AXI_00_DFI_INIT_COMPLETE;
+    output AXI_00_DFI_PHYUPD_REQ;
+    output AXI_00_DFI_PHY_LP_STATE;
+    output AXI_00_DFI_RST_N_BUF;
+    output [5:0] AXI_00_MC_STATUS;
+    output [7:0] AXI_00_PHY_STATUS;
+    output [255:0] AXI_00_RDATA;
+    output [31:0] AXI_00_RDATA_PARITY;
+    output [5:0] AXI_00_RID;
+    output AXI_00_RLAST;
+    output [1:0] AXI_00_RRESP;
+    output AXI_00_RVALID;
+    output AXI_00_WREADY;
+    output AXI_01_ARREADY;
+    output AXI_01_AWREADY;
+    output [5:0] AXI_01_BID;
+    output [1:0] AXI_01_BRESP;
+    output AXI_01_BVALID;
+    output [1:0] AXI_01_DFI_AW_AERR_N;
+    output AXI_01_DFI_CLK_BUF;
+    output [7:0] AXI_01_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_01_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_01_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_01_DFI_DW_RDDATA_VALID;
+    output AXI_01_DFI_INIT_COMPLETE;
+    output AXI_01_DFI_PHYUPD_REQ;
+    output AXI_01_DFI_PHY_LP_STATE;
+    output AXI_01_DFI_RST_N_BUF;
+    output [255:0] AXI_01_RDATA;
+    output [31:0] AXI_01_RDATA_PARITY;
+    output [5:0] AXI_01_RID;
+    output AXI_01_RLAST;
+    output [1:0] AXI_01_RRESP;
+    output AXI_01_RVALID;
+    output AXI_01_WREADY;
+    output AXI_02_ARREADY;
+    output AXI_02_AWREADY;
+    output [5:0] AXI_02_BID;
+    output [1:0] AXI_02_BRESP;
+    output AXI_02_BVALID;
+    output [1:0] AXI_02_DFI_AW_AERR_N;
+    output AXI_02_DFI_CLK_BUF;
+    output [7:0] AXI_02_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_02_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_02_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_02_DFI_DW_RDDATA_VALID;
+    output AXI_02_DFI_INIT_COMPLETE;
+    output AXI_02_DFI_PHYUPD_REQ;
+    output AXI_02_DFI_PHY_LP_STATE;
+    output AXI_02_DFI_RST_N_BUF;
+    output [5:0] AXI_02_MC_STATUS;
+    output [7:0] AXI_02_PHY_STATUS;
+    output [255:0] AXI_02_RDATA;
+    output [31:0] AXI_02_RDATA_PARITY;
+    output [5:0] AXI_02_RID;
+    output AXI_02_RLAST;
+    output [1:0] AXI_02_RRESP;
+    output AXI_02_RVALID;
+    output AXI_02_WREADY;
+    output AXI_03_ARREADY;
+    output AXI_03_AWREADY;
+    output [5:0] AXI_03_BID;
+    output [1:0] AXI_03_BRESP;
+    output AXI_03_BVALID;
+    output [1:0] AXI_03_DFI_AW_AERR_N;
+    output AXI_03_DFI_CLK_BUF;
+    output [7:0] AXI_03_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_03_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_03_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_03_DFI_DW_RDDATA_VALID;
+    output AXI_03_DFI_INIT_COMPLETE;
+    output AXI_03_DFI_PHYUPD_REQ;
+    output AXI_03_DFI_PHY_LP_STATE;
+    output AXI_03_DFI_RST_N_BUF;
+    output [255:0] AXI_03_RDATA;
+    output [31:0] AXI_03_RDATA_PARITY;
+    output [5:0] AXI_03_RID;
+    output AXI_03_RLAST;
+    output [1:0] AXI_03_RRESP;
+    output AXI_03_RVALID;
+    output AXI_03_WREADY;
+    output AXI_04_ARREADY;
+    output AXI_04_AWREADY;
+    output [5:0] AXI_04_BID;
+    output [1:0] AXI_04_BRESP;
+    output AXI_04_BVALID;
+    output [1:0] AXI_04_DFI_AW_AERR_N;
+    output AXI_04_DFI_CLK_BUF;
+    output [7:0] AXI_04_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_04_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_04_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_04_DFI_DW_RDDATA_VALID;
+    output AXI_04_DFI_INIT_COMPLETE;
+    output AXI_04_DFI_PHYUPD_REQ;
+    output AXI_04_DFI_PHY_LP_STATE;
+    output AXI_04_DFI_RST_N_BUF;
+    output [5:0] AXI_04_MC_STATUS;
+    output [7:0] AXI_04_PHY_STATUS;
+    output [255:0] AXI_04_RDATA;
+    output [31:0] AXI_04_RDATA_PARITY;
+    output [5:0] AXI_04_RID;
+    output AXI_04_RLAST;
+    output [1:0] AXI_04_RRESP;
+    output AXI_04_RVALID;
+    output AXI_04_WREADY;
+    output AXI_05_ARREADY;
+    output AXI_05_AWREADY;
+    output [5:0] AXI_05_BID;
+    output [1:0] AXI_05_BRESP;
+    output AXI_05_BVALID;
+    output [1:0] AXI_05_DFI_AW_AERR_N;
+    output AXI_05_DFI_CLK_BUF;
+    output [7:0] AXI_05_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_05_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_05_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_05_DFI_DW_RDDATA_VALID;
+    output AXI_05_DFI_INIT_COMPLETE;
+    output AXI_05_DFI_PHYUPD_REQ;
+    output AXI_05_DFI_PHY_LP_STATE;
+    output AXI_05_DFI_RST_N_BUF;
+    output [255:0] AXI_05_RDATA;
+    output [31:0] AXI_05_RDATA_PARITY;
+    output [5:0] AXI_05_RID;
+    output AXI_05_RLAST;
+    output [1:0] AXI_05_RRESP;
+    output AXI_05_RVALID;
+    output AXI_05_WREADY;
+    output AXI_06_ARREADY;
+    output AXI_06_AWREADY;
+    output [5:0] AXI_06_BID;
+    output [1:0] AXI_06_BRESP;
+    output AXI_06_BVALID;
+    output [1:0] AXI_06_DFI_AW_AERR_N;
+    output AXI_06_DFI_CLK_BUF;
+    output [7:0] AXI_06_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_06_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_06_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_06_DFI_DW_RDDATA_VALID;
+    output AXI_06_DFI_INIT_COMPLETE;
+    output AXI_06_DFI_PHYUPD_REQ;
+    output AXI_06_DFI_PHY_LP_STATE;
+    output AXI_06_DFI_RST_N_BUF;
+    output [5:0] AXI_06_MC_STATUS;
+    output [7:0] AXI_06_PHY_STATUS;
+    output [255:0] AXI_06_RDATA;
+    output [31:0] AXI_06_RDATA_PARITY;
+    output [5:0] AXI_06_RID;
+    output AXI_06_RLAST;
+    output [1:0] AXI_06_RRESP;
+    output AXI_06_RVALID;
+    output AXI_06_WREADY;
+    output AXI_07_ARREADY;
+    output AXI_07_AWREADY;
+    output [5:0] AXI_07_BID;
+    output [1:0] AXI_07_BRESP;
+    output AXI_07_BVALID;
+    output [1:0] AXI_07_DFI_AW_AERR_N;
+    output AXI_07_DFI_CLK_BUF;
+    output [7:0] AXI_07_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_07_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_07_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_07_DFI_DW_RDDATA_VALID;
+    output AXI_07_DFI_INIT_COMPLETE;
+    output AXI_07_DFI_PHYUPD_REQ;
+    output AXI_07_DFI_PHY_LP_STATE;
+    output AXI_07_DFI_RST_N_BUF;
+    output [255:0] AXI_07_RDATA;
+    output [31:0] AXI_07_RDATA_PARITY;
+    output [5:0] AXI_07_RID;
+    output AXI_07_RLAST;
+    output [1:0] AXI_07_RRESP;
+    output AXI_07_RVALID;
+    output AXI_07_WREADY;
+    output AXI_08_ARREADY;
+    output AXI_08_AWREADY;
+    output [5:0] AXI_08_BID;
+    output [1:0] AXI_08_BRESP;
+    output AXI_08_BVALID;
+    output [1:0] AXI_08_DFI_AW_AERR_N;
+    output AXI_08_DFI_CLK_BUF;
+    output [7:0] AXI_08_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_08_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_08_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_08_DFI_DW_RDDATA_VALID;
+    output AXI_08_DFI_INIT_COMPLETE;
+    output AXI_08_DFI_PHYUPD_REQ;
+    output AXI_08_DFI_PHY_LP_STATE;
+    output AXI_08_DFI_RST_N_BUF;
+    output [5:0] AXI_08_MC_STATUS;
+    output [7:0] AXI_08_PHY_STATUS;
+    output [255:0] AXI_08_RDATA;
+    output [31:0] AXI_08_RDATA_PARITY;
+    output [5:0] AXI_08_RID;
+    output AXI_08_RLAST;
+    output [1:0] AXI_08_RRESP;
+    output AXI_08_RVALID;
+    output AXI_08_WREADY;
+    output AXI_09_ARREADY;
+    output AXI_09_AWREADY;
+    output [5:0] AXI_09_BID;
+    output [1:0] AXI_09_BRESP;
+    output AXI_09_BVALID;
+    output [1:0] AXI_09_DFI_AW_AERR_N;
+    output AXI_09_DFI_CLK_BUF;
+    output [7:0] AXI_09_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_09_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_09_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_09_DFI_DW_RDDATA_VALID;
+    output AXI_09_DFI_INIT_COMPLETE;
+    output AXI_09_DFI_PHYUPD_REQ;
+    output AXI_09_DFI_PHY_LP_STATE;
+    output AXI_09_DFI_RST_N_BUF;
+    output [255:0] AXI_09_RDATA;
+    output [31:0] AXI_09_RDATA_PARITY;
+    output [5:0] AXI_09_RID;
+    output AXI_09_RLAST;
+    output [1:0] AXI_09_RRESP;
+    output AXI_09_RVALID;
+    output AXI_09_WREADY;
+    output AXI_10_ARREADY;
+    output AXI_10_AWREADY;
+    output [5:0] AXI_10_BID;
+    output [1:0] AXI_10_BRESP;
+    output AXI_10_BVALID;
+    output [1:0] AXI_10_DFI_AW_AERR_N;
+    output AXI_10_DFI_CLK_BUF;
+    output [7:0] AXI_10_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_10_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_10_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_10_DFI_DW_RDDATA_VALID;
+    output AXI_10_DFI_INIT_COMPLETE;
+    output AXI_10_DFI_PHYUPD_REQ;
+    output AXI_10_DFI_PHY_LP_STATE;
+    output AXI_10_DFI_RST_N_BUF;
+    output [5:0] AXI_10_MC_STATUS;
+    output [7:0] AXI_10_PHY_STATUS;
+    output [255:0] AXI_10_RDATA;
+    output [31:0] AXI_10_RDATA_PARITY;
+    output [5:0] AXI_10_RID;
+    output AXI_10_RLAST;
+    output [1:0] AXI_10_RRESP;
+    output AXI_10_RVALID;
+    output AXI_10_WREADY;
+    output AXI_11_ARREADY;
+    output AXI_11_AWREADY;
+    output [5:0] AXI_11_BID;
+    output [1:0] AXI_11_BRESP;
+    output AXI_11_BVALID;
+    output [1:0] AXI_11_DFI_AW_AERR_N;
+    output AXI_11_DFI_CLK_BUF;
+    output [7:0] AXI_11_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_11_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_11_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_11_DFI_DW_RDDATA_VALID;
+    output AXI_11_DFI_INIT_COMPLETE;
+    output AXI_11_DFI_PHYUPD_REQ;
+    output AXI_11_DFI_PHY_LP_STATE;
+    output AXI_11_DFI_RST_N_BUF;
+    output [255:0] AXI_11_RDATA;
+    output [31:0] AXI_11_RDATA_PARITY;
+    output [5:0] AXI_11_RID;
+    output AXI_11_RLAST;
+    output [1:0] AXI_11_RRESP;
+    output AXI_11_RVALID;
+    output AXI_11_WREADY;
+    output AXI_12_ARREADY;
+    output AXI_12_AWREADY;
+    output [5:0] AXI_12_BID;
+    output [1:0] AXI_12_BRESP;
+    output AXI_12_BVALID;
+    output [1:0] AXI_12_DFI_AW_AERR_N;
+    output AXI_12_DFI_CLK_BUF;
+    output [7:0] AXI_12_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_12_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_12_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_12_DFI_DW_RDDATA_VALID;
+    output AXI_12_DFI_INIT_COMPLETE;
+    output AXI_12_DFI_PHYUPD_REQ;
+    output AXI_12_DFI_PHY_LP_STATE;
+    output AXI_12_DFI_RST_N_BUF;
+    output [5:0] AXI_12_MC_STATUS;
+    output [7:0] AXI_12_PHY_STATUS;
+    output [255:0] AXI_12_RDATA;
+    output [31:0] AXI_12_RDATA_PARITY;
+    output [5:0] AXI_12_RID;
+    output AXI_12_RLAST;
+    output [1:0] AXI_12_RRESP;
+    output AXI_12_RVALID;
+    output AXI_12_WREADY;
+    output AXI_13_ARREADY;
+    output AXI_13_AWREADY;
+    output [5:0] AXI_13_BID;
+    output [1:0] AXI_13_BRESP;
+    output AXI_13_BVALID;
+    output [1:0] AXI_13_DFI_AW_AERR_N;
+    output AXI_13_DFI_CLK_BUF;
+    output [7:0] AXI_13_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_13_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_13_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_13_DFI_DW_RDDATA_VALID;
+    output AXI_13_DFI_INIT_COMPLETE;
+    output AXI_13_DFI_PHYUPD_REQ;
+    output AXI_13_DFI_PHY_LP_STATE;
+    output AXI_13_DFI_RST_N_BUF;
+    output [255:0] AXI_13_RDATA;
+    output [31:0] AXI_13_RDATA_PARITY;
+    output [5:0] AXI_13_RID;
+    output AXI_13_RLAST;
+    output [1:0] AXI_13_RRESP;
+    output AXI_13_RVALID;
+    output AXI_13_WREADY;
+    output AXI_14_ARREADY;
+    output AXI_14_AWREADY;
+    output [5:0] AXI_14_BID;
+    output [1:0] AXI_14_BRESP;
+    output AXI_14_BVALID;
+    output [1:0] AXI_14_DFI_AW_AERR_N;
+    output AXI_14_DFI_CLK_BUF;
+    output [7:0] AXI_14_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_14_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_14_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_14_DFI_DW_RDDATA_VALID;
+    output AXI_14_DFI_INIT_COMPLETE;
+    output AXI_14_DFI_PHYUPD_REQ;
+    output AXI_14_DFI_PHY_LP_STATE;
+    output AXI_14_DFI_RST_N_BUF;
+    output [5:0] AXI_14_MC_STATUS;
+    output [7:0] AXI_14_PHY_STATUS;
+    output [255:0] AXI_14_RDATA;
+    output [31:0] AXI_14_RDATA_PARITY;
+    output [5:0] AXI_14_RID;
+    output AXI_14_RLAST;
+    output [1:0] AXI_14_RRESP;
+    output AXI_14_RVALID;
+    output AXI_14_WREADY;
+    output AXI_15_ARREADY;
+    output AXI_15_AWREADY;
+    output [5:0] AXI_15_BID;
+    output [1:0] AXI_15_BRESP;
+    output AXI_15_BVALID;
+    output [1:0] AXI_15_DFI_AW_AERR_N;
+    output AXI_15_DFI_CLK_BUF;
+    output [7:0] AXI_15_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_15_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_15_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_15_DFI_DW_RDDATA_VALID;
+    output AXI_15_DFI_INIT_COMPLETE;
+    output AXI_15_DFI_PHYUPD_REQ;
+    output AXI_15_DFI_PHY_LP_STATE;
+    output AXI_15_DFI_RST_N_BUF;
+    output [255:0] AXI_15_RDATA;
+    output [31:0] AXI_15_RDATA_PARITY;
+    output [5:0] AXI_15_RID;
+    output AXI_15_RLAST;
+    output [1:0] AXI_15_RRESP;
+    output AXI_15_RVALID;
+    output AXI_15_WREADY;
+    output AXI_16_ARREADY;
+    output AXI_16_AWREADY;
+    output [5:0] AXI_16_BID;
+    output [1:0] AXI_16_BRESP;
+    output AXI_16_BVALID;
+    output [1:0] AXI_16_DFI_AW_AERR_N;
+    output AXI_16_DFI_CLK_BUF;
+    output [7:0] AXI_16_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_16_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_16_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_16_DFI_DW_RDDATA_VALID;
+    output AXI_16_DFI_INIT_COMPLETE;
+    output AXI_16_DFI_PHYUPD_REQ;
+    output AXI_16_DFI_PHY_LP_STATE;
+    output AXI_16_DFI_RST_N_BUF;
+    output [5:0] AXI_16_MC_STATUS;
+    output [7:0] AXI_16_PHY_STATUS;
+    output [255:0] AXI_16_RDATA;
+    output [31:0] AXI_16_RDATA_PARITY;
+    output [5:0] AXI_16_RID;
+    output AXI_16_RLAST;
+    output [1:0] AXI_16_RRESP;
+    output AXI_16_RVALID;
+    output AXI_16_WREADY;
+    output AXI_17_ARREADY;
+    output AXI_17_AWREADY;
+    output [5:0] AXI_17_BID;
+    output [1:0] AXI_17_BRESP;
+    output AXI_17_BVALID;
+    output [1:0] AXI_17_DFI_AW_AERR_N;
+    output AXI_17_DFI_CLK_BUF;
+    output [7:0] AXI_17_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_17_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_17_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_17_DFI_DW_RDDATA_VALID;
+    output AXI_17_DFI_INIT_COMPLETE;
+    output AXI_17_DFI_PHYUPD_REQ;
+    output AXI_17_DFI_PHY_LP_STATE;
+    output AXI_17_DFI_RST_N_BUF;
+    output [255:0] AXI_17_RDATA;
+    output [31:0] AXI_17_RDATA_PARITY;
+    output [5:0] AXI_17_RID;
+    output AXI_17_RLAST;
+    output [1:0] AXI_17_RRESP;
+    output AXI_17_RVALID;
+    output AXI_17_WREADY;
+    output AXI_18_ARREADY;
+    output AXI_18_AWREADY;
+    output [5:0] AXI_18_BID;
+    output [1:0] AXI_18_BRESP;
+    output AXI_18_BVALID;
+    output [1:0] AXI_18_DFI_AW_AERR_N;
+    output AXI_18_DFI_CLK_BUF;
+    output [7:0] AXI_18_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_18_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_18_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_18_DFI_DW_RDDATA_VALID;
+    output AXI_18_DFI_INIT_COMPLETE;
+    output AXI_18_DFI_PHYUPD_REQ;
+    output AXI_18_DFI_PHY_LP_STATE;
+    output AXI_18_DFI_RST_N_BUF;
+    output [5:0] AXI_18_MC_STATUS;
+    output [7:0] AXI_18_PHY_STATUS;
+    output [255:0] AXI_18_RDATA;
+    output [31:0] AXI_18_RDATA_PARITY;
+    output [5:0] AXI_18_RID;
+    output AXI_18_RLAST;
+    output [1:0] AXI_18_RRESP;
+    output AXI_18_RVALID;
+    output AXI_18_WREADY;
+    output AXI_19_ARREADY;
+    output AXI_19_AWREADY;
+    output [5:0] AXI_19_BID;
+    output [1:0] AXI_19_BRESP;
+    output AXI_19_BVALID;
+    output [1:0] AXI_19_DFI_AW_AERR_N;
+    output AXI_19_DFI_CLK_BUF;
+    output [7:0] AXI_19_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_19_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_19_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_19_DFI_DW_RDDATA_VALID;
+    output AXI_19_DFI_INIT_COMPLETE;
+    output AXI_19_DFI_PHYUPD_REQ;
+    output AXI_19_DFI_PHY_LP_STATE;
+    output AXI_19_DFI_RST_N_BUF;
+    output [255:0] AXI_19_RDATA;
+    output [31:0] AXI_19_RDATA_PARITY;
+    output [5:0] AXI_19_RID;
+    output AXI_19_RLAST;
+    output [1:0] AXI_19_RRESP;
+    output AXI_19_RVALID;
+    output AXI_19_WREADY;
+    output AXI_20_ARREADY;
+    output AXI_20_AWREADY;
+    output [5:0] AXI_20_BID;
+    output [1:0] AXI_20_BRESP;
+    output AXI_20_BVALID;
+    output [1:0] AXI_20_DFI_AW_AERR_N;
+    output AXI_20_DFI_CLK_BUF;
+    output [7:0] AXI_20_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_20_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_20_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_20_DFI_DW_RDDATA_VALID;
+    output AXI_20_DFI_INIT_COMPLETE;
+    output AXI_20_DFI_PHYUPD_REQ;
+    output AXI_20_DFI_PHY_LP_STATE;
+    output AXI_20_DFI_RST_N_BUF;
+    output [5:0] AXI_20_MC_STATUS;
+    output [7:0] AXI_20_PHY_STATUS;
+    output [255:0] AXI_20_RDATA;
+    output [31:0] AXI_20_RDATA_PARITY;
+    output [5:0] AXI_20_RID;
+    output AXI_20_RLAST;
+    output [1:0] AXI_20_RRESP;
+    output AXI_20_RVALID;
+    output AXI_20_WREADY;
+    output AXI_21_ARREADY;
+    output AXI_21_AWREADY;
+    output [5:0] AXI_21_BID;
+    output [1:0] AXI_21_BRESP;
+    output AXI_21_BVALID;
+    output [1:0] AXI_21_DFI_AW_AERR_N;
+    output AXI_21_DFI_CLK_BUF;
+    output [7:0] AXI_21_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_21_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_21_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_21_DFI_DW_RDDATA_VALID;
+    output AXI_21_DFI_INIT_COMPLETE;
+    output AXI_21_DFI_PHYUPD_REQ;
+    output AXI_21_DFI_PHY_LP_STATE;
+    output AXI_21_DFI_RST_N_BUF;
+    output [255:0] AXI_21_RDATA;
+    output [31:0] AXI_21_RDATA_PARITY;
+    output [5:0] AXI_21_RID;
+    output AXI_21_RLAST;
+    output [1:0] AXI_21_RRESP;
+    output AXI_21_RVALID;
+    output AXI_21_WREADY;
+    output AXI_22_ARREADY;
+    output AXI_22_AWREADY;
+    output [5:0] AXI_22_BID;
+    output [1:0] AXI_22_BRESP;
+    output AXI_22_BVALID;
+    output [1:0] AXI_22_DFI_AW_AERR_N;
+    output AXI_22_DFI_CLK_BUF;
+    output [7:0] AXI_22_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_22_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_22_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_22_DFI_DW_RDDATA_VALID;
+    output AXI_22_DFI_INIT_COMPLETE;
+    output AXI_22_DFI_PHYUPD_REQ;
+    output AXI_22_DFI_PHY_LP_STATE;
+    output AXI_22_DFI_RST_N_BUF;
+    output [5:0] AXI_22_MC_STATUS;
+    output [7:0] AXI_22_PHY_STATUS;
+    output [255:0] AXI_22_RDATA;
+    output [31:0] AXI_22_RDATA_PARITY;
+    output [5:0] AXI_22_RID;
+    output AXI_22_RLAST;
+    output [1:0] AXI_22_RRESP;
+    output AXI_22_RVALID;
+    output AXI_22_WREADY;
+    output AXI_23_ARREADY;
+    output AXI_23_AWREADY;
+    output [5:0] AXI_23_BID;
+    output [1:0] AXI_23_BRESP;
+    output AXI_23_BVALID;
+    output [1:0] AXI_23_DFI_AW_AERR_N;
+    output AXI_23_DFI_CLK_BUF;
+    output [7:0] AXI_23_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_23_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_23_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_23_DFI_DW_RDDATA_VALID;
+    output AXI_23_DFI_INIT_COMPLETE;
+    output AXI_23_DFI_PHYUPD_REQ;
+    output AXI_23_DFI_PHY_LP_STATE;
+    output AXI_23_DFI_RST_N_BUF;
+    output [255:0] AXI_23_RDATA;
+    output [31:0] AXI_23_RDATA_PARITY;
+    output [5:0] AXI_23_RID;
+    output AXI_23_RLAST;
+    output [1:0] AXI_23_RRESP;
+    output AXI_23_RVALID;
+    output AXI_23_WREADY;
+    output AXI_24_ARREADY;
+    output AXI_24_AWREADY;
+    output [5:0] AXI_24_BID;
+    output [1:0] AXI_24_BRESP;
+    output AXI_24_BVALID;
+    output [1:0] AXI_24_DFI_AW_AERR_N;
+    output AXI_24_DFI_CLK_BUF;
+    output [7:0] AXI_24_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_24_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_24_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_24_DFI_DW_RDDATA_VALID;
+    output AXI_24_DFI_INIT_COMPLETE;
+    output AXI_24_DFI_PHYUPD_REQ;
+    output AXI_24_DFI_PHY_LP_STATE;
+    output AXI_24_DFI_RST_N_BUF;
+    output [5:0] AXI_24_MC_STATUS;
+    output [7:0] AXI_24_PHY_STATUS;
+    output [255:0] AXI_24_RDATA;
+    output [31:0] AXI_24_RDATA_PARITY;
+    output [5:0] AXI_24_RID;
+    output AXI_24_RLAST;
+    output [1:0] AXI_24_RRESP;
+    output AXI_24_RVALID;
+    output AXI_24_WREADY;
+    output AXI_25_ARREADY;
+    output AXI_25_AWREADY;
+    output [5:0] AXI_25_BID;
+    output [1:0] AXI_25_BRESP;
+    output AXI_25_BVALID;
+    output [1:0] AXI_25_DFI_AW_AERR_N;
+    output AXI_25_DFI_CLK_BUF;
+    output [7:0] AXI_25_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_25_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_25_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_25_DFI_DW_RDDATA_VALID;
+    output AXI_25_DFI_INIT_COMPLETE;
+    output AXI_25_DFI_PHYUPD_REQ;
+    output AXI_25_DFI_PHY_LP_STATE;
+    output AXI_25_DFI_RST_N_BUF;
+    output [255:0] AXI_25_RDATA;
+    output [31:0] AXI_25_RDATA_PARITY;
+    output [5:0] AXI_25_RID;
+    output AXI_25_RLAST;
+    output [1:0] AXI_25_RRESP;
+    output AXI_25_RVALID;
+    output AXI_25_WREADY;
+    output AXI_26_ARREADY;
+    output AXI_26_AWREADY;
+    output [5:0] AXI_26_BID;
+    output [1:0] AXI_26_BRESP;
+    output AXI_26_BVALID;
+    output [1:0] AXI_26_DFI_AW_AERR_N;
+    output AXI_26_DFI_CLK_BUF;
+    output [7:0] AXI_26_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_26_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_26_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_26_DFI_DW_RDDATA_VALID;
+    output AXI_26_DFI_INIT_COMPLETE;
+    output AXI_26_DFI_PHYUPD_REQ;
+    output AXI_26_DFI_PHY_LP_STATE;
+    output AXI_26_DFI_RST_N_BUF;
+    output [5:0] AXI_26_MC_STATUS;
+    output [7:0] AXI_26_PHY_STATUS;
+    output [255:0] AXI_26_RDATA;
+    output [31:0] AXI_26_RDATA_PARITY;
+    output [5:0] AXI_26_RID;
+    output AXI_26_RLAST;
+    output [1:0] AXI_26_RRESP;
+    output AXI_26_RVALID;
+    output AXI_26_WREADY;
+    output AXI_27_ARREADY;
+    output AXI_27_AWREADY;
+    output [5:0] AXI_27_BID;
+    output [1:0] AXI_27_BRESP;
+    output AXI_27_BVALID;
+    output [1:0] AXI_27_DFI_AW_AERR_N;
+    output AXI_27_DFI_CLK_BUF;
+    output [7:0] AXI_27_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_27_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_27_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_27_DFI_DW_RDDATA_VALID;
+    output AXI_27_DFI_INIT_COMPLETE;
+    output AXI_27_DFI_PHYUPD_REQ;
+    output AXI_27_DFI_PHY_LP_STATE;
+    output AXI_27_DFI_RST_N_BUF;
+    output [255:0] AXI_27_RDATA;
+    output [31:0] AXI_27_RDATA_PARITY;
+    output [5:0] AXI_27_RID;
+    output AXI_27_RLAST;
+    output [1:0] AXI_27_RRESP;
+    output AXI_27_RVALID;
+    output AXI_27_WREADY;
+    output AXI_28_ARREADY;
+    output AXI_28_AWREADY;
+    output [5:0] AXI_28_BID;
+    output [1:0] AXI_28_BRESP;
+    output AXI_28_BVALID;
+    output [1:0] AXI_28_DFI_AW_AERR_N;
+    output AXI_28_DFI_CLK_BUF;
+    output [7:0] AXI_28_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_28_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_28_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_28_DFI_DW_RDDATA_VALID;
+    output AXI_28_DFI_INIT_COMPLETE;
+    output AXI_28_DFI_PHYUPD_REQ;
+    output AXI_28_DFI_PHY_LP_STATE;
+    output AXI_28_DFI_RST_N_BUF;
+    output [5:0] AXI_28_MC_STATUS;
+    output [7:0] AXI_28_PHY_STATUS;
+    output [255:0] AXI_28_RDATA;
+    output [31:0] AXI_28_RDATA_PARITY;
+    output [5:0] AXI_28_RID;
+    output AXI_28_RLAST;
+    output [1:0] AXI_28_RRESP;
+    output AXI_28_RVALID;
+    output AXI_28_WREADY;
+    output AXI_29_ARREADY;
+    output AXI_29_AWREADY;
+    output [5:0] AXI_29_BID;
+    output [1:0] AXI_29_BRESP;
+    output AXI_29_BVALID;
+    output [1:0] AXI_29_DFI_AW_AERR_N;
+    output AXI_29_DFI_CLK_BUF;
+    output [7:0] AXI_29_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_29_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_29_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_29_DFI_DW_RDDATA_VALID;
+    output AXI_29_DFI_INIT_COMPLETE;
+    output AXI_29_DFI_PHYUPD_REQ;
+    output AXI_29_DFI_PHY_LP_STATE;
+    output AXI_29_DFI_RST_N_BUF;
+    output [255:0] AXI_29_RDATA;
+    output [31:0] AXI_29_RDATA_PARITY;
+    output [5:0] AXI_29_RID;
+    output AXI_29_RLAST;
+    output [1:0] AXI_29_RRESP;
+    output AXI_29_RVALID;
+    output AXI_29_WREADY;
+    output AXI_30_ARREADY;
+    output AXI_30_AWREADY;
+    output [5:0] AXI_30_BID;
+    output [1:0] AXI_30_BRESP;
+    output AXI_30_BVALID;
+    output [1:0] AXI_30_DFI_AW_AERR_N;
+    output AXI_30_DFI_CLK_BUF;
+    output [7:0] AXI_30_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_30_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_30_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_30_DFI_DW_RDDATA_VALID;
+    output AXI_30_DFI_INIT_COMPLETE;
+    output AXI_30_DFI_PHYUPD_REQ;
+    output AXI_30_DFI_PHY_LP_STATE;
+    output AXI_30_DFI_RST_N_BUF;
+    output [5:0] AXI_30_MC_STATUS;
+    output [7:0] AXI_30_PHY_STATUS;
+    output [255:0] AXI_30_RDATA;
+    output [31:0] AXI_30_RDATA_PARITY;
+    output [5:0] AXI_30_RID;
+    output AXI_30_RLAST;
+    output [1:0] AXI_30_RRESP;
+    output AXI_30_RVALID;
+    output AXI_30_WREADY;
+    output AXI_31_ARREADY;
+    output AXI_31_AWREADY;
+    output [5:0] AXI_31_BID;
+    output [1:0] AXI_31_BRESP;
+    output AXI_31_BVALID;
+    output [1:0] AXI_31_DFI_AW_AERR_N;
+    output AXI_31_DFI_CLK_BUF;
+    output [7:0] AXI_31_DFI_DBI_BYTE_DISABLE;
+    output [20:0] AXI_31_DFI_DW_RDDATA_DBI;
+    output [7:0] AXI_31_DFI_DW_RDDATA_DERR;
+    output [1:0] AXI_31_DFI_DW_RDDATA_VALID;
+    output AXI_31_DFI_INIT_COMPLETE;
+    output AXI_31_DFI_PHYUPD_REQ;
+    output AXI_31_DFI_PHY_LP_STATE;
+    output AXI_31_DFI_RST_N_BUF;
+    output [255:0] AXI_31_RDATA;
+    output [31:0] AXI_31_RDATA_PARITY;
+    output [5:0] AXI_31_RID;
+    output AXI_31_RLAST;
+    output [1:0] AXI_31_RRESP;
+    output AXI_31_RVALID;
+    output AXI_31_WREADY;
+    output DRAM_0_STAT_CATTRIP;
+    output [2:0] DRAM_0_STAT_TEMP;
+    output DRAM_1_STAT_CATTRIP;
+    output [2:0] DRAM_1_STAT_TEMP;
+    input [21:0] APB_0_PADDR;
+    (* invertible_pin = "IS_APB_0_PCLK_INVERTED" *)
+    input APB_0_PCLK;
+    input APB_0_PENABLE;
+    (* invertible_pin = "IS_APB_0_PRESET_N_INVERTED" *)
+    input APB_0_PRESET_N;
+    input APB_0_PSEL;
+    input [31:0] APB_0_PWDATA;
+    input APB_0_PWRITE;
+    input [21:0] APB_1_PADDR;
+    (* invertible_pin = "IS_APB_1_PCLK_INVERTED" *)
+    input APB_1_PCLK;
+    input APB_1_PENABLE;
+    (* invertible_pin = "IS_APB_1_PRESET_N_INVERTED" *)
+    input APB_1_PRESET_N;
+    input APB_1_PSEL;
+    input [31:0] APB_1_PWDATA;
+    input APB_1_PWRITE;
+    (* invertible_pin = "IS_AXI_00_ACLK_INVERTED" *)
+    input AXI_00_ACLK;
+    input [36:0] AXI_00_ARADDR;
+    input [1:0] AXI_00_ARBURST;
+    (* invertible_pin = "IS_AXI_00_ARESET_N_INVERTED" *)
+    input AXI_00_ARESET_N;
+    input [5:0] AXI_00_ARID;
+    input [3:0] AXI_00_ARLEN;
+    input [2:0] AXI_00_ARSIZE;
+    input AXI_00_ARVALID;
+    input [36:0] AXI_00_AWADDR;
+    input [1:0] AXI_00_AWBURST;
+    input [5:0] AXI_00_AWID;
+    input [3:0] AXI_00_AWLEN;
+    input [2:0] AXI_00_AWSIZE;
+    input AXI_00_AWVALID;
+    input AXI_00_BREADY;
+    input AXI_00_DFI_LP_PWR_X_REQ;
+    input AXI_00_RREADY;
+    input [255:0] AXI_00_WDATA;
+    input [31:0] AXI_00_WDATA_PARITY;
+    input AXI_00_WLAST;
+    input [31:0] AXI_00_WSTRB;
+    input AXI_00_WVALID;
+    (* invertible_pin = "IS_AXI_01_ACLK_INVERTED" *)
+    input AXI_01_ACLK;
+    input [36:0] AXI_01_ARADDR;
+    input [1:0] AXI_01_ARBURST;
+    (* invertible_pin = "IS_AXI_01_ARESET_N_INVERTED" *)
+    input AXI_01_ARESET_N;
+    input [5:0] AXI_01_ARID;
+    input [3:0] AXI_01_ARLEN;
+    input [2:0] AXI_01_ARSIZE;
+    input AXI_01_ARVALID;
+    input [36:0] AXI_01_AWADDR;
+    input [1:0] AXI_01_AWBURST;
+    input [5:0] AXI_01_AWID;
+    input [3:0] AXI_01_AWLEN;
+    input [2:0] AXI_01_AWSIZE;
+    input AXI_01_AWVALID;
+    input AXI_01_BREADY;
+    input AXI_01_DFI_LP_PWR_X_REQ;
+    input AXI_01_RREADY;
+    input [255:0] AXI_01_WDATA;
+    input [31:0] AXI_01_WDATA_PARITY;
+    input AXI_01_WLAST;
+    input [31:0] AXI_01_WSTRB;
+    input AXI_01_WVALID;
+    (* invertible_pin = "IS_AXI_02_ACLK_INVERTED" *)
+    input AXI_02_ACLK;
+    input [36:0] AXI_02_ARADDR;
+    input [1:0] AXI_02_ARBURST;
+    (* invertible_pin = "IS_AXI_02_ARESET_N_INVERTED" *)
+    input AXI_02_ARESET_N;
+    input [5:0] AXI_02_ARID;
+    input [3:0] AXI_02_ARLEN;
+    input [2:0] AXI_02_ARSIZE;
+    input AXI_02_ARVALID;
+    input [36:0] AXI_02_AWADDR;
+    input [1:0] AXI_02_AWBURST;
+    input [5:0] AXI_02_AWID;
+    input [3:0] AXI_02_AWLEN;
+    input [2:0] AXI_02_AWSIZE;
+    input AXI_02_AWVALID;
+    input AXI_02_BREADY;
+    input AXI_02_DFI_LP_PWR_X_REQ;
+    input AXI_02_RREADY;
+    input [255:0] AXI_02_WDATA;
+    input [31:0] AXI_02_WDATA_PARITY;
+    input AXI_02_WLAST;
+    input [31:0] AXI_02_WSTRB;
+    input AXI_02_WVALID;
+    (* invertible_pin = "IS_AXI_03_ACLK_INVERTED" *)
+    input AXI_03_ACLK;
+    input [36:0] AXI_03_ARADDR;
+    input [1:0] AXI_03_ARBURST;
+    (* invertible_pin = "IS_AXI_03_ARESET_N_INVERTED" *)
+    input AXI_03_ARESET_N;
+    input [5:0] AXI_03_ARID;
+    input [3:0] AXI_03_ARLEN;
+    input [2:0] AXI_03_ARSIZE;
+    input AXI_03_ARVALID;
+    input [36:0] AXI_03_AWADDR;
+    input [1:0] AXI_03_AWBURST;
+    input [5:0] AXI_03_AWID;
+    input [3:0] AXI_03_AWLEN;
+    input [2:0] AXI_03_AWSIZE;
+    input AXI_03_AWVALID;
+    input AXI_03_BREADY;
+    input AXI_03_DFI_LP_PWR_X_REQ;
+    input AXI_03_RREADY;
+    input [255:0] AXI_03_WDATA;
+    input [31:0] AXI_03_WDATA_PARITY;
+    input AXI_03_WLAST;
+    input [31:0] AXI_03_WSTRB;
+    input AXI_03_WVALID;
+    (* invertible_pin = "IS_AXI_04_ACLK_INVERTED" *)
+    input AXI_04_ACLK;
+    input [36:0] AXI_04_ARADDR;
+    input [1:0] AXI_04_ARBURST;
+    (* invertible_pin = "IS_AXI_04_ARESET_N_INVERTED" *)
+    input AXI_04_ARESET_N;
+    input [5:0] AXI_04_ARID;
+    input [3:0] AXI_04_ARLEN;
+    input [2:0] AXI_04_ARSIZE;
+    input AXI_04_ARVALID;
+    input [36:0] AXI_04_AWADDR;
+    input [1:0] AXI_04_AWBURST;
+    input [5:0] AXI_04_AWID;
+    input [3:0] AXI_04_AWLEN;
+    input [2:0] AXI_04_AWSIZE;
+    input AXI_04_AWVALID;
+    input AXI_04_BREADY;
+    input AXI_04_DFI_LP_PWR_X_REQ;
+    input AXI_04_RREADY;
+    input [255:0] AXI_04_WDATA;
+    input [31:0] AXI_04_WDATA_PARITY;
+    input AXI_04_WLAST;
+    input [31:0] AXI_04_WSTRB;
+    input AXI_04_WVALID;
+    (* invertible_pin = "IS_AXI_05_ACLK_INVERTED" *)
+    input AXI_05_ACLK;
+    input [36:0] AXI_05_ARADDR;
+    input [1:0] AXI_05_ARBURST;
+    (* invertible_pin = "IS_AXI_05_ARESET_N_INVERTED" *)
+    input AXI_05_ARESET_N;
+    input [5:0] AXI_05_ARID;
+    input [3:0] AXI_05_ARLEN;
+    input [2:0] AXI_05_ARSIZE;
+    input AXI_05_ARVALID;
+    input [36:0] AXI_05_AWADDR;
+    input [1:0] AXI_05_AWBURST;
+    input [5:0] AXI_05_AWID;
+    input [3:0] AXI_05_AWLEN;
+    input [2:0] AXI_05_AWSIZE;
+    input AXI_05_AWVALID;
+    input AXI_05_BREADY;
+    input AXI_05_DFI_LP_PWR_X_REQ;
+    input AXI_05_RREADY;
+    input [255:0] AXI_05_WDATA;
+    input [31:0] AXI_05_WDATA_PARITY;
+    input AXI_05_WLAST;
+    input [31:0] AXI_05_WSTRB;
+    input AXI_05_WVALID;
+    (* invertible_pin = "IS_AXI_06_ACLK_INVERTED" *)
+    input AXI_06_ACLK;
+    input [36:0] AXI_06_ARADDR;
+    input [1:0] AXI_06_ARBURST;
+    (* invertible_pin = "IS_AXI_06_ARESET_N_INVERTED" *)
+    input AXI_06_ARESET_N;
+    input [5:0] AXI_06_ARID;
+    input [3:0] AXI_06_ARLEN;
+    input [2:0] AXI_06_ARSIZE;
+    input AXI_06_ARVALID;
+    input [36:0] AXI_06_AWADDR;
+    input [1:0] AXI_06_AWBURST;
+    input [5:0] AXI_06_AWID;
+    input [3:0] AXI_06_AWLEN;
+    input [2:0] AXI_06_AWSIZE;
+    input AXI_06_AWVALID;
+    input AXI_06_BREADY;
+    input AXI_06_DFI_LP_PWR_X_REQ;
+    input AXI_06_RREADY;
+    input [255:0] AXI_06_WDATA;
+    input [31:0] AXI_06_WDATA_PARITY;
+    input AXI_06_WLAST;
+    input [31:0] AXI_06_WSTRB;
+    input AXI_06_WVALID;
+    (* invertible_pin = "IS_AXI_07_ACLK_INVERTED" *)
+    input AXI_07_ACLK;
+    input [36:0] AXI_07_ARADDR;
+    input [1:0] AXI_07_ARBURST;
+    (* invertible_pin = "IS_AXI_07_ARESET_N_INVERTED" *)
+    input AXI_07_ARESET_N;
+    input [5:0] AXI_07_ARID;
+    input [3:0] AXI_07_ARLEN;
+    input [2:0] AXI_07_ARSIZE;
+    input AXI_07_ARVALID;
+    input [36:0] AXI_07_AWADDR;
+    input [1:0] AXI_07_AWBURST;
+    input [5:0] AXI_07_AWID;
+    input [3:0] AXI_07_AWLEN;
+    input [2:0] AXI_07_AWSIZE;
+    input AXI_07_AWVALID;
+    input AXI_07_BREADY;
+    input AXI_07_DFI_LP_PWR_X_REQ;
+    input AXI_07_RREADY;
+    input [255:0] AXI_07_WDATA;
+    input [31:0] AXI_07_WDATA_PARITY;
+    input AXI_07_WLAST;
+    input [31:0] AXI_07_WSTRB;
+    input AXI_07_WVALID;
+    (* invertible_pin = "IS_AXI_08_ACLK_INVERTED" *)
+    input AXI_08_ACLK;
+    input [36:0] AXI_08_ARADDR;
+    input [1:0] AXI_08_ARBURST;
+    (* invertible_pin = "IS_AXI_08_ARESET_N_INVERTED" *)
+    input AXI_08_ARESET_N;
+    input [5:0] AXI_08_ARID;
+    input [3:0] AXI_08_ARLEN;
+    input [2:0] AXI_08_ARSIZE;
+    input AXI_08_ARVALID;
+    input [36:0] AXI_08_AWADDR;
+    input [1:0] AXI_08_AWBURST;
+    input [5:0] AXI_08_AWID;
+    input [3:0] AXI_08_AWLEN;
+    input [2:0] AXI_08_AWSIZE;
+    input AXI_08_AWVALID;
+    input AXI_08_BREADY;
+    input AXI_08_DFI_LP_PWR_X_REQ;
+    input AXI_08_RREADY;
+    input [255:0] AXI_08_WDATA;
+    input [31:0] AXI_08_WDATA_PARITY;
+    input AXI_08_WLAST;
+    input [31:0] AXI_08_WSTRB;
+    input AXI_08_WVALID;
+    (* invertible_pin = "IS_AXI_09_ACLK_INVERTED" *)
+    input AXI_09_ACLK;
+    input [36:0] AXI_09_ARADDR;
+    input [1:0] AXI_09_ARBURST;
+    (* invertible_pin = "IS_AXI_09_ARESET_N_INVERTED" *)
+    input AXI_09_ARESET_N;
+    input [5:0] AXI_09_ARID;
+    input [3:0] AXI_09_ARLEN;
+    input [2:0] AXI_09_ARSIZE;
+    input AXI_09_ARVALID;
+    input [36:0] AXI_09_AWADDR;
+    input [1:0] AXI_09_AWBURST;
+    input [5:0] AXI_09_AWID;
+    input [3:0] AXI_09_AWLEN;
+    input [2:0] AXI_09_AWSIZE;
+    input AXI_09_AWVALID;
+    input AXI_09_BREADY;
+    input AXI_09_DFI_LP_PWR_X_REQ;
+    input AXI_09_RREADY;
+    input [255:0] AXI_09_WDATA;
+    input [31:0] AXI_09_WDATA_PARITY;
+    input AXI_09_WLAST;
+    input [31:0] AXI_09_WSTRB;
+    input AXI_09_WVALID;
+    (* invertible_pin = "IS_AXI_10_ACLK_INVERTED" *)
+    input AXI_10_ACLK;
+    input [36:0] AXI_10_ARADDR;
+    input [1:0] AXI_10_ARBURST;
+    (* invertible_pin = "IS_AXI_10_ARESET_N_INVERTED" *)
+    input AXI_10_ARESET_N;
+    input [5:0] AXI_10_ARID;
+    input [3:0] AXI_10_ARLEN;
+    input [2:0] AXI_10_ARSIZE;
+    input AXI_10_ARVALID;
+    input [36:0] AXI_10_AWADDR;
+    input [1:0] AXI_10_AWBURST;
+    input [5:0] AXI_10_AWID;
+    input [3:0] AXI_10_AWLEN;
+    input [2:0] AXI_10_AWSIZE;
+    input AXI_10_AWVALID;
+    input AXI_10_BREADY;
+    input AXI_10_DFI_LP_PWR_X_REQ;
+    input AXI_10_RREADY;
+    input [255:0] AXI_10_WDATA;
+    input [31:0] AXI_10_WDATA_PARITY;
+    input AXI_10_WLAST;
+    input [31:0] AXI_10_WSTRB;
+    input AXI_10_WVALID;
+    (* invertible_pin = "IS_AXI_11_ACLK_INVERTED" *)
+    input AXI_11_ACLK;
+    input [36:0] AXI_11_ARADDR;
+    input [1:0] AXI_11_ARBURST;
+    (* invertible_pin = "IS_AXI_11_ARESET_N_INVERTED" *)
+    input AXI_11_ARESET_N;
+    input [5:0] AXI_11_ARID;
+    input [3:0] AXI_11_ARLEN;
+    input [2:0] AXI_11_ARSIZE;
+    input AXI_11_ARVALID;
+    input [36:0] AXI_11_AWADDR;
+    input [1:0] AXI_11_AWBURST;
+    input [5:0] AXI_11_AWID;
+    input [3:0] AXI_11_AWLEN;
+    input [2:0] AXI_11_AWSIZE;
+    input AXI_11_AWVALID;
+    input AXI_11_BREADY;
+    input AXI_11_DFI_LP_PWR_X_REQ;
+    input AXI_11_RREADY;
+    input [255:0] AXI_11_WDATA;
+    input [31:0] AXI_11_WDATA_PARITY;
+    input AXI_11_WLAST;
+    input [31:0] AXI_11_WSTRB;
+    input AXI_11_WVALID;
+    (* invertible_pin = "IS_AXI_12_ACLK_INVERTED" *)
+    input AXI_12_ACLK;
+    input [36:0] AXI_12_ARADDR;
+    input [1:0] AXI_12_ARBURST;
+    (* invertible_pin = "IS_AXI_12_ARESET_N_INVERTED" *)
+    input AXI_12_ARESET_N;
+    input [5:0] AXI_12_ARID;
+    input [3:0] AXI_12_ARLEN;
+    input [2:0] AXI_12_ARSIZE;
+    input AXI_12_ARVALID;
+    input [36:0] AXI_12_AWADDR;
+    input [1:0] AXI_12_AWBURST;
+    input [5:0] AXI_12_AWID;
+    input [3:0] AXI_12_AWLEN;
+    input [2:0] AXI_12_AWSIZE;
+    input AXI_12_AWVALID;
+    input AXI_12_BREADY;
+    input AXI_12_DFI_LP_PWR_X_REQ;
+    input AXI_12_RREADY;
+    input [255:0] AXI_12_WDATA;
+    input [31:0] AXI_12_WDATA_PARITY;
+    input AXI_12_WLAST;
+    input [31:0] AXI_12_WSTRB;
+    input AXI_12_WVALID;
+    (* invertible_pin = "IS_AXI_13_ACLK_INVERTED" *)
+    input AXI_13_ACLK;
+    input [36:0] AXI_13_ARADDR;
+    input [1:0] AXI_13_ARBURST;
+    (* invertible_pin = "IS_AXI_13_ARESET_N_INVERTED" *)
+    input AXI_13_ARESET_N;
+    input [5:0] AXI_13_ARID;
+    input [3:0] AXI_13_ARLEN;
+    input [2:0] AXI_13_ARSIZE;
+    input AXI_13_ARVALID;
+    input [36:0] AXI_13_AWADDR;
+    input [1:0] AXI_13_AWBURST;
+    input [5:0] AXI_13_AWID;
+    input [3:0] AXI_13_AWLEN;
+    input [2:0] AXI_13_AWSIZE;
+    input AXI_13_AWVALID;
+    input AXI_13_BREADY;
+    input AXI_13_DFI_LP_PWR_X_REQ;
+    input AXI_13_RREADY;
+    input [255:0] AXI_13_WDATA;
+    input [31:0] AXI_13_WDATA_PARITY;
+    input AXI_13_WLAST;
+    input [31:0] AXI_13_WSTRB;
+    input AXI_13_WVALID;
+    (* invertible_pin = "IS_AXI_14_ACLK_INVERTED" *)
+    input AXI_14_ACLK;
+    input [36:0] AXI_14_ARADDR;
+    input [1:0] AXI_14_ARBURST;
+    (* invertible_pin = "IS_AXI_14_ARESET_N_INVERTED" *)
+    input AXI_14_ARESET_N;
+    input [5:0] AXI_14_ARID;
+    input [3:0] AXI_14_ARLEN;
+    input [2:0] AXI_14_ARSIZE;
+    input AXI_14_ARVALID;
+    input [36:0] AXI_14_AWADDR;
+    input [1:0] AXI_14_AWBURST;
+    input [5:0] AXI_14_AWID;
+    input [3:0] AXI_14_AWLEN;
+    input [2:0] AXI_14_AWSIZE;
+    input AXI_14_AWVALID;
+    input AXI_14_BREADY;
+    input AXI_14_DFI_LP_PWR_X_REQ;
+    input AXI_14_RREADY;
+    input [255:0] AXI_14_WDATA;
+    input [31:0] AXI_14_WDATA_PARITY;
+    input AXI_14_WLAST;
+    input [31:0] AXI_14_WSTRB;
+    input AXI_14_WVALID;
+    (* invertible_pin = "IS_AXI_15_ACLK_INVERTED" *)
+    input AXI_15_ACLK;
+    input [36:0] AXI_15_ARADDR;
+    input [1:0] AXI_15_ARBURST;
+    (* invertible_pin = "IS_AXI_15_ARESET_N_INVERTED" *)
+    input AXI_15_ARESET_N;
+    input [5:0] AXI_15_ARID;
+    input [3:0] AXI_15_ARLEN;
+    input [2:0] AXI_15_ARSIZE;
+    input AXI_15_ARVALID;
+    input [36:0] AXI_15_AWADDR;
+    input [1:0] AXI_15_AWBURST;
+    input [5:0] AXI_15_AWID;
+    input [3:0] AXI_15_AWLEN;
+    input [2:0] AXI_15_AWSIZE;
+    input AXI_15_AWVALID;
+    input AXI_15_BREADY;
+    input AXI_15_DFI_LP_PWR_X_REQ;
+    input AXI_15_RREADY;
+    input [255:0] AXI_15_WDATA;
+    input [31:0] AXI_15_WDATA_PARITY;
+    input AXI_15_WLAST;
+    input [31:0] AXI_15_WSTRB;
+    input AXI_15_WVALID;
+    (* invertible_pin = "IS_AXI_16_ACLK_INVERTED" *)
+    input AXI_16_ACLK;
+    input [36:0] AXI_16_ARADDR;
+    input [1:0] AXI_16_ARBURST;
+    (* invertible_pin = "IS_AXI_16_ARESET_N_INVERTED" *)
+    input AXI_16_ARESET_N;
+    input [5:0] AXI_16_ARID;
+    input [3:0] AXI_16_ARLEN;
+    input [2:0] AXI_16_ARSIZE;
+    input AXI_16_ARVALID;
+    input [36:0] AXI_16_AWADDR;
+    input [1:0] AXI_16_AWBURST;
+    input [5:0] AXI_16_AWID;
+    input [3:0] AXI_16_AWLEN;
+    input [2:0] AXI_16_AWSIZE;
+    input AXI_16_AWVALID;
+    input AXI_16_BREADY;
+    input AXI_16_DFI_LP_PWR_X_REQ;
+    input AXI_16_RREADY;
+    input [255:0] AXI_16_WDATA;
+    input [31:0] AXI_16_WDATA_PARITY;
+    input AXI_16_WLAST;
+    input [31:0] AXI_16_WSTRB;
+    input AXI_16_WVALID;
+    (* invertible_pin = "IS_AXI_17_ACLK_INVERTED" *)
+    input AXI_17_ACLK;
+    input [36:0] AXI_17_ARADDR;
+    input [1:0] AXI_17_ARBURST;
+    (* invertible_pin = "IS_AXI_17_ARESET_N_INVERTED" *)
+    input AXI_17_ARESET_N;
+    input [5:0] AXI_17_ARID;
+    input [3:0] AXI_17_ARLEN;
+    input [2:0] AXI_17_ARSIZE;
+    input AXI_17_ARVALID;
+    input [36:0] AXI_17_AWADDR;
+    input [1:0] AXI_17_AWBURST;
+    input [5:0] AXI_17_AWID;
+    input [3:0] AXI_17_AWLEN;
+    input [2:0] AXI_17_AWSIZE;
+    input AXI_17_AWVALID;
+    input AXI_17_BREADY;
+    input AXI_17_DFI_LP_PWR_X_REQ;
+    input AXI_17_RREADY;
+    input [255:0] AXI_17_WDATA;
+    input [31:0] AXI_17_WDATA_PARITY;
+    input AXI_17_WLAST;
+    input [31:0] AXI_17_WSTRB;
+    input AXI_17_WVALID;
+    (* invertible_pin = "IS_AXI_18_ACLK_INVERTED" *)
+    input AXI_18_ACLK;
+    input [36:0] AXI_18_ARADDR;
+    input [1:0] AXI_18_ARBURST;
+    (* invertible_pin = "IS_AXI_18_ARESET_N_INVERTED" *)
+    input AXI_18_ARESET_N;
+    input [5:0] AXI_18_ARID;
+    input [3:0] AXI_18_ARLEN;
+    input [2:0] AXI_18_ARSIZE;
+    input AXI_18_ARVALID;
+    input [36:0] AXI_18_AWADDR;
+    input [1:0] AXI_18_AWBURST;
+    input [5:0] AXI_18_AWID;
+    input [3:0] AXI_18_AWLEN;
+    input [2:0] AXI_18_AWSIZE;
+    input AXI_18_AWVALID;
+    input AXI_18_BREADY;
+    input AXI_18_DFI_LP_PWR_X_REQ;
+    input AXI_18_RREADY;
+    input [255:0] AXI_18_WDATA;
+    input [31:0] AXI_18_WDATA_PARITY;
+    input AXI_18_WLAST;
+    input [31:0] AXI_18_WSTRB;
+    input AXI_18_WVALID;
+    (* invertible_pin = "IS_AXI_19_ACLK_INVERTED" *)
+    input AXI_19_ACLK;
+    input [36:0] AXI_19_ARADDR;
+    input [1:0] AXI_19_ARBURST;
+    (* invertible_pin = "IS_AXI_19_ARESET_N_INVERTED" *)
+    input AXI_19_ARESET_N;
+    input [5:0] AXI_19_ARID;
+    input [3:0] AXI_19_ARLEN;
+    input [2:0] AXI_19_ARSIZE;
+    input AXI_19_ARVALID;
+    input [36:0] AXI_19_AWADDR;
+    input [1:0] AXI_19_AWBURST;
+    input [5:0] AXI_19_AWID;
+    input [3:0] AXI_19_AWLEN;
+    input [2:0] AXI_19_AWSIZE;
+    input AXI_19_AWVALID;
+    input AXI_19_BREADY;
+    input AXI_19_DFI_LP_PWR_X_REQ;
+    input AXI_19_RREADY;
+    input [255:0] AXI_19_WDATA;
+    input [31:0] AXI_19_WDATA_PARITY;
+    input AXI_19_WLAST;
+    input [31:0] AXI_19_WSTRB;
+    input AXI_19_WVALID;
+    (* invertible_pin = "IS_AXI_20_ACLK_INVERTED" *)
+    input AXI_20_ACLK;
+    input [36:0] AXI_20_ARADDR;
+    input [1:0] AXI_20_ARBURST;
+    (* invertible_pin = "IS_AXI_20_ARESET_N_INVERTED" *)
+    input AXI_20_ARESET_N;
+    input [5:0] AXI_20_ARID;
+    input [3:0] AXI_20_ARLEN;
+    input [2:0] AXI_20_ARSIZE;
+    input AXI_20_ARVALID;
+    input [36:0] AXI_20_AWADDR;
+    input [1:0] AXI_20_AWBURST;
+    input [5:0] AXI_20_AWID;
+    input [3:0] AXI_20_AWLEN;
+    input [2:0] AXI_20_AWSIZE;
+    input AXI_20_AWVALID;
+    input AXI_20_BREADY;
+    input AXI_20_DFI_LP_PWR_X_REQ;
+    input AXI_20_RREADY;
+    input [255:0] AXI_20_WDATA;
+    input [31:0] AXI_20_WDATA_PARITY;
+    input AXI_20_WLAST;
+    input [31:0] AXI_20_WSTRB;
+    input AXI_20_WVALID;
+    (* invertible_pin = "IS_AXI_21_ACLK_INVERTED" *)
+    input AXI_21_ACLK;
+    input [36:0] AXI_21_ARADDR;
+    input [1:0] AXI_21_ARBURST;
+    (* invertible_pin = "IS_AXI_21_ARESET_N_INVERTED" *)
+    input AXI_21_ARESET_N;
+    input [5:0] AXI_21_ARID;
+    input [3:0] AXI_21_ARLEN;
+    input [2:0] AXI_21_ARSIZE;
+    input AXI_21_ARVALID;
+    input [36:0] AXI_21_AWADDR;
+    input [1:0] AXI_21_AWBURST;
+    input [5:0] AXI_21_AWID;
+    input [3:0] AXI_21_AWLEN;
+    input [2:0] AXI_21_AWSIZE;
+    input AXI_21_AWVALID;
+    input AXI_21_BREADY;
+    input AXI_21_DFI_LP_PWR_X_REQ;
+    input AXI_21_RREADY;
+    input [255:0] AXI_21_WDATA;
+    input [31:0] AXI_21_WDATA_PARITY;
+    input AXI_21_WLAST;
+    input [31:0] AXI_21_WSTRB;
+    input AXI_21_WVALID;
+    (* invertible_pin = "IS_AXI_22_ACLK_INVERTED" *)
+    input AXI_22_ACLK;
+    input [36:0] AXI_22_ARADDR;
+    input [1:0] AXI_22_ARBURST;
+    (* invertible_pin = "IS_AXI_22_ARESET_N_INVERTED" *)
+    input AXI_22_ARESET_N;
+    input [5:0] AXI_22_ARID;
+    input [3:0] AXI_22_ARLEN;
+    input [2:0] AXI_22_ARSIZE;
+    input AXI_22_ARVALID;
+    input [36:0] AXI_22_AWADDR;
+    input [1:0] AXI_22_AWBURST;
+    input [5:0] AXI_22_AWID;
+    input [3:0] AXI_22_AWLEN;
+    input [2:0] AXI_22_AWSIZE;
+    input AXI_22_AWVALID;
+    input AXI_22_BREADY;
+    input AXI_22_DFI_LP_PWR_X_REQ;
+    input AXI_22_RREADY;
+    input [255:0] AXI_22_WDATA;
+    input [31:0] AXI_22_WDATA_PARITY;
+    input AXI_22_WLAST;
+    input [31:0] AXI_22_WSTRB;
+    input AXI_22_WVALID;
+    (* invertible_pin = "IS_AXI_23_ACLK_INVERTED" *)
+    input AXI_23_ACLK;
+    input [36:0] AXI_23_ARADDR;
+    input [1:0] AXI_23_ARBURST;
+    (* invertible_pin = "IS_AXI_23_ARESET_N_INVERTED" *)
+    input AXI_23_ARESET_N;
+    input [5:0] AXI_23_ARID;
+    input [3:0] AXI_23_ARLEN;
+    input [2:0] AXI_23_ARSIZE;
+    input AXI_23_ARVALID;
+    input [36:0] AXI_23_AWADDR;
+    input [1:0] AXI_23_AWBURST;
+    input [5:0] AXI_23_AWID;
+    input [3:0] AXI_23_AWLEN;
+    input [2:0] AXI_23_AWSIZE;
+    input AXI_23_AWVALID;
+    input AXI_23_BREADY;
+    input AXI_23_DFI_LP_PWR_X_REQ;
+    input AXI_23_RREADY;
+    input [255:0] AXI_23_WDATA;
+    input [31:0] AXI_23_WDATA_PARITY;
+    input AXI_23_WLAST;
+    input [31:0] AXI_23_WSTRB;
+    input AXI_23_WVALID;
+    (* invertible_pin = "IS_AXI_24_ACLK_INVERTED" *)
+    input AXI_24_ACLK;
+    input [36:0] AXI_24_ARADDR;
+    input [1:0] AXI_24_ARBURST;
+    (* invertible_pin = "IS_AXI_24_ARESET_N_INVERTED" *)
+    input AXI_24_ARESET_N;
+    input [5:0] AXI_24_ARID;
+    input [3:0] AXI_24_ARLEN;
+    input [2:0] AXI_24_ARSIZE;
+    input AXI_24_ARVALID;
+    input [36:0] AXI_24_AWADDR;
+    input [1:0] AXI_24_AWBURST;
+    input [5:0] AXI_24_AWID;
+    input [3:0] AXI_24_AWLEN;
+    input [2:0] AXI_24_AWSIZE;
+    input AXI_24_AWVALID;
+    input AXI_24_BREADY;
+    input AXI_24_DFI_LP_PWR_X_REQ;
+    input AXI_24_RREADY;
+    input [255:0] AXI_24_WDATA;
+    input [31:0] AXI_24_WDATA_PARITY;
+    input AXI_24_WLAST;
+    input [31:0] AXI_24_WSTRB;
+    input AXI_24_WVALID;
+    (* invertible_pin = "IS_AXI_25_ACLK_INVERTED" *)
+    input AXI_25_ACLK;
+    input [36:0] AXI_25_ARADDR;
+    input [1:0] AXI_25_ARBURST;
+    (* invertible_pin = "IS_AXI_25_ARESET_N_INVERTED" *)
+    input AXI_25_ARESET_N;
+    input [5:0] AXI_25_ARID;
+    input [3:0] AXI_25_ARLEN;
+    input [2:0] AXI_25_ARSIZE;
+    input AXI_25_ARVALID;
+    input [36:0] AXI_25_AWADDR;
+    input [1:0] AXI_25_AWBURST;
+    input [5:0] AXI_25_AWID;
+    input [3:0] AXI_25_AWLEN;
+    input [2:0] AXI_25_AWSIZE;
+    input AXI_25_AWVALID;
+    input AXI_25_BREADY;
+    input AXI_25_DFI_LP_PWR_X_REQ;
+    input AXI_25_RREADY;
+    input [255:0] AXI_25_WDATA;
+    input [31:0] AXI_25_WDATA_PARITY;
+    input AXI_25_WLAST;
+    input [31:0] AXI_25_WSTRB;
+    input AXI_25_WVALID;
+    (* invertible_pin = "IS_AXI_26_ACLK_INVERTED" *)
+    input AXI_26_ACLK;
+    input [36:0] AXI_26_ARADDR;
+    input [1:0] AXI_26_ARBURST;
+    (* invertible_pin = "IS_AXI_26_ARESET_N_INVERTED" *)
+    input AXI_26_ARESET_N;
+    input [5:0] AXI_26_ARID;
+    input [3:0] AXI_26_ARLEN;
+    input [2:0] AXI_26_ARSIZE;
+    input AXI_26_ARVALID;
+    input [36:0] AXI_26_AWADDR;
+    input [1:0] AXI_26_AWBURST;
+    input [5:0] AXI_26_AWID;
+    input [3:0] AXI_26_AWLEN;
+    input [2:0] AXI_26_AWSIZE;
+    input AXI_26_AWVALID;
+    input AXI_26_BREADY;
+    input AXI_26_DFI_LP_PWR_X_REQ;
+    input AXI_26_RREADY;
+    input [255:0] AXI_26_WDATA;
+    input [31:0] AXI_26_WDATA_PARITY;
+    input AXI_26_WLAST;
+    input [31:0] AXI_26_WSTRB;
+    input AXI_26_WVALID;
+    (* invertible_pin = "IS_AXI_27_ACLK_INVERTED" *)
+    input AXI_27_ACLK;
+    input [36:0] AXI_27_ARADDR;
+    input [1:0] AXI_27_ARBURST;
+    (* invertible_pin = "IS_AXI_27_ARESET_N_INVERTED" *)
+    input AXI_27_ARESET_N;
+    input [5:0] AXI_27_ARID;
+    input [3:0] AXI_27_ARLEN;
+    input [2:0] AXI_27_ARSIZE;
+    input AXI_27_ARVALID;
+    input [36:0] AXI_27_AWADDR;
+    input [1:0] AXI_27_AWBURST;
+    input [5:0] AXI_27_AWID;
+    input [3:0] AXI_27_AWLEN;
+    input [2:0] AXI_27_AWSIZE;
+    input AXI_27_AWVALID;
+    input AXI_27_BREADY;
+    input AXI_27_DFI_LP_PWR_X_REQ;
+    input AXI_27_RREADY;
+    input [255:0] AXI_27_WDATA;
+    input [31:0] AXI_27_WDATA_PARITY;
+    input AXI_27_WLAST;
+    input [31:0] AXI_27_WSTRB;
+    input AXI_27_WVALID;
+    (* invertible_pin = "IS_AXI_28_ACLK_INVERTED" *)
+    input AXI_28_ACLK;
+    input [36:0] AXI_28_ARADDR;
+    input [1:0] AXI_28_ARBURST;
+    (* invertible_pin = "IS_AXI_28_ARESET_N_INVERTED" *)
+    input AXI_28_ARESET_N;
+    input [5:0] AXI_28_ARID;
+    input [3:0] AXI_28_ARLEN;
+    input [2:0] AXI_28_ARSIZE;
+    input AXI_28_ARVALID;
+    input [36:0] AXI_28_AWADDR;
+    input [1:0] AXI_28_AWBURST;
+    input [5:0] AXI_28_AWID;
+    input [3:0] AXI_28_AWLEN;
+    input [2:0] AXI_28_AWSIZE;
+    input AXI_28_AWVALID;
+    input AXI_28_BREADY;
+    input AXI_28_DFI_LP_PWR_X_REQ;
+    input AXI_28_RREADY;
+    input [255:0] AXI_28_WDATA;
+    input [31:0] AXI_28_WDATA_PARITY;
+    input AXI_28_WLAST;
+    input [31:0] AXI_28_WSTRB;
+    input AXI_28_WVALID;
+    (* invertible_pin = "IS_AXI_29_ACLK_INVERTED" *)
+    input AXI_29_ACLK;
+    input [36:0] AXI_29_ARADDR;
+    input [1:0] AXI_29_ARBURST;
+    (* invertible_pin = "IS_AXI_29_ARESET_N_INVERTED" *)
+    input AXI_29_ARESET_N;
+    input [5:0] AXI_29_ARID;
+    input [3:0] AXI_29_ARLEN;
+    input [2:0] AXI_29_ARSIZE;
+    input AXI_29_ARVALID;
+    input [36:0] AXI_29_AWADDR;
+    input [1:0] AXI_29_AWBURST;
+    input [5:0] AXI_29_AWID;
+    input [3:0] AXI_29_AWLEN;
+    input [2:0] AXI_29_AWSIZE;
+    input AXI_29_AWVALID;
+    input AXI_29_BREADY;
+    input AXI_29_DFI_LP_PWR_X_REQ;
+    input AXI_29_RREADY;
+    input [255:0] AXI_29_WDATA;
+    input [31:0] AXI_29_WDATA_PARITY;
+    input AXI_29_WLAST;
+    input [31:0] AXI_29_WSTRB;
+    input AXI_29_WVALID;
+    (* invertible_pin = "IS_AXI_30_ACLK_INVERTED" *)
+    input AXI_30_ACLK;
+    input [36:0] AXI_30_ARADDR;
+    input [1:0] AXI_30_ARBURST;
+    (* invertible_pin = "IS_AXI_30_ARESET_N_INVERTED" *)
+    input AXI_30_ARESET_N;
+    input [5:0] AXI_30_ARID;
+    input [3:0] AXI_30_ARLEN;
+    input [2:0] AXI_30_ARSIZE;
+    input AXI_30_ARVALID;
+    input [36:0] AXI_30_AWADDR;
+    input [1:0] AXI_30_AWBURST;
+    input [5:0] AXI_30_AWID;
+    input [3:0] AXI_30_AWLEN;
+    input [2:0] AXI_30_AWSIZE;
+    input AXI_30_AWVALID;
+    input AXI_30_BREADY;
+    input AXI_30_DFI_LP_PWR_X_REQ;
+    input AXI_30_RREADY;
+    input [255:0] AXI_30_WDATA;
+    input [31:0] AXI_30_WDATA_PARITY;
+    input AXI_30_WLAST;
+    input [31:0] AXI_30_WSTRB;
+    input AXI_30_WVALID;
+    (* invertible_pin = "IS_AXI_31_ACLK_INVERTED" *)
+    input AXI_31_ACLK;
+    input [36:0] AXI_31_ARADDR;
+    input [1:0] AXI_31_ARBURST;
+    (* invertible_pin = "IS_AXI_31_ARESET_N_INVERTED" *)
+    input AXI_31_ARESET_N;
+    input [5:0] AXI_31_ARID;
+    input [3:0] AXI_31_ARLEN;
+    input [2:0] AXI_31_ARSIZE;
+    input AXI_31_ARVALID;
+    input [36:0] AXI_31_AWADDR;
+    input [1:0] AXI_31_AWBURST;
+    input [5:0] AXI_31_AWID;
+    input [3:0] AXI_31_AWLEN;
+    input [2:0] AXI_31_AWSIZE;
+    input AXI_31_AWVALID;
+    input AXI_31_BREADY;
+    input AXI_31_DFI_LP_PWR_X_REQ;
+    input AXI_31_RREADY;
+    input [255:0] AXI_31_WDATA;
+    input [31:0] AXI_31_WDATA_PARITY;
+    input AXI_31_WLAST;
+    input [31:0] AXI_31_WSTRB;
+    input AXI_31_WVALID;
+    input BSCAN_DRCK_0;
+    input BSCAN_DRCK_1;
+    input BSCAN_TCK_0;
+    input BSCAN_TCK_1;
+    input HBM_REF_CLK_0;
+    input HBM_REF_CLK_1;
+    input MBIST_EN_00;
+    input MBIST_EN_01;
+    input MBIST_EN_02;
+    input MBIST_EN_03;
+    input MBIST_EN_04;
+    input MBIST_EN_05;
+    input MBIST_EN_06;
+    input MBIST_EN_07;
+    input MBIST_EN_08;
+    input MBIST_EN_09;
+    input MBIST_EN_10;
+    input MBIST_EN_11;
+    input MBIST_EN_12;
+    input MBIST_EN_13;
+    input MBIST_EN_14;
+    input MBIST_EN_15;
+endmodule
+
+module PPC405_ADV (...);
+    parameter in_delay=100;
+    parameter out_delay=100;
+    output APUFCMDECODED;
+    output APUFCMDECUDIVALID;
+    output APUFCMENDIAN;
+    output APUFCMFLUSH;
+    output APUFCMINSTRVALID;
+    output APUFCMLOADDVALID;
+    output APUFCMOPERANDVALID;
+    output APUFCMWRITEBACKOK;
+    output APUFCMXERCA;
+    output C405CPMCORESLEEPREQ;
+    output C405CPMMSRCE;
+    output C405CPMMSREE;
+    output C405CPMTIMERIRQ;
+    output C405CPMTIMERRESETREQ;
+    output C405DBGLOADDATAONAPUDBUS;
+    output C405DBGMSRWE;
+    output C405DBGSTOPACK;
+    output C405DBGWBCOMPLETE;
+    output C405DBGWBFULL;
+    output C405JTGCAPTUREDR;
+    output C405JTGEXTEST;
+    output C405JTGPGMOUT;
+    output C405JTGSHIFTDR;
+    output C405JTGTDO;
+    output C405JTGTDOEN;
+    output C405JTGUPDATEDR;
+    output C405PLBDCUABORT;
+    output C405PLBDCUCACHEABLE;
+    output C405PLBDCUGUARDED;
+    output C405PLBDCUREQUEST;
+    output C405PLBDCURNW;
+    output C405PLBDCUSIZE2;
+    output C405PLBDCUU0ATTR;
+    output C405PLBDCUWRITETHRU;
+    output C405PLBICUABORT;
+    output C405PLBICUCACHEABLE;
+    output C405PLBICUREQUEST;
+    output C405PLBICUU0ATTR;
+    output C405RSTCHIPRESETREQ;
+    output C405RSTCORERESETREQ;
+    output C405RSTSYSRESETREQ;
+    output C405TRCCYCLE;
+    output C405TRCTRIGGEREVENTOUT;
+    output C405XXXMACHINECHECK;
+    output DCREMACCLK;
+    output DCREMACENABLER;
+    output DCREMACREAD;
+    output DCREMACWRITE;
+    output DSOCMBRAMEN;
+    output DSOCMBUSY;
+    output DSOCMRDADDRVALID;
+    output DSOCMWRADDRVALID;
+    output EXTDCRREAD;
+    output EXTDCRWRITE;
+    output ISOCMBRAMEN;
+    output ISOCMBRAMEVENWRITEEN;
+    output ISOCMBRAMODDWRITEEN;
+    output ISOCMDCRBRAMEVENEN;
+    output ISOCMDCRBRAMODDEN;
+    output ISOCMDCRBRAMRDSELECT;
+    output [0:10] C405TRCTRIGGEREVENTTYPE;
+    output [0:1] C405PLBDCUPRIORITY;
+    output [0:1] C405PLBICUPRIORITY;
+    output [0:1] C405TRCEVENEXECUTIONSTATUS;
+    output [0:1] C405TRCODDEXECUTIONSTATUS;
+    output [0:29] C405DBGWBIAR;
+    output [0:29] C405PLBICUABUS;
+    output [0:2] APUFCMDECUDI;
+    output [0:31] APUFCMINSTRUCTION;
+    output [0:31] APUFCMLOADDATA;
+    output [0:31] APUFCMRADATA;
+    output [0:31] APUFCMRBDATA;
+    output [0:31] C405PLBDCUABUS;
+    output [0:31] DCREMACDBUS;
+    output [0:31] DSOCMBRAMWRDBUS;
+    output [0:31] EXTDCRDBUSOUT;
+    output [0:31] ISOCMBRAMWRDBUS;
+    output [0:3] APUFCMLOADBYTEEN;
+    output [0:3] C405TRCTRACESTATUS;
+    output [0:3] DSOCMBRAMBYTEWRITE;
+    output [0:63] C405PLBDCUWRDBUS;
+    output [0:7] C405PLBDCUBE;
+    output [0:9] EXTDCRABUS;
+    output [2:3] C405PLBICUSIZE;
+    output [8:28] ISOCMBRAMRDABUS;
+    output [8:28] ISOCMBRAMWRABUS;
+    output [8:29] DSOCMBRAMABUS;
+    output [8:9] DCREMACABUS;
+    input BRAMDSOCMCLK;
+    input BRAMISOCMCLK;
+    input CPMC405CLOCK;
+    input CPMC405CORECLKINACTIVE;
+    input CPMC405CPUCLKEN;
+    input CPMC405JTAGCLKEN;
+    input CPMC405SYNCBYPASS;
+    input CPMC405TIMERCLKEN;
+    input CPMC405TIMERTICK;
+    input CPMDCRCLK;
+    input CPMFCMCLK;
+    input DBGC405DEBUGHALT;
+    input DBGC405EXTBUSHOLDACK;
+    input DBGC405UNCONDDEBUGEVENT;
+    input DSOCMRWCOMPLETE;
+    input EICC405CRITINPUTIRQ;
+    input EICC405EXTINPUTIRQ;
+    input EMACDCRACK;
+    input EXTDCRACK;
+    input FCMAPUDCDCREN;
+    input FCMAPUDCDFORCEALIGN;
+    input FCMAPUDCDFORCEBESTEERING;
+    input FCMAPUDCDFPUOP;
+    input FCMAPUDCDGPRWRITE;
+    input FCMAPUDCDLDSTBYTE;
+    input FCMAPUDCDLDSTDW;
+    input FCMAPUDCDLDSTHW;
+    input FCMAPUDCDLDSTQW;
+    input FCMAPUDCDLDSTWD;
+    input FCMAPUDCDLOAD;
+    input FCMAPUDCDPRIVOP;
+    input FCMAPUDCDRAEN;
+    input FCMAPUDCDRBEN;
+    input FCMAPUDCDSTORE;
+    input FCMAPUDCDTRAPBE;
+    input FCMAPUDCDTRAPLE;
+    input FCMAPUDCDUPDATE;
+    input FCMAPUDCDXERCAEN;
+    input FCMAPUDCDXEROVEN;
+    input FCMAPUDECODEBUSY;
+    input FCMAPUDONE;
+    input FCMAPUEXCEPTION;
+    input FCMAPUEXEBLOCKINGMCO;
+    input FCMAPUEXENONBLOCKINGMCO;
+    input FCMAPUINSTRACK;
+    input FCMAPULOADWAIT;
+    input FCMAPURESULTVALID;
+    input FCMAPUSLEEPNOTREADY;
+    input FCMAPUXERCA;
+    input FCMAPUXEROV;
+    input JTGC405BNDSCANTDO;
+    input JTGC405TCK;
+    input JTGC405TDI;
+    input JTGC405TMS;
+    input JTGC405TRSTNEG;
+    input MCBCPUCLKEN;
+    input MCBJTAGEN;
+    input MCBTIMEREN;
+    input MCPPCRST;
+    input PLBC405DCUADDRACK;
+    input PLBC405DCUBUSY;
+    input PLBC405DCUERR;
+    input PLBC405DCURDDACK;
+    input PLBC405DCUSSIZE1;
+    input PLBC405DCUWRDACK;
+    input PLBC405ICUADDRACK;
+    input PLBC405ICUBUSY;
+    input PLBC405ICUERR;
+    input PLBC405ICURDDACK;
+    input PLBC405ICUSSIZE1;
+    input PLBCLK;
+    input RSTC405RESETCHIP;
+    input RSTC405RESETCORE;
+    input RSTC405RESETSYS;
+    input TIEC405DETERMINISTICMULT;
+    input TIEC405DISOPERANDFWD;
+    input TIEC405MMUEN;
+    input TIEPVRBIT10;
+    input TIEPVRBIT11;
+    input TIEPVRBIT28;
+    input TIEPVRBIT29;
+    input TIEPVRBIT30;
+    input TIEPVRBIT31;
+    input TIEPVRBIT8;
+    input TIEPVRBIT9;
+    input TRCC405TRACEDISABLE;
+    input TRCC405TRIGGEREVENTIN;
+    input [0:15] TIEAPUCONTROL;
+    input [0:23] TIEAPUUDI1;
+    input [0:23] TIEAPUUDI2;
+    input [0:23] TIEAPUUDI3;
+    input [0:23] TIEAPUUDI4;
+    input [0:23] TIEAPUUDI5;
+    input [0:23] TIEAPUUDI6;
+    input [0:23] TIEAPUUDI7;
+    input [0:23] TIEAPUUDI8;
+    input [0:2] FCMAPUEXECRFIELD;
+    input [0:31] BRAMDSOCMRDDBUS;
+    input [0:31] BRAMISOCMDCRRDDBUS;
+    input [0:31] EMACDCRDBUS;
+    input [0:31] EXTDCRDBUSIN;
+    input [0:31] FCMAPURESULT;
+    input [0:3] FCMAPUCR;
+    input [0:5] TIEDCRADDR;
+    input [0:63] BRAMISOCMRDDBUS;
+    input [0:63] PLBC405DCURDDBUS;
+    input [0:63] PLBC405ICURDDBUS;
+    input [0:7] DSARCVALUE;
+    input [0:7] DSCNTLVALUE;
+    input [0:7] ISARCVALUE;
+    input [0:7] ISCNTLVALUE;
+    input [1:3] PLBC405DCURDWDADDR;
+    input [1:3] PLBC405ICURDWDADDR;
+endmodule
+
+module PPC440 (...);
+    parameter CLOCK_DELAY = "FALSE";
+    parameter DCR_AUTOLOCK_ENABLE = "TRUE";
+    parameter PPCDM_ASYNCMODE = "FALSE";
+    parameter PPCDS_ASYNCMODE = "FALSE";
+    parameter PPCS0_WIDTH_128N64 = "TRUE";
+    parameter PPCS1_WIDTH_128N64 = "TRUE";
+    parameter [0:16] APU_CONTROL = 17'h02000;
+    parameter [0:23] APU_UDI0 = 24'h000000;
+    parameter [0:23] APU_UDI1 = 24'h000000;
+    parameter [0:23] APU_UDI10 = 24'h000000;
+    parameter [0:23] APU_UDI11 = 24'h000000;
+    parameter [0:23] APU_UDI12 = 24'h000000;
+    parameter [0:23] APU_UDI13 = 24'h000000;
+    parameter [0:23] APU_UDI14 = 24'h000000;
+    parameter [0:23] APU_UDI15 = 24'h000000;
+    parameter [0:23] APU_UDI2 = 24'h000000;
+    parameter [0:23] APU_UDI3 = 24'h000000;
+    parameter [0:23] APU_UDI4 = 24'h000000;
+    parameter [0:23] APU_UDI5 = 24'h000000;
+    parameter [0:23] APU_UDI6 = 24'h000000;
+    parameter [0:23] APU_UDI7 = 24'h000000;
+    parameter [0:23] APU_UDI8 = 24'h000000;
+    parameter [0:23] APU_UDI9 = 24'h000000;
+    parameter [0:31] DMA0_RXCHANNELCTRL = 32'h01010000;
+    parameter [0:31] DMA0_TXCHANNELCTRL = 32'h01010000;
+    parameter [0:31] DMA1_RXCHANNELCTRL = 32'h01010000;
+    parameter [0:31] DMA1_TXCHANNELCTRL = 32'h01010000;
+    parameter [0:31] DMA2_RXCHANNELCTRL = 32'h01010000;
+    parameter [0:31] DMA2_TXCHANNELCTRL = 32'h01010000;
+    parameter [0:31] DMA3_RXCHANNELCTRL = 32'h01010000;
+    parameter [0:31] DMA3_TXCHANNELCTRL = 32'h01010000;
+    parameter [0:31] INTERCONNECT_IMASK = 32'hFFFFFFFF;
+    parameter [0:31] INTERCONNECT_TMPL_SEL = 32'h3FFFFFFF;
+    parameter [0:31] MI_ARBCONFIG = 32'h00432010;
+    parameter [0:31] MI_BANKCONFLICT_MASK = 32'h00000000;
+    parameter [0:31] MI_CONTROL = 32'h0000008F;
+    parameter [0:31] MI_ROWCONFLICT_MASK = 32'h00000000;
+    parameter [0:31] PPCM_ARBCONFIG = 32'h00432010;
+    parameter [0:31] PPCM_CONTROL = 32'h8000019F;
+    parameter [0:31] PPCM_COUNTER = 32'h00000500;
+    parameter [0:31] PPCS0_ADDRMAP_TMPL0 = 32'hFFFFFFFF;
+    parameter [0:31] PPCS0_ADDRMAP_TMPL1 = 32'hFFFFFFFF;
+    parameter [0:31] PPCS0_ADDRMAP_TMPL2 = 32'hFFFFFFFF;
+    parameter [0:31] PPCS0_ADDRMAP_TMPL3 = 32'hFFFFFFFF;
+    parameter [0:31] PPCS0_CONTROL = 32'h8033336C;
+    parameter [0:31] PPCS1_ADDRMAP_TMPL0 = 32'hFFFFFFFF;
+    parameter [0:31] PPCS1_ADDRMAP_TMPL1 = 32'hFFFFFFFF;
+    parameter [0:31] PPCS1_ADDRMAP_TMPL2 = 32'hFFFFFFFF;
+    parameter [0:31] PPCS1_ADDRMAP_TMPL3 = 32'hFFFFFFFF;
+    parameter [0:31] PPCS1_CONTROL = 32'h8033336C;
+    parameter [0:31] XBAR_ADDRMAP_TMPL0 = 32'hFFFF0000;
+    parameter [0:31] XBAR_ADDRMAP_TMPL1 = 32'h00000000;
+    parameter [0:31] XBAR_ADDRMAP_TMPL2 = 32'h00000000;
+    parameter [0:31] XBAR_ADDRMAP_TMPL3 = 32'h00000000;
+    parameter [0:7] DMA0_CONTROL = 8'h00;
+    parameter [0:7] DMA1_CONTROL = 8'h00;
+    parameter [0:7] DMA2_CONTROL = 8'h00;
+    parameter [0:7] DMA3_CONTROL = 8'h00;
+    parameter [0:9] DMA0_RXIRQTIMER = 10'h3FF;
+    parameter [0:9] DMA0_TXIRQTIMER = 10'h3FF;
+    parameter [0:9] DMA1_RXIRQTIMER = 10'h3FF;
+    parameter [0:9] DMA1_TXIRQTIMER = 10'h3FF;
+    parameter [0:9] DMA2_RXIRQTIMER = 10'h3FF;
+    parameter [0:9] DMA2_TXIRQTIMER = 10'h3FF;
+    parameter [0:9] DMA3_RXIRQTIMER = 10'h3FF;
+    parameter [0:9] DMA3_TXIRQTIMER = 10'h3FF;
+    output APUFCMDECFPUOP;
+    output APUFCMDECLOAD;
+    output APUFCMDECNONAUTON;
+    output APUFCMDECSTORE;
+    output APUFCMDECUDIVALID;
+    output APUFCMENDIAN;
+    output APUFCMFLUSH;
+    output APUFCMINSTRVALID;
+    output APUFCMLOADDVALID;
+    output APUFCMMSRFE0;
+    output APUFCMMSRFE1;
+    output APUFCMNEXTINSTRREADY;
+    output APUFCMOPERANDVALID;
+    output APUFCMWRITEBACKOK;
+    output C440CPMCORESLEEPREQ;
+    output C440CPMDECIRPTREQ;
+    output C440CPMFITIRPTREQ;
+    output C440CPMMSRCE;
+    output C440CPMMSREE;
+    output C440CPMTIMERRESETREQ;
+    output C440CPMWDIRPTREQ;
+    output C440JTGTDO;
+    output C440JTGTDOEN;
+    output C440MACHINECHECK;
+    output C440RSTCHIPRESETREQ;
+    output C440RSTCORERESETREQ;
+    output C440RSTSYSTEMRESETREQ;
+    output C440TRCCYCLE;
+    output C440TRCTRIGGEREVENTOUT;
+    output DMA0LLRSTENGINEACK;
+    output DMA0LLRXDSTRDYN;
+    output DMA0LLTXEOFN;
+    output DMA0LLTXEOPN;
+    output DMA0LLTXSOFN;
+    output DMA0LLTXSOPN;
+    output DMA0LLTXSRCRDYN;
+    output DMA0RXIRQ;
+    output DMA0TXIRQ;
+    output DMA1LLRSTENGINEACK;
+    output DMA1LLRXDSTRDYN;
+    output DMA1LLTXEOFN;
+    output DMA1LLTXEOPN;
+    output DMA1LLTXSOFN;
+    output DMA1LLTXSOPN;
+    output DMA1LLTXSRCRDYN;
+    output DMA1RXIRQ;
+    output DMA1TXIRQ;
+    output DMA2LLRSTENGINEACK;
+    output DMA2LLRXDSTRDYN;
+    output DMA2LLTXEOFN;
+    output DMA2LLTXEOPN;
+    output DMA2LLTXSOFN;
+    output DMA2LLTXSOPN;
+    output DMA2LLTXSRCRDYN;
+    output DMA2RXIRQ;
+    output DMA2TXIRQ;
+    output DMA3LLRSTENGINEACK;
+    output DMA3LLRXDSTRDYN;
+    output DMA3LLTXEOFN;
+    output DMA3LLTXEOPN;
+    output DMA3LLTXSOFN;
+    output DMA3LLTXSOPN;
+    output DMA3LLTXSRCRDYN;
+    output DMA3RXIRQ;
+    output DMA3TXIRQ;
+    output MIMCADDRESSVALID;
+    output MIMCBANKCONFLICT;
+    output MIMCREADNOTWRITE;
+    output MIMCROWCONFLICT;
+    output MIMCWRITEDATAVALID;
+    output PPCCPMINTERCONNECTBUSY;
+    output PPCDMDCRREAD;
+    output PPCDMDCRWRITE;
+    output PPCDSDCRACK;
+    output PPCDSDCRTIMEOUTWAIT;
+    output PPCEICINTERCONNECTIRQ;
+    output PPCMPLBABORT;
+    output PPCMPLBBUSLOCK;
+    output PPCMPLBLOCKERR;
+    output PPCMPLBRDBURST;
+    output PPCMPLBREQUEST;
+    output PPCMPLBRNW;
+    output PPCMPLBWRBURST;
+    output PPCS0PLBADDRACK;
+    output PPCS0PLBRDBTERM;
+    output PPCS0PLBRDCOMP;
+    output PPCS0PLBRDDACK;
+    output PPCS0PLBREARBITRATE;
+    output PPCS0PLBWAIT;
+    output PPCS0PLBWRBTERM;
+    output PPCS0PLBWRCOMP;
+    output PPCS0PLBWRDACK;
+    output PPCS1PLBADDRACK;
+    output PPCS1PLBRDBTERM;
+    output PPCS1PLBRDCOMP;
+    output PPCS1PLBRDDACK;
+    output PPCS1PLBREARBITRATE;
+    output PPCS1PLBWAIT;
+    output PPCS1PLBWRBTERM;
+    output PPCS1PLBWRCOMP;
+    output PPCS1PLBWRDACK;
+    output [0:127] APUFCMLOADDATA;
+    output [0:127] MIMCWRITEDATA;
+    output [0:127] PPCMPLBWRDBUS;
+    output [0:127] PPCS0PLBRDDBUS;
+    output [0:127] PPCS1PLBRDDBUS;
+    output [0:13] C440TRCTRIGGEREVENTTYPE;
+    output [0:15] MIMCBYTEENABLE;
+    output [0:15] PPCMPLBBE;
+    output [0:15] PPCMPLBTATTRIBUTE;
+    output [0:1] PPCMPLBPRIORITY;
+    output [0:1] PPCS0PLBSSIZE;
+    output [0:1] PPCS1PLBSSIZE;
+    output [0:2] APUFCMDECLDSTXFERSIZE;
+    output [0:2] C440TRCBRANCHSTATUS;
+    output [0:2] PPCMPLBTYPE;
+    output [0:31] APUFCMINSTRUCTION;
+    output [0:31] APUFCMRADATA;
+    output [0:31] APUFCMRBDATA;
+    output [0:31] DMA0LLTXD;
+    output [0:31] DMA1LLTXD;
+    output [0:31] DMA2LLTXD;
+    output [0:31] DMA3LLTXD;
+    output [0:31] PPCDMDCRDBUSOUT;
+    output [0:31] PPCDSDCRDBUSIN;
+    output [0:31] PPCMPLBABUS;
+    output [0:35] MIMCADDRESS;
+    output [0:3] APUFCMDECUDI;
+    output [0:3] APUFCMLOADBYTEADDR;
+    output [0:3] DMA0LLTXREM;
+    output [0:3] DMA1LLTXREM;
+    output [0:3] DMA2LLTXREM;
+    output [0:3] DMA3LLTXREM;
+    output [0:3] PPCMPLBSIZE;
+    output [0:3] PPCS0PLBMBUSY;
+    output [0:3] PPCS0PLBMIRQ;
+    output [0:3] PPCS0PLBMRDERR;
+    output [0:3] PPCS0PLBMWRERR;
+    output [0:3] PPCS0PLBRDWDADDR;
+    output [0:3] PPCS1PLBMBUSY;
+    output [0:3] PPCS1PLBMIRQ;
+    output [0:3] PPCS1PLBMRDERR;
+    output [0:3] PPCS1PLBMWRERR;
+    output [0:3] PPCS1PLBRDWDADDR;
+    output [0:4] C440TRCEXECUTIONSTATUS;
+    output [0:6] C440TRCTRACESTATUS;
+    output [0:7] C440DBGSYSTEMCONTROL;
+    output [0:9] PPCDMDCRABUS;
+    output [20:21] PPCDMDCRUABUS;
+    output [28:31] PPCMPLBUABUS;
+    input CPMC440CLK;
+    input CPMC440CLKEN;
+    input CPMC440CORECLOCKINACTIVE;
+    input CPMC440TIMERCLOCK;
+    input CPMDCRCLK;
+    input CPMDMA0LLCLK;
+    input CPMDMA1LLCLK;
+    input CPMDMA2LLCLK;
+    input CPMDMA3LLCLK;
+    input CPMFCMCLK;
+    input CPMINTERCONNECTCLK;
+    input CPMINTERCONNECTCLKEN;
+    input CPMINTERCONNECTCLKNTO1;
+    input CPMMCCLK;
+    input CPMPPCMPLBCLK;
+    input CPMPPCS0PLBCLK;
+    input CPMPPCS1PLBCLK;
+    input DBGC440DEBUGHALT;
+    input DBGC440UNCONDDEBUGEVENT;
+    input DCRPPCDMACK;
+    input DCRPPCDMTIMEOUTWAIT;
+    input DCRPPCDSREAD;
+    input DCRPPCDSWRITE;
+    input EICC440CRITIRQ;
+    input EICC440EXTIRQ;
+    input FCMAPUCONFIRMINSTR;
+    input FCMAPUDONE;
+    input FCMAPUEXCEPTION;
+    input FCMAPUFPSCRFEX;
+    input FCMAPURESULTVALID;
+    input FCMAPUSLEEPNOTREADY;
+    input JTGC440TCK;
+    input JTGC440TDI;
+    input JTGC440TMS;
+    input JTGC440TRSTNEG;
+    input LLDMA0RSTENGINEREQ;
+    input LLDMA0RXEOFN;
+    input LLDMA0RXEOPN;
+    input LLDMA0RXSOFN;
+    input LLDMA0RXSOPN;
+    input LLDMA0RXSRCRDYN;
+    input LLDMA0TXDSTRDYN;
+    input LLDMA1RSTENGINEREQ;
+    input LLDMA1RXEOFN;
+    input LLDMA1RXEOPN;
+    input LLDMA1RXSOFN;
+    input LLDMA1RXSOPN;
+    input LLDMA1RXSRCRDYN;
+    input LLDMA1TXDSTRDYN;
+    input LLDMA2RSTENGINEREQ;
+    input LLDMA2RXEOFN;
+    input LLDMA2RXEOPN;
+    input LLDMA2RXSOFN;
+    input LLDMA2RXSOPN;
+    input LLDMA2RXSRCRDYN;
+    input LLDMA2TXDSTRDYN;
+    input LLDMA3RSTENGINEREQ;
+    input LLDMA3RXEOFN;
+    input LLDMA3RXEOPN;
+    input LLDMA3RXSOFN;
+    input LLDMA3RXSOPN;
+    input LLDMA3RXSRCRDYN;
+    input LLDMA3TXDSTRDYN;
+    input MCMIADDRREADYTOACCEPT;
+    input MCMIREADDATAERR;
+    input MCMIREADDATAVALID;
+    input PLBPPCMADDRACK;
+    input PLBPPCMMBUSY;
+    input PLBPPCMMIRQ;
+    input PLBPPCMMRDERR;
+    input PLBPPCMMWRERR;
+    input PLBPPCMRDBTERM;
+    input PLBPPCMRDDACK;
+    input PLBPPCMRDPENDREQ;
+    input PLBPPCMREARBITRATE;
+    input PLBPPCMTIMEOUT;
+    input PLBPPCMWRBTERM;
+    input PLBPPCMWRDACK;
+    input PLBPPCMWRPENDREQ;
+    input PLBPPCS0ABORT;
+    input PLBPPCS0BUSLOCK;
+    input PLBPPCS0LOCKERR;
+    input PLBPPCS0PAVALID;
+    input PLBPPCS0RDBURST;
+    input PLBPPCS0RDPENDREQ;
+    input PLBPPCS0RDPRIM;
+    input PLBPPCS0RNW;
+    input PLBPPCS0SAVALID;
+    input PLBPPCS0WRBURST;
+    input PLBPPCS0WRPENDREQ;
+    input PLBPPCS0WRPRIM;
+    input PLBPPCS1ABORT;
+    input PLBPPCS1BUSLOCK;
+    input PLBPPCS1LOCKERR;
+    input PLBPPCS1PAVALID;
+    input PLBPPCS1RDBURST;
+    input PLBPPCS1RDPENDREQ;
+    input PLBPPCS1RDPRIM;
+    input PLBPPCS1RNW;
+    input PLBPPCS1SAVALID;
+    input PLBPPCS1WRBURST;
+    input PLBPPCS1WRPENDREQ;
+    input PLBPPCS1WRPRIM;
+    input RSTC440RESETCHIP;
+    input RSTC440RESETCORE;
+    input RSTC440RESETSYSTEM;
+    input TIEC440ENDIANRESET;
+    input TRCC440TRACEDISABLE;
+    input TRCC440TRIGGEREVENTIN;
+    input [0:127] FCMAPUSTOREDATA;
+    input [0:127] MCMIREADDATA;
+    input [0:127] PLBPPCMRDDBUS;
+    input [0:127] PLBPPCS0WRDBUS;
+    input [0:127] PLBPPCS1WRDBUS;
+    input [0:15] PLBPPCS0BE;
+    input [0:15] PLBPPCS0TATTRIBUTE;
+    input [0:15] PLBPPCS1BE;
+    input [0:15] PLBPPCS1TATTRIBUTE;
+    input [0:1] PLBPPCMRDPENDPRI;
+    input [0:1] PLBPPCMREQPRI;
+    input [0:1] PLBPPCMSSIZE;
+    input [0:1] PLBPPCMWRPENDPRI;
+    input [0:1] PLBPPCS0MASTERID;
+    input [0:1] PLBPPCS0MSIZE;
+    input [0:1] PLBPPCS0RDPENDPRI;
+    input [0:1] PLBPPCS0REQPRI;
+    input [0:1] PLBPPCS0WRPENDPRI;
+    input [0:1] PLBPPCS1MASTERID;
+    input [0:1] PLBPPCS1MSIZE;
+    input [0:1] PLBPPCS1RDPENDPRI;
+    input [0:1] PLBPPCS1REQPRI;
+    input [0:1] PLBPPCS1WRPENDPRI;
+    input [0:1] TIEC440DCURDLDCACHEPLBPRIO;
+    input [0:1] TIEC440DCURDNONCACHEPLBPRIO;
+    input [0:1] TIEC440DCURDTOUCHPLBPRIO;
+    input [0:1] TIEC440DCURDURGENTPLBPRIO;
+    input [0:1] TIEC440DCUWRFLUSHPLBPRIO;
+    input [0:1] TIEC440DCUWRSTOREPLBPRIO;
+    input [0:1] TIEC440DCUWRURGENTPLBPRIO;
+    input [0:1] TIEC440ICURDFETCHPLBPRIO;
+    input [0:1] TIEC440ICURDSPECPLBPRIO;
+    input [0:1] TIEC440ICURDTOUCHPLBPRIO;
+    input [0:1] TIEDCRBASEADDR;
+    input [0:2] PLBPPCS0TYPE;
+    input [0:2] PLBPPCS1TYPE;
+    input [0:31] DCRPPCDMDBUSIN;
+    input [0:31] DCRPPCDSDBUSOUT;
+    input [0:31] FCMAPURESULT;
+    input [0:31] LLDMA0RXD;
+    input [0:31] LLDMA1RXD;
+    input [0:31] LLDMA2RXD;
+    input [0:31] LLDMA3RXD;
+    input [0:31] PLBPPCS0ABUS;
+    input [0:31] PLBPPCS1ABUS;
+    input [0:3] FCMAPUCR;
+    input [0:3] LLDMA0RXREM;
+    input [0:3] LLDMA1RXREM;
+    input [0:3] LLDMA2RXREM;
+    input [0:3] LLDMA3RXREM;
+    input [0:3] PLBPPCMRDWDADDR;
+    input [0:3] PLBPPCS0SIZE;
+    input [0:3] PLBPPCS1SIZE;
+    input [0:3] TIEC440ERPNRESET;
+    input [0:3] TIEC440USERRESET;
+    input [0:4] DBGC440SYSTEMSTATUS;
+    input [0:9] DCRPPCDSABUS;
+    input [28:31] PLBPPCS0UABUS;
+    input [28:31] PLBPPCS1UABUS;
+    input [28:31] TIEC440PIR;
+    input [28:31] TIEC440PVR;
+endmodule
+
 (* keep *)
 module PS7 (...);
     output DMA0DAVALID;
@@ -28088,3 +33144,297 @@ module ILKNE4 (...);
     input TX_SOPIN3;
 endmodule
 
+(* keep *)
+module VCU (...);
+    parameter integer CORECLKREQ = 667;
+    parameter integer DECHORRESOLUTION = 3840;
+    parameter DECODERCHROMAFORMAT = "4_2_2";
+    parameter DECODERCODING = "H.265";
+    parameter integer DECODERCOLORDEPTH = 10;
+    parameter integer DECODERNUMCORES = 2;
+    parameter integer DECVERTRESOLUTION = 2160;
+    parameter ENABLEDECODER = "TRUE";
+    parameter ENABLEENCODER = "TRUE";
+    parameter integer ENCHORRESOLUTION = 3840;
+    parameter ENCODERCHROMAFORMAT = "4_2_2";
+    parameter ENCODERCODING = "H.265";
+    parameter integer ENCODERCOLORDEPTH = 10;
+    parameter integer ENCODERNUMCORES = 4;
+    parameter integer ENCVERTRESOLUTION = 2160;
+    output VCUPLARREADYAXILITEAPB;
+    output VCUPLAWREADYAXILITEAPB;
+    output [1:0] VCUPLBRESPAXILITEAPB;
+    output VCUPLBVALIDAXILITEAPB;
+    output VCUPLCORESTATUSCLKPLL;
+    output [43:0] VCUPLDECARADDR0;
+    output [43:0] VCUPLDECARADDR1;
+    output [1:0] VCUPLDECARBURST0;
+    output [1:0] VCUPLDECARBURST1;
+    output [3:0] VCUPLDECARCACHE0;
+    output [3:0] VCUPLDECARCACHE1;
+    output [3:0] VCUPLDECARID0;
+    output [3:0] VCUPLDECARID1;
+    output [7:0] VCUPLDECARLEN0;
+    output [7:0] VCUPLDECARLEN1;
+    output VCUPLDECARPROT0;
+    output VCUPLDECARPROT1;
+    output [3:0] VCUPLDECARQOS0;
+    output [3:0] VCUPLDECARQOS1;
+    output [2:0] VCUPLDECARSIZE0;
+    output [2:0] VCUPLDECARSIZE1;
+    output VCUPLDECARVALID0;
+    output VCUPLDECARVALID1;
+    output [43:0] VCUPLDECAWADDR0;
+    output [43:0] VCUPLDECAWADDR1;
+    output [1:0] VCUPLDECAWBURST0;
+    output [1:0] VCUPLDECAWBURST1;
+    output [3:0] VCUPLDECAWCACHE0;
+    output [3:0] VCUPLDECAWCACHE1;
+    output [3:0] VCUPLDECAWID0;
+    output [3:0] VCUPLDECAWID1;
+    output [7:0] VCUPLDECAWLEN0;
+    output [7:0] VCUPLDECAWLEN1;
+    output VCUPLDECAWPROT0;
+    output VCUPLDECAWPROT1;
+    output [3:0] VCUPLDECAWQOS0;
+    output [3:0] VCUPLDECAWQOS1;
+    output [2:0] VCUPLDECAWSIZE0;
+    output [2:0] VCUPLDECAWSIZE1;
+    output VCUPLDECAWVALID0;
+    output VCUPLDECAWVALID1;
+    output VCUPLDECBREADY0;
+    output VCUPLDECBREADY1;
+    output VCUPLDECRREADY0;
+    output VCUPLDECRREADY1;
+    output [127:0] VCUPLDECWDATA0;
+    output [127:0] VCUPLDECWDATA1;
+    output VCUPLDECWLAST0;
+    output VCUPLDECWLAST1;
+    output VCUPLDECWVALID0;
+    output VCUPLDECWVALID1;
+    output [16:0] VCUPLENCALL2CADDR;
+    output VCUPLENCALL2CRVALID;
+    output [319:0] VCUPLENCALL2CWDATA;
+    output VCUPLENCALL2CWVALID;
+    output [43:0] VCUPLENCARADDR0;
+    output [43:0] VCUPLENCARADDR1;
+    output [1:0] VCUPLENCARBURST0;
+    output [1:0] VCUPLENCARBURST1;
+    output [3:0] VCUPLENCARCACHE0;
+    output [3:0] VCUPLENCARCACHE1;
+    output [3:0] VCUPLENCARID0;
+    output [3:0] VCUPLENCARID1;
+    output [7:0] VCUPLENCARLEN0;
+    output [7:0] VCUPLENCARLEN1;
+    output VCUPLENCARPROT0;
+    output VCUPLENCARPROT1;
+    output [3:0] VCUPLENCARQOS0;
+    output [3:0] VCUPLENCARQOS1;
+    output [2:0] VCUPLENCARSIZE0;
+    output [2:0] VCUPLENCARSIZE1;
+    output VCUPLENCARVALID0;
+    output VCUPLENCARVALID1;
+    output [43:0] VCUPLENCAWADDR0;
+    output [43:0] VCUPLENCAWADDR1;
+    output [1:0] VCUPLENCAWBURST0;
+    output [1:0] VCUPLENCAWBURST1;
+    output [3:0] VCUPLENCAWCACHE0;
+    output [3:0] VCUPLENCAWCACHE1;
+    output [3:0] VCUPLENCAWID0;
+    output [3:0] VCUPLENCAWID1;
+    output [7:0] VCUPLENCAWLEN0;
+    output [7:0] VCUPLENCAWLEN1;
+    output VCUPLENCAWPROT0;
+    output VCUPLENCAWPROT1;
+    output [3:0] VCUPLENCAWQOS0;
+    output [3:0] VCUPLENCAWQOS1;
+    output [2:0] VCUPLENCAWSIZE0;
+    output [2:0] VCUPLENCAWSIZE1;
+    output VCUPLENCAWVALID0;
+    output VCUPLENCAWVALID1;
+    output VCUPLENCBREADY0;
+    output VCUPLENCBREADY1;
+    output VCUPLENCRREADY0;
+    output VCUPLENCRREADY1;
+    output [127:0] VCUPLENCWDATA0;
+    output [127:0] VCUPLENCWDATA1;
+    output VCUPLENCWLAST0;
+    output VCUPLENCWLAST1;
+    output VCUPLENCWVALID0;
+    output VCUPLENCWVALID1;
+    output [43:0] VCUPLMCUMAXIICDCARADDR;
+    output [1:0] VCUPLMCUMAXIICDCARBURST;
+    output [3:0] VCUPLMCUMAXIICDCARCACHE;
+    output [2:0] VCUPLMCUMAXIICDCARID;
+    output [7:0] VCUPLMCUMAXIICDCARLEN;
+    output VCUPLMCUMAXIICDCARLOCK;
+    output [2:0] VCUPLMCUMAXIICDCARPROT;
+    output [3:0] VCUPLMCUMAXIICDCARQOS;
+    output [2:0] VCUPLMCUMAXIICDCARSIZE;
+    output VCUPLMCUMAXIICDCARVALID;
+    output [43:0] VCUPLMCUMAXIICDCAWADDR;
+    output [1:0] VCUPLMCUMAXIICDCAWBURST;
+    output [3:0] VCUPLMCUMAXIICDCAWCACHE;
+    output [2:0] VCUPLMCUMAXIICDCAWID;
+    output [7:0] VCUPLMCUMAXIICDCAWLEN;
+    output VCUPLMCUMAXIICDCAWLOCK;
+    output [2:0] VCUPLMCUMAXIICDCAWPROT;
+    output [3:0] VCUPLMCUMAXIICDCAWQOS;
+    output [2:0] VCUPLMCUMAXIICDCAWSIZE;
+    output VCUPLMCUMAXIICDCAWVALID;
+    output VCUPLMCUMAXIICDCBREADY;
+    output VCUPLMCUMAXIICDCRREADY;
+    output [31:0] VCUPLMCUMAXIICDCWDATA;
+    output VCUPLMCUMAXIICDCWLAST;
+    output [3:0] VCUPLMCUMAXIICDCWSTRB;
+    output VCUPLMCUMAXIICDCWVALID;
+    output VCUPLMCUSTATUSCLKPLL;
+    output VCUPLPINTREQ;
+    output VCUPLPLLSTATUSPLLLOCK;
+    output VCUPLPWRSUPPLYSTATUSVCCAUX;
+    output VCUPLPWRSUPPLYSTATUSVCUINT;
+    output [31:0] VCUPLRDATAAXILITEAPB;
+    output [1:0] VCUPLRRESPAXILITEAPB;
+    output VCUPLRVALIDAXILITEAPB;
+    output VCUPLWREADYAXILITEAPB;
+    input INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD;
+    input [19:0] PLVCUARADDRAXILITEAPB;
+    input [2:0] PLVCUARPROTAXILITEAPB;
+    input PLVCUARVALIDAXILITEAPB;
+    input [19:0] PLVCUAWADDRAXILITEAPB;
+    input [2:0] PLVCUAWPROTAXILITEAPB;
+    input PLVCUAWVALIDAXILITEAPB;
+    input PLVCUAXIDECCLK;
+    input PLVCUAXIENCCLK;
+    input PLVCUAXILITECLK;
+    input PLVCUAXIMCUCLK;
+    input PLVCUBREADYAXILITEAPB;
+    input PLVCUCORECLK;
+    input PLVCUDECARREADY0;
+    input PLVCUDECARREADY1;
+    input PLVCUDECAWREADY0;
+    input PLVCUDECAWREADY1;
+    input [3:0] PLVCUDECBID0;
+    input [3:0] PLVCUDECBID1;
+    input [1:0] PLVCUDECBRESP0;
+    input [1:0] PLVCUDECBRESP1;
+    input PLVCUDECBVALID0;
+    input PLVCUDECBVALID1;
+    input [127:0] PLVCUDECRDATA0;
+    input [127:0] PLVCUDECRDATA1;
+    input [3:0] PLVCUDECRID0;
+    input [3:0] PLVCUDECRID1;
+    input PLVCUDECRLAST0;
+    input PLVCUDECRLAST1;
+    input [1:0] PLVCUDECRRESP0;
+    input [1:0] PLVCUDECRRESP1;
+    input PLVCUDECRVALID0;
+    input PLVCUDECRVALID1;
+    input PLVCUDECWREADY0;
+    input PLVCUDECWREADY1;
+    input [319:0] PLVCUENCALL2CRDATA;
+    input PLVCUENCALL2CRREADY;
+    input PLVCUENCARREADY0;
+    input PLVCUENCARREADY1;
+    input PLVCUENCAWREADY0;
+    input PLVCUENCAWREADY1;
+    input [3:0] PLVCUENCBID0;
+    input [3:0] PLVCUENCBID1;
+    input [1:0] PLVCUENCBRESP0;
+    input [1:0] PLVCUENCBRESP1;
+    input PLVCUENCBVALID0;
+    input PLVCUENCBVALID1;
+    input PLVCUENCL2CCLK;
+    input [127:0] PLVCUENCRDATA0;
+    input [127:0] PLVCUENCRDATA1;
+    input [3:0] PLVCUENCRID0;
+    input [3:0] PLVCUENCRID1;
+    input PLVCUENCRLAST0;
+    input PLVCUENCRLAST1;
+    input [1:0] PLVCUENCRRESP0;
+    input [1:0] PLVCUENCRRESP1;
+    input PLVCUENCRVALID0;
+    input PLVCUENCRVALID1;
+    input PLVCUENCWREADY0;
+    input PLVCUENCWREADY1;
+    input PLVCUMCUCLK;
+    input PLVCUMCUMAXIICDCARREADY;
+    input PLVCUMCUMAXIICDCAWREADY;
+    input [2:0] PLVCUMCUMAXIICDCBID;
+    input [1:0] PLVCUMCUMAXIICDCBRESP;
+    input PLVCUMCUMAXIICDCBVALID;
+    input [31:0] PLVCUMCUMAXIICDCRDATA;
+    input [2:0] PLVCUMCUMAXIICDCRID;
+    input PLVCUMCUMAXIICDCRLAST;
+    input [1:0] PLVCUMCUMAXIICDCRRESP;
+    input PLVCUMCUMAXIICDCRVALID;
+    input PLVCUMCUMAXIICDCWREADY;
+    input PLVCUPLLREFCLKPL;
+    input PLVCURAWRSTN;
+    input PLVCURREADYAXILITEAPB;
+    input [31:0] PLVCUWDATAAXILITEAPB;
+    input [3:0] PLVCUWSTRBAXILITEAPB;
+    input PLVCUWVALIDAXILITEAPB;
+endmodule
+
+module FE (...);
+    parameter MODE = "TURBO_DECODE";
+    parameter real PHYSICAL_UTILIZATION = 100.00;
+    parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+    parameter STANDARD = "LTE";
+    parameter real THROUGHPUT_UTILIZATION = 100.00;
+    output [399:0] DEBUG_DOUT;
+    output DEBUG_PHASE;
+    output INTERRUPT;
+    output [511:0] M_AXIS_DOUT_TDATA;
+    output M_AXIS_DOUT_TLAST;
+    output M_AXIS_DOUT_TVALID;
+    output [31:0] M_AXIS_STATUS_TDATA;
+    output M_AXIS_STATUS_TVALID;
+    output [15:0] SPARE_OUT;
+    output S_AXIS_CTRL_TREADY;
+    output S_AXIS_DIN_TREADY;
+    output S_AXIS_DIN_WORDS_TREADY;
+    output S_AXIS_DOUT_WORDS_TREADY;
+    output S_AXI_ARREADY;
+    output S_AXI_AWREADY;
+    output S_AXI_BVALID;
+    output [31:0] S_AXI_RDATA;
+    output S_AXI_RVALID;
+    output S_AXI_WREADY;
+    input CORE_CLK;
+    input DEBUG_CLK_EN;
+    input DEBUG_EN;
+    input [3:0] DEBUG_SEL_IN;
+    input M_AXIS_DOUT_ACLK;
+    input M_AXIS_DOUT_TREADY;
+    input M_AXIS_STATUS_ACLK;
+    input M_AXIS_STATUS_TREADY;
+    input RESET_N;
+    input [15:0] SPARE_IN;
+    input S_AXIS_CTRL_ACLK;
+    input [31:0] S_AXIS_CTRL_TDATA;
+    input S_AXIS_CTRL_TVALID;
+    input S_AXIS_DIN_ACLK;
+    input [511:0] S_AXIS_DIN_TDATA;
+    input S_AXIS_DIN_TLAST;
+    input S_AXIS_DIN_TVALID;
+    input S_AXIS_DIN_WORDS_ACLK;
+    input [31:0] S_AXIS_DIN_WORDS_TDATA;
+    input S_AXIS_DIN_WORDS_TLAST;
+    input S_AXIS_DIN_WORDS_TVALID;
+    input S_AXIS_DOUT_WORDS_ACLK;
+    input [31:0] S_AXIS_DOUT_WORDS_TDATA;
+    input S_AXIS_DOUT_WORDS_TLAST;
+    input S_AXIS_DOUT_WORDS_TVALID;
+    input S_AXI_ACLK;
+    input [17:0] S_AXI_ARADDR;
+    input S_AXI_ARVALID;
+    input [17:0] S_AXI_AWADDR;
+    input S_AXI_AWVALID;
+    input S_AXI_BREADY;
+    input S_AXI_RREADY;
+    input [31:0] S_AXI_WDATA;
+    input S_AXI_WVALID;
+endmodule
+