+2003-05-19 Richard Sandiford <rsandifo@redhat.com>
+
+ * config/mips/mips-protos.h (final_prescan_insn,
+ mips_count_memory_refs, mips_fill_delay_slot): Remove.
+ * config/mips/mips.h (delay_type, dslots_load_total,
+ dslots_load_filled, dslots_jump_total, dslots_jump_filled,
+ dslots_number_nops, num_refs, mips_load_reg, mips_load_reg2,
+ mips_load_reg3, mips_load_reg4): Remove.
+ (MASK_STATS): Remove.
+ (MASK_EXPLICIT_RELOCS): Reuse its value.
+ (TARGET_STATS): Remove.
+ (TARGET_SWITCHES): Turn -mstats and -mno-stats into no-ops.
+ Warn that -mstats is now ignored.
+ (FINAL_PRESCAN_INSN): Undefine.
+ (DBR_OUTPUT_SEQEND): Remove handling of dslot statistics.
+ (ASM_OUTPUT_REG_POP): Likewise.
+ * config/mips/mips.c (dslots_load_total, dslots_load_filled,
+ dslots_jump_total, dslots_jump_filled, dslots_number_nops, num_refs,
+ mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4,
+ mips_fill_delay_slot, mips_count_memory_refs,
+ final_prescan_insn): Remove.
+ (output_block_move): Remove calls to mips_count_memory_refs.
+ (print_operand): Remove printing of #nop for TARGET_STATS.
+ (mips_output_function_epilogue): Remove TARGET_STATS code.
+ Reorganize setting of fnnmae.
+ * config/mips/mips.md: Remove handling of dslot statistics
+ throughout file. Change all fcmp patterns into normal asm
+ templates, removing calls to mips_fill_delay_slot.
+ * doc/invoke.texi: Remove documentation of -mstats.
+
2003-05-19 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.c (mips_class_max_nregs): Return the number of
extern bool mips_expand_unaligned_store PARAMS ((rtx, rtx,
unsigned int,
int));
-extern void final_prescan_insn PARAMS ((rtx, rtx *, int));
extern void init_cumulative_args PARAMS ((CUMULATIVE_ARGS *,
tree, rtx));
extern void gen_conditional_move PARAMS ((rtx *));
extern void mips_gen_conditional_trap PARAMS ((rtx *));
extern void mips_emit_fcc_reload PARAMS ((rtx, rtx, rtx));
extern void mips_set_return_address PARAMS ((rtx, rtx));
-extern void mips_count_memory_refs PARAMS ((rtx, int));
extern HOST_WIDE_INT mips_debugger_offset PARAMS ((rtx, HOST_WIDE_INT));
-extern const char *mips_fill_delay_slot PARAMS ((const char *,
- enum delay_type, rtx *,
- rtx));
extern rtx mips_subword PARAMS ((rtx, int));
extern bool mips_split_64bit_move_p PARAMS ((rtx, rtx));
extern void mips_split_64bit_move PARAMS ((rtx, rtx));
/* The next branch instruction is a branch likely, not branch normal. */
int mips_branch_likely;
-/* Count of delay slots and how many are filled. */
-int dslots_load_total;
-int dslots_load_filled;
-int dslots_jump_total;
-int dslots_jump_filled;
-
-/* # of nops needed by previous insn */
-int dslots_number_nops;
-
-/* Number of 1/2/3 word references to data items (ie, not jal's). */
-int num_refs[3];
-
-/* registers to check for load delay */
-rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
-
/* Cached operands, and operator to compare for use in set/branch/trap
on condition codes. */
rtx branch_cmp[2];
return 0;
}
-\f
-/* Returns an operand string for the given instruction's delay slot,
- after updating filled delay slot statistics.
-
- We assume that operands[0] is the target register that is set.
-
- In order to check the next insn, most of this functionality is moved
- to FINAL_PRESCAN_INSN, and we just set the global variables that
- it needs. */
-
-/* ??? This function no longer does anything useful, because final_prescan_insn
- now will never emit a nop. */
-
-const char *
-mips_fill_delay_slot (ret, type, operands, cur_insn)
- const char *ret; /* normal string to return */
- enum delay_type type; /* type of delay */
- rtx operands[]; /* operands to use */
- rtx cur_insn; /* current insn */
-{
- register rtx set_reg;
- register enum machine_mode mode;
- register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
- register int num_nops;
-
- if (type == DELAY_LOAD || type == DELAY_FCMP)
- num_nops = 1;
-
- else if (type == DELAY_HILO)
- num_nops = 2;
-
- else
- num_nops = 0;
-
- /* Make sure that we don't put nop's after labels. */
- next_insn = NEXT_INSN (cur_insn);
- while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
- next_insn = NEXT_INSN (next_insn);
-
- dslots_load_total += num_nops;
- if (TARGET_DEBUG_F_MODE
- || !optimize
- || type == DELAY_NONE
- || operands == 0
- || cur_insn == 0
- || next_insn == 0
- || GET_CODE (next_insn) == CODE_LABEL
- || (set_reg = operands[0]) == 0)
- {
- dslots_number_nops = 0;
- mips_load_reg = 0;
- mips_load_reg2 = 0;
- mips_load_reg3 = 0;
- mips_load_reg4 = 0;
- return ret;
- }
-
- set_reg = operands[0];
- if (set_reg == 0)
- return ret;
-
- while (GET_CODE (set_reg) == SUBREG)
- set_reg = SUBREG_REG (set_reg);
-
- mode = GET_MODE (set_reg);
- dslots_number_nops = num_nops;
- mips_load_reg = set_reg;
- if (GET_MODE_SIZE (mode)
- > (unsigned) (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
- mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
- else
- mips_load_reg2 = 0;
-
- if (type == DELAY_HILO)
- {
- mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
- mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
- }
- else
- {
- mips_load_reg3 = 0;
- mips_load_reg4 = 0;
- }
-
- return ret;
-}
-
\f
static bool
mips_rtx_costs (x, code, outer_code, total)
{
return mips_address_insns (addr, SImode);
}
-
-/* Determine whether a memory reference takes one (based off of the GP
- pointer), two (normal), or three (label + reg) instructions, and bump the
- appropriate counter for -mstats. */
-
-void
-mips_count_memory_refs (op, num)
- rtx op;
- int num;
-{
- int additional = 0;
- int n_words = 0;
- rtx addr, plus0, plus1;
- enum rtx_code code0, code1;
- int looping;
-
- if (TARGET_DEBUG_B_MODE)
- {
- fprintf (stderr, "\n========== mips_count_memory_refs:\n");
- debug_rtx (op);
- }
-
- /* Skip MEM if passed, otherwise handle movsi of address. */
- addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
-
- /* Loop, going through the address RTL. */
- do
- {
- looping = FALSE;
- switch (GET_CODE (addr))
- {
- case REG:
- case CONST_INT:
- case LO_SUM:
- break;
-
- case PLUS:
- plus0 = XEXP (addr, 0);
- plus1 = XEXP (addr, 1);
- code0 = GET_CODE (plus0);
- code1 = GET_CODE (plus1);
-
- if (code0 == REG)
- {
- additional++;
- addr = plus1;
- looping = 1;
- continue;
- }
-
- if (code0 == CONST_INT)
- {
- addr = plus1;
- looping = 1;
- continue;
- }
-
- if (code1 == REG)
- {
- additional++;
- addr = plus0;
- looping = 1;
- continue;
- }
-
- if (code1 == CONST_INT)
- {
- addr = plus0;
- looping = 1;
- continue;
- }
-
- if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
- {
- addr = plus0;
- looping = 1;
- continue;
- }
-
- if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
- {
- addr = plus1;
- looping = 1;
- continue;
- }
-
- break;
-
- case LABEL_REF:
- n_words = 2; /* always 2 words */
- break;
-
- case CONST:
- addr = XEXP (addr, 0);
- looping = 1;
- continue;
-
- case SYMBOL_REF:
- n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
- break;
-
- default:
- break;
- }
- }
- while (looping);
-
- if (n_words == 0)
- return;
-
- n_words += additional;
- if (n_words > 3)
- n_words = 3;
-
- num_refs[n_words-1] += num;
-}
-
\f
/* Return a pseudo that points to the address of the current function.
The first time it is called for a function, an initializer for the
{
if (CONSTANT_P (src_reg))
{
- if (TARGET_STATS)
- mips_count_memory_refs (operands[1], 1);
-
src_reg = operands[3 + num_regs--];
if (move_type != BLOCK_MOVE_LAST)
{
if (CONSTANT_P (dest_reg))
{
- if (TARGET_STATS)
- mips_count_memory_refs (operands[0], 1);
-
dest_reg = operands[3 + num_regs--];
if (move_type != BLOCK_MOVE_LAST)
{
bytes--;
}
- if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
- {
- dslots_load_total++;
- dslots_load_filled++;
-
- if (CONSTANT_P (src_reg))
- mips_count_memory_refs (src_reg, 1);
-
- if (CONSTANT_P (dest_reg))
- mips_count_memory_refs (dest_reg, 1);
- }
-
/* Emit load/stores now if we have run out of registers or are
at the end of the move. */
{
/* If only load/store, we need a NOP after the load. */
if (num == 1)
- {
- load_store[0].load = load_store[0].load_nop;
- if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
- dslots_load_filled--;
- }
+ load_store[0].load = load_store[0].load_nop;
if (move_type != BLOCK_MOVE_LAST)
{
case '#':
if (set_noreorder != 0)
fputs ("\n\tnop", file);
- else if (TARGET_STATS)
- fputs ("\n\t#nop", file);
-
break;
case '(':
fprintf (stream, "\"\n");
}
\f
-/* If defined, a C statement to be executed just prior to the output of
- assembler code for INSN, to modify the extracted operands so they will be
- output differently.
-
- Here the argument OPVEC is the vector containing the operands extracted
- from INSN, and NOPERANDS is the number of elements of the vector which
- contain meaningful data for this insn. The contents of this vector are
- what will be used to convert the insn template into assembler code, so you
- can change the assembler output by changing the contents of the vector.
-
- We use it to check if the current insn needs a nop in front of it because
- of load delays, and also to update the delay slot statistics. */
-
-/* ??? There is no real need for this function, because it never actually
- emits a NOP anymore. */
-
-void
-final_prescan_insn (insn, opvec, noperands)
- rtx insn;
- rtx opvec[] ATTRIBUTE_UNUSED;
- int noperands ATTRIBUTE_UNUSED;
-{
- if (dslots_number_nops > 0)
- {
- rtx pattern = PATTERN (insn);
- int length = get_attr_length (insn);
-
- /* Do we need to emit a NOP? */
- if (length == 0
- || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
- || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
- || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
- || (mips_load_reg4 != 0
- && reg_mentioned_p (mips_load_reg4, pattern)))
- fputs ("\t#nop\n", asm_out_file);
-
- else
- dslots_load_filled++;
-
- while (--dslots_number_nops > 0)
- fputs ("\t#nop\n", asm_out_file);
-
- mips_load_reg = 0;
- mips_load_reg2 = 0;
- mips_load_reg3 = 0;
- mips_load_reg4 = 0;
- }
-
- if (TARGET_STATS
- && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
- dslots_jump_total++;
-}
-\f
/* Output at beginning of assembler file.
If we are optimizing to use the global pointer, create a temporary file to
FILE *file ATTRIBUTE_UNUSED;
HOST_WIDE_INT size ATTRIBUTE_UNUSED;
{
- const char *fnname = ""; /* FIXME: Correct initialisation? */
rtx string;
#ifndef FUNCTION_NAME_ALREADY_DECLARED
- /* Get the function name the same way that toplev.c does before calling
- assemble_start_function. This is needed so that the name used here
- exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
- fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
-
if (!flag_inhibit_size_directive)
{
+ const char *fnname;
+
+ /* Get the function name the same way that toplev.c does before calling
+ assemble_start_function. This is needed so that the name used here
+ exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
+ fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
fputs ("\t.end\t", file);
assemble_name (file, fnname);
fputs ("\n", file);
}
#endif
- if (TARGET_STATS)
- {
- int num_gp_regs = cfun->machine->frame.gp_reg_size / 4;
- int num_fp_regs = cfun->machine->frame.fp_reg_size / 8;
- int num_regs = num_gp_regs + num_fp_regs;
- const char *name = fnname;
-
- if (name[0] == '*')
- name++;
-
- dslots_load_total += num_regs;
-
- fprintf (stderr,
- "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
- name, frame_pointer_needed ? 'y' : 'n',
- (cfun->machine->frame.mask & RA_MASK) != 0 ? 'n' : 'y',
- current_function_calls_alloca ? 'y' : 'n',
- current_function_calls_setjmp ? 'y' : 'n',
- cfun->machine->frame.total_size,
- current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
- dslots_load_total, dslots_load_filled,
- dslots_jump_total, dslots_jump_filled,
- num_refs[0], num_refs[1], num_refs[2]);
-
- fputc ('\n', stderr);
- }
-
/* Reset state info for each function. */
inside_function = 0;
ignore_line_number = 0;
- dslots_load_total = 0;
- dslots_jump_total = 0;
- dslots_load_filled = 0;
- dslots_jump_filled = 0;
- num_refs[0] = 0;
- num_refs[1] = 0;
- num_refs[2] = 0;
- mips_load_reg = 0;
- mips_load_reg2 = 0;
while (string_constants != NULL)
{
CMP_MAX /* max comparison type */
};
-/* types of delay slot */
-enum delay_type {
- DELAY_NONE, /* no delay slot */
- DELAY_LOAD, /* load from memory delay */
- DELAY_HILO, /* move from/to hi/lo registers */
- DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
-};
-
/* Which processor to schedule for. Since there is no difference between
a R2000 and R3000 in terms of the scheduler, we collapse them into
just an R3000. The elements of the enumeration must match exactly
extern const char *mips_entry_string; /* for -mentry */
extern const char *mips_no_mips16_string;/* for -mno-mips16 */
extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
-extern int dslots_load_total; /* total # load related delay slots */
-extern int dslots_load_filled; /* # filled load delay slots */
-extern int dslots_jump_total; /* total # jump related delay slots */
-extern int dslots_jump_filled; /* # filled jump delay slots */
-extern int dslots_number_nops; /* # of nops needed by previous insn */
-extern int num_refs[3]; /* # 1/2/3 word references */
-extern GTY(()) rtx mips_load_reg; /* register to check for load delay */
-extern GTY(()) rtx mips_load_reg2; /* 2nd reg to check for load delay */
-extern GTY(()) rtx mips_load_reg3; /* 3rd reg to check for load delay */
-extern GTY(()) rtx mips_load_reg4; /* 4th reg to check for load delay */
extern int mips_string_length; /* length of strings for mips16 */
extern const struct mips_cpu_info mips_cpu_info_table[];
extern const struct mips_cpu_info *mips_arch_info;
#define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
#define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
#define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
-#define MASK_STATS 0x00000040 /* print statistics to stderr */
+#define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
#define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
#define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
#define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
multiply-add operations. */
#define MASK_BRANCHLIKELY 0x02000000 /* Generate Branch Likely
instructions. */
-#define MASK_EXPLICIT_RELOCS 0x04000000 /* Use relocation operators. */
/* Debug switches, not documented */
#define MASK_DEBUG 0 /* unused */
/* Optimize for Sdata/Sbss */
#define TARGET_GP_OPT (target_flags & MASK_GPOPT)
- /* print program statistics */
-#define TARGET_STATS (target_flags & MASK_STATS)
-
/* call memcpy instead of inline code */
#define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
N_("Don't use GP relative sdata/sbss sections")}, \
{"no-gpopt", -MASK_GPOPT, \
N_("Don't use GP relative sdata/sbss sections")}, \
- {"stats", MASK_STATS, \
- N_("Output compiler statistics")}, \
- {"no-stats", -MASK_STATS, \
+ {"stats", 0, \
+ N_("Output compiler statistics (now ignored)")}, \
+ {"no-stats", 0, \
N_("Don't output compiler statistics")}, \
{"memcpy", MASK_MEMCPY, \
N_("Don't optimize block moves")}, \
#define SPECIAL_MODE_PREDICATES \
"pc_or_label_operand",
-
-\f
-/* If defined, a C statement to be executed just prior to the
- output of assembler code for INSN, to modify the extracted
- operands so they will be output differently.
-
- Here the argument OPVEC is the vector containing the operands
- extracted from INSN, and NOPERANDS is the number of elements of
- the vector which contain meaningful data for this insn. The
- contents of this vector are what will be used to convert the
- insn template into assembler code, so you can change the
- assembler output by changing the contents of the vector.
-
- We use it to check if the current insn needs a nop in front of it
- because of load delays, and also to update the delay slot
- statistics. */
-
-#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
- final_prescan_insn (INSN, OPVEC, NOPERANDS)
-
\f
/* Control the assembler format that we output. */
if (set_noreorder > 0 && --set_noreorder == 0) \
fputs ("\t.set\treorder\n", STREAM); \
\
- dslots_jump_filled++; \
fputs ("\n", STREAM); \
} \
while (0)
if (! set_noreorder) \
fprintf (STREAM, "\t.set\tnoreorder\n"); \
\
- dslots_load_total++; \
- dslots_load_filled++; \
fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
TARGET_64BIT ? "ld" : "lw", \
reg_names[REGNO], \
"!TARGET_MIPS16"
"*
{
- dslots_jump_total++;
- dslots_jump_filled++;
operands[2] = const0_rtx;
if (REGNO (operands[0]) == REGNO (operands[1]))
"*
{
unsigned int regno1;
- dslots_jump_total++;
- dslots_jump_filled++;
operands[2] = const0_rtx;
if (GET_CODE (operands[1]) == REG)
"!TARGET_MIPS16"
"*
{
- dslots_jump_total += 2;
- dslots_jump_filled += 2;
operands[4] = const0_rtx;
if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
"TARGET_64BIT && !TARGET_MIPS16"
"*
{
- dslots_jump_total += 2;
- dslots_jump_filled += 2;
operands[4] = const0_rtx;
if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
"*
{
operands[4] = const0_rtx;
- dslots_jump_total += 3;
- dslots_jump_filled += 2;
return \"sll\\t%3,%2,26\\n\\
\\tbgez\\t%3,1f\\n\\
"*
{
operands[4] = const0_rtx;
- dslots_jump_total += 3;
- dslots_jump_filled += 2;
return \"sll\\t%3,%2,26\\n\\
\\tbgez\\t%3,1f\\n\\
"*
{
operands[4] = const0_rtx;
- dslots_jump_total += 3;
- dslots_jump_filled += 2;
return \"sll\\t%3,%2,26\\n\\
\\tbgez\\t%3,1f\\n\\
(unordered:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.un.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.un.d\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "sunlt_df"
[(set (match_operand:CC 0 "register_operand" "=z")
(unlt:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.ult.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.ult.d\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "suneq_df"
[(set (match_operand:CC 0 "register_operand" "=z")
(uneq:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.ueq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.ueq.d\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "sunle_df"
[(set (match_operand:CC 0 "register_operand" "=z")
(unle:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.ule.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.ule.d\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "seq_df"
[(set (match_operand:CC 0 "register_operand" "=z")
(eq:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.eq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.eq.d\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "slt_df"
[(set (match_operand:CC 0 "register_operand" "=z")
(lt:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.lt.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.lt.d\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "sle_df"
[(set (match_operand:CC 0 "register_operand" "=z")
(le:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.le.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.le.d\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "sgt_df"
[(set (match_operand:CC 0 "register_operand" "=z")
(gt:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.lt.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.lt.d\t%Z0%2,%1"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "sge_df"
[(set (match_operand:CC 0 "register_operand" "=z")
(ge:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.le.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.le.d\t%Z0%2,%1"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "sunordered_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
(unordered:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.un.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.un.s\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "sunlt_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
(unlt:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.ult.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.ult.s\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "suneq_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
(uneq:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.ueq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.ueq.s\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "sunle_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
(unle:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.ule.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.ule.s\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "seq_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
(eq:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.eq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.eq.s\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "slt_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
(lt:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.lt.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.lt.s\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "sle_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
(le:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.le.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.le.s\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "sgt_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
(gt:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.lt.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.lt.s\t%Z0%2,%1"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
(define_insn "sge_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
(ge:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.le.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ "c.le.s\t%Z0%2,%1"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
\f
;;
-mno-memcpy -mno-mips-tfile -mno-rnames -mno-stats @gol
-mrnames -msoft-float @gol
-m4650 -msingle-float -mmad @gol
--mstats -EL -EB -G @var{num} -nocpp @gol
+-EL -EB -G @var{num} -nocpp @gol
-mabi=32 -mabi=n32 -mabi=64 -mabi=eabi -mabi-fake-default @gol
-mfix7000 -mno-crt0 -mflush-func=@var{func} -mno-flush-func @gol
-mbranch-likely -mno-branch-likely}
words for short global or static data items. This is on by default if
optimization is selected.
-@item -mstats
-@itemx -mno-stats
-@opindex mstats
-@opindex mno-stats
-For each non-inline function processed, the @option{-mstats} switch
-causes the compiler to emit one line to the standard error file to
-print statistics about the program (number of registers saved, stack
-size, etc.).
-
@item -mmemcpy
@itemx -mno-memcpy
@opindex mmemcpy
projects / gcc.git / commitdiff