Will be used for asic specific pm4 behavior.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
return;
- pm4 = CALLOC_STRUCT(si_pm4_state);
+ pm4 = si_pm4_alloc_state(ctx);
+
+ if (pm4 == NULL)
+ return;
+
si_cmd_surface_sync(pm4, S_0085F0_CB0_DEST_BASE_ENA(1) |
S_0085F0_CB1_DEST_BASE_ENA(1) |
S_0085F0_CB2_DEST_BASE_ENA(1) |
FREE(state);
}
+struct si_pm4_state * si_pm4_alloc_state(struct r600_context *rctx)
+{
+ struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+
+ if (pm4 == NULL)
+ return NULL;
+
+ pm4->chip_class = rctx->chip_class;
+
+ return pm4;
+}
+
uint32_t si_pm4_sync_flags(struct r600_context *rctx)
{
uint32_t cp_coher_cntl = 0;
// forward defines
struct r600_context;
+enum chip_class;
struct si_pm4_state
{
+ /* family specific handling */
+ enum chip_class chip_class;
/* PKT3_SET_*_REG handling */
unsigned last_opcode;
unsigned last_reg;
void si_pm4_free_state(struct r600_context *rctx,
struct si_pm4_state *state,
unsigned idx);
+struct si_pm4_state * si_pm4_alloc_state(struct r600_context *rctx);
uint32_t si_pm4_sync_flags(struct r600_context *rctx);
unsigned si_pm4_dirty_dw(struct r600_context *rctx);
if (blend == NULL)
return;
- pm4 = CALLOC_STRUCT(si_pm4_state);
+ pm4 = si_pm4_alloc_state(rctx);
if (pm4 == NULL)
return;
const struct pipe_blend_color *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
if (pm4 == NULL)
return;
const struct pipe_clip_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
struct pipe_constant_buffer cb;
if (pm4 == NULL)
const struct pipe_scissor_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
uint32_t tl, br;
if (pm4 == NULL)
return;
}
- pm4 = CALLOC_STRUCT(si_pm4_state);
+ pm4 = si_pm4_alloc_state(rctx);
+
+ if (pm4 == NULL)
+ return;
+
/* FIXME some of those reg can be computed with cso */
offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
*/
static void si_update_dsa_stencil_ref(struct r600_context *rctx)
{
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
struct pipe_stencil_ref *ref = &rctx->stencil_ref;
struct si_state_dsa *dsa = rctx->queued.named.dsa;
const struct pipe_framebuffer_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
uint32_t tl, br;
int tl_x, tl_y, br_x, br_y;
unsigned user_data_reg)
{
struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
int i, j;
if (!count)
unsigned user_data_reg)
{
struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
uint32_t *border_color_table = NULL;
int i, j;
static void si_texture_barrier(struct pipe_context *ctx)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+
+ if (pm4 == NULL)
+ return;
si_pm4_inval_texture_cache(pm4);
si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
void si_init_config(struct r600_context *rctx)
{
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+
+ if (pm4 == NULL)
+ return;
si_cmd_context_control(pm4);
uint64_t va;
si_pm4_delete_state(rctx, vs, shader->pm4);
- pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
+ pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
+
+ if (pm4 == NULL)
+ return;
si_pm4_inval_shader_cache(pm4);
uint64_t va;
si_pm4_delete_state(rctx, ps, shader->pm4);
- pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
+ pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
+
+ if (pm4 == NULL)
+ return;
si_pm4_inval_shader_cache(pm4);
static bool si_update_draw_info_state(struct r600_context *rctx,
const struct pipe_draw_info *info)
{
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
struct si_shader *vs = &rctx->vs_shader->current->shader;
unsigned prim = si_conv_pipe_prim(info->mode);
unsigned ls_mask = 0;
{
struct si_shader *ps = &rctx->ps_shader->current->shader;
struct si_shader *vs = &rctx->vs_shader->current->shader;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
unsigned i, j, tmp;
for (i = 0; i < ps->ninput; i++) {
static void si_vertex_buffer_update(struct r600_context *rctx)
{
struct pipe_context *ctx = &rctx->context;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
bool bound[PIPE_MAX_ATTRIBS] = {};
unsigned i, count;
uint64_t va;
const struct pipe_draw_info *info,
const struct pipe_index_buffer *ib)
{
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+
+ if (pm4 == NULL)
+ return;
/* queries need some special values
* (this is non-zero if any query is active) */
cp_coher_cntl = si_pm4_sync_flags(rctx);
if (cp_coher_cntl) {
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+
+ if (pm4 == NULL)
+ return;
+
si_cmd_surface_sync(pm4, cp_coher_cntl);
si_pm4_set_state(rctx, sync, pm4);
}