# List of headers to generate
isa_switch_hdrs = Split('''
- faults.hh
interrupts.hh
isa.hh
isa_traits.hh
#include <string>
#include <queue>
-#include "arch/faults.hh"
#include "arch/utility.hh"
#include "base/fast_alloc.hh"
#include "base/trace.hh"
#include "cpu/translation.hh"
#include "mem/packet.hh"
#include "sim/byteswap.hh"
+#include "sim/fault_fwd.hh"
#include "sim/system.hh"
#include "sim/tlb.hh"
#include <vector>
-#include "arch/faults.hh"
#include "arch/isa_traits.hh"
#include "base/types.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include <sstream>
#include <string>
-#include "arch/faults.hh"
#include "base/bigint.hh"
#include "base/cp_annotate.hh"
#include "base/cprintf.hh"
#include "cpu/exetrace.hh"
#include "debug/InOrderDynInst.hh"
#include "mem/request.hh"
+#include "sim/fault_fwd.hh"
#include "sim/full_system.hh"
using namespace std;
#include <list>
#include <string>
-#include "arch/faults.hh"
#include "arch/isa_traits.hh"
#include "arch/mt.hh"
#include "arch/types.hh"
#include "cpu/thread_context.hh"
#include "debug/InOrderDynInst.hh"
#include "mem/packet.hh"
+#include "sim/fault_fwd.hh"
#include "sim/system.hh"
#if THE_ISA == ALPHA_ISA
#ifndef __CPU_INORDER_THREAD_STATE_HH__
#define __CPU_INORDER_THREAD_STATE_HH__
-#include "arch/faults.hh"
#include "arch/isa_traits.hh"
#include "base/callback.hh"
#include "base/output.hh"
#include <map>
#include <queue>
-#include "arch/faults.hh"
#include "arch/generic/debugfaults.hh"
#include "arch/isa_traits.hh"
#include "arch/locked_mem.hh"
#include "debug/LSQUnit.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
+#include "sim/fault_fwd.hh"
struct DerivO3CPUParams;
*/
#include "arch/alpha/osfpal.hh"
-#include "arch/faults.hh"
#include "arch/isa_traits.hh" // For MachInst
#include "arch/kernel_stats.hh"
#include "arch/tlb.hh"
#include <map>
#include <queue>
-#include "arch/faults.hh"
#include "arch/types.hh"
#include "base/hashmap.hh"
#include "config/the_isa.hh"
#include "cpu/inst_seq.hh"
#include "mem/mem_interface.hh"
//#include "mem/page_table.hh"
+#include "sim/fault_fwd.hh"
#include "sim/sim_object.hh"
class PageTable;
* Authors: Kevin Lim
*/
-#include "arch/faults.hh"
#include "base/str.hh"
#include "config/the_isa.hh"
#include "cpu/ozone/lsq_unit.hh"
+#include "sim/fault_fwd.hh"
template <class Impl>
OzoneLSQ<Impl>::StoreCompletionEvent::StoreCompletionEvent(int store_idx,
#include <map>
#include <queue>
-#include "arch/faults.hh"
#include "arch/types.hh"
#include "base/fast_alloc.hh"
#include "base/hashmap.hh"
#include "mem/port.hh"
//#include "mem/page_table.hh"
#include "sim/debug.hh"
+#include "sim/fault_fwd.hh"
#include "sim/sim_object.hh"
class MemObject;
* Authors: Kevin Lim
*/
-#include "arch/faults.hh"
#include "base/str.hh"
#include "config/the_isa.hh"
#include "config/use_checker.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/ozone/lw_lsq.hh"
+#include "sim/fault_fwd.hh"
template<class Impl>
OzoneLWLSQ<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
* Authors: Steve Reinhardt
*/
-#include "arch/faults.hh"
#include "arch/kernel_stats.hh"
#include "arch/stacktrace.hh"
#include "arch/tlb.hh"
#include "params/BaseSimpleCPU.hh"
#include "sim/byteswap.hh"
#include "sim/debug.hh"
+#include "sim/faults.hh"
#include "sim/full_system.hh"
#include "sim/sim_events.hh"
#include "sim/sim_object.hh"