write_xaiger to skip POs driven by 1'bx

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 1485e2b0c23876f3a1f997e56bc17cea5d487454..12b23cfe9141683a59ed0ea518d9d1cd0af00bcf 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -152,9 +152,13 @@ struct XAigerWriter
                                }
 
                                if (wire->port_output || keep) {
-                                       if (bit != wirebit)
-                                               alias_map[wirebit] = bit;
-                                       output_bits.insert(wirebit);
+                                       if (bit != RTLIL::Sx) {
+                                               if (bit != wirebit)
+                                                       alias_map[wirebit] = bit;
+                                               output_bits.insert(wirebit);
+                                       }
+                                       else
+                                               log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
                                }
                        }
                }