broadcom/vc5: Update QPU instruction pack/unpack for v4.2.

After the 4.1 spec, 4.2 retroactively renamed patchid to barrierid because
it's used for other barriers in compute.

diff --git a/src/broadcom/qpu/qpu_instr.c b/src/broadcom/qpu/qpu_instr.c
index 986097a11be39ad627db242db0e6a088f9675f11..f31c81f8ca4defd7571cde68aea6aa0a0aa51d0d 100644 (file)
--- a/src/broadcom/qpu/qpu_instr.c
+++ b/src/broadcom/qpu/qpu_instr.c
@@ -48,6 +48,7 @@ v3d_qpu_magic_waddr_name(enum v3d_qpu_waddr waddr)
                 [V3D_QPU_WADDR_VPMU] = "vpmu",
                 [V3D_QPU_WADDR_SYNC] = "sync",
                 [V3D_QPU_WADDR_SYNCU] = "syncu",
+                [V3D_QPU_WADDR_SYNCB] = "syncb",
                 [V3D_QPU_WADDR_RECIP] = "recip",
                 [V3D_QPU_WADDR_RSQRT] = "rsqrt",
                 [V3D_QPU_WADDR_EXP] = "exp",
@@ -125,7 +126,7 @@ v3d_qpu_add_op_name(enum v3d_qpu_add_op op)
                 [V3D_QPU_A_VDWWT] = "vdwwt",
                 [V3D_QPU_A_IID] = "iid",
                 [V3D_QPU_A_SAMPID] = "sampid",
-                [V3D_QPU_A_PATCHID] = "patchid",
+                [V3D_QPU_A_BARRIERID] = "barrierid",
                 [V3D_QPU_A_TMUWT] = "tmuwt",
                 [V3D_QPU_A_VPMSETUP] = "vpmsetup",
                 [V3D_QPU_A_VPMWT] = "vpmwt",
@@ -389,7 +390,7 @@ static const uint8_t add_op_args[] = {
         [V3D_QPU_A_VDWWT] = D,
         [V3D_QPU_A_IID] = D,
         [V3D_QPU_A_SAMPID] = D,
-        [V3D_QPU_A_PATCHID] = D,
+        [V3D_QPU_A_BARRIERID] = D,
         [V3D_QPU_A_TMUWT] = D,
         [V3D_QPU_A_VPMWT] = D,
 

diff --git a/src/broadcom/qpu/qpu_instr.h b/src/broadcom/qpu/qpu_instr.h
index b65a35ae3c3a641c5cc5a743ed61a6d6e5e11a3a..2289e182256af347d4c8a3e31803483af90918ef 100644 (file)
--- a/src/broadcom/qpu/qpu_instr.h
+++ b/src/broadcom/qpu/qpu_instr.h
@@ -107,7 +107,7 @@ enum v3d_qpu_waddr {
         V3D_QPU_WADDR_VPMU = 15,
         V3D_QPU_WADDR_SYNC = 16,
         V3D_QPU_WADDR_SYNCU = 17,
-        /* reserved */
+        V3D_QPU_WADDR_SYNCB = 18,
         V3D_QPU_WADDR_RECIP = 19,
         V3D_QPU_WADDR_RSQRT = 20,
         V3D_QPU_WADDR_EXP = 21,
@@ -185,7 +185,7 @@ enum v3d_qpu_add_op {
         V3D_QPU_A_VDWWT,
         V3D_QPU_A_IID,
         V3D_QPU_A_SAMPID,
-        V3D_QPU_A_PATCHID,
+        V3D_QPU_A_BARRIERID,
         V3D_QPU_A_TMUWT,
         V3D_QPU_A_VPMSETUP,
         V3D_QPU_A_VPMWT,

diff --git a/src/broadcom/qpu/qpu_pack.c b/src/broadcom/qpu/qpu_pack.c
index 60ed2d697cb29c8ae3f23f2ed1c01b868c28ce82..4615fd35d0692187ec3e17b950a921123f0aa2d6 100644 (file)
--- a/src/broadcom/qpu/qpu_pack.c
+++ b/src/broadcom/qpu/qpu_pack.c
@@ -514,7 +514,7 @@ static const struct opcode_desc add_ops[] = {
         { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_VDWWT, 33 },
         { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_IID, 40 },
         { 187, 187, 1 << 2, 1 << 3, V3D_QPU_A_SAMPID, 40 },
-        { 187, 187, 1 << 2, 1 << 4, V3D_QPU_A_PATCHID, 40 },
+        { 187, 187, 1 << 2, 1 << 4, V3D_QPU_A_BARRIERID, 40 },
         { 187, 187, 1 << 2, 1 << 5, V3D_QPU_A_TMUWT },
         { 187, 187, 1 << 2, 1 << 6, V3D_QPU_A_VPMWT },
 

diff --git a/src/broadcom/qpu/tests/qpu_disasm.c b/src/broadcom/qpu/tests/qpu_disasm.c
index a8e803ad815eb0cc87ded8e79c073b2823ecaa37..814e032bf1cfd269a895e769cb135aeaef3b05be 100644 (file)
--- a/src/broadcom/qpu/tests/qpu_disasm.c
+++ b/src/broadcom/qpu/tests/qpu_disasm.c
@@ -82,6 +82,9 @@ static const struct {
         { 41, 0x3de020c7bdfd200dull, "ldvpmg_in  rf7, r2, r2; mov  r3, 13" },
         { 41, 0x3de02040f8ff7201ull, "stvpmv  1, rf8       ; mov  r1, 1" },
         { 41, 0xd8000e50bb2d3000ull, "sampid  rf16         ; fmul  rf57.h, r3, r1.l" },
+
+        /* v4.2 changes */
+        { 42, 0x3c203192bb814000ull, "barrierid  syncb     ; nop               ; thrsw" },
 };
 
 static void