soc: increase default BIOS size

diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index ef7c454549c2d3d23d216114eeb9a1ab8bc8f608..0280cba7975c72c012f51bea63313e78fdece83c 100644 (file)
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -146,7 +146,7 @@ class SoC(Module):
         if size is not None:
             self.add_memory_region(name, address, size)
 
-    def register_rom(self, interface, rom_size=0xa000):
+    def register_rom(self, interface, rom_size=0x10000):
         self.add_wb_slave(mem_decoder(self.mem_map["rom"]), interface)
         self.add_memory_region("rom", self.cpu_reset_address, rom_size)