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diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index be9a5069ddd9debdd5d3ac61d724e54dfdcf345a..1d2fa4ae58d4ca03dc2f0bab01648608763ecb1a 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -28,8 +28,8 @@ Modes apply to Arithmetic and Logical SVP64 operations:
   *VL is altered as a result*.
 * **sat mode** or saturation: clamps each element result to a min/max rather than overflows / wraps.  allows signed and unsigned clamping for both INT
 and FP.
-* **reduce mode**. if used correftly, a mapreduce (or a prefix sum)
-  is performed.    see [[svp64/appendix]]:
+* **reduce mode**. if used correctly, a mapreduce (or a prefix sum)
+  is performed.    see [[svp64/appendix]].
   note that there are comprehensive caveats when using this mode.
 * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch conditional testing) and if the test fails it
 is as if the