radeonsi: don't set RB+ registers on GFX9 chips without RB+
authorMarek Olšák <marek.olsak@amd.com>
Sat, 7 Apr 2018 15:53:26 +0000 (11:53 -0400)
committerMarek Olšák <marek.olsak@amd.com>
Mon, 9 Apr 2018 17:40:25 +0000 (13:40 -0400)
CLEAR_STATE initializes them properly.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
src/gallium/drivers/radeonsi/si_state.c

index c4fb254c2ef637a0db2e9d961ebde5f449e5dc0b..2924a72f48d5c2d715c0409e28de9517e204bd9e 100644 (file)
@@ -265,11 +265,6 @@ static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *a
                radeon_emit(cs, sx_ps_downconvert);     /* R_028754_SX_PS_DOWNCONVERT */
                radeon_emit(cs, sx_blend_opt_epsilon);  /* R_028758_SX_BLEND_OPT_EPSILON */
                radeon_emit(cs, sx_blend_opt_control);  /* R_02875C_SX_BLEND_OPT_CONTROL */
-       } else if (sctx->screen->has_rbplus) {
-               radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
-               radeon_emit(cs, 0);     /* R_028754_SX_PS_DOWNCONVERT */
-               radeon_emit(cs, 0);     /* R_028758_SX_BLEND_OPT_EPSILON */
-               radeon_emit(cs, 0);     /* R_02875C_SX_BLEND_OPT_CONTROL */
        }
 }
 
@@ -628,7 +623,7 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
                color_control |= S_028808_MODE(V_028808_CB_DISABLE);
        }
 
-       if (sctx->screen->has_rbplus) {
+       if (sctx->screen->rbplus_allowed) {
                /* Disable RB+ blend optimizations for dual source blending.
                 * Vulkan does this.
                 */