(no commit message)

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index cdf3b53f9efa9ae8acd51f067fc118d5fb36b61e..7f667c5bde837d215bdd8bb5662c0a649071332e 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -629,18 +629,20 @@ As pointed out in the [[sv/ldst]] page there is limited space in only
 * LD/ST Immediate has no individual control over src/dest zeroing,
   whereas LD/ST Indexed does.
 * LD/ST Immediate has no Saturated Pack/Unpack (Arithmetic Mode does)
-* LD/ST Indexed has no Pack/Unpack (REMAP may be used instead)
+* LD/ST Indexed has no Pack/Unpack, whereas LD/ST Immediate does.
 
 These are not insurmountable problems: there do exist workarounds.
 For example it is possible to set up Matrix REMAP to perform the same
 job as Pack/Unpack, at which point the LD/ST "Saturation" mode may
-be used, saving on costly intermediary registers at double the LD
-width if a Saturated MV had to be involved.
+be used, saving on costly intermediary registers *at double the LD
+width* if a Saturated MV had to be involved. Store on the other hand
+it is extremely likely that an arithmetic operation already computed
+a Saturated Vector of results, so is less of a problem than Load.
 
 Also, the LD/ST Indexed Mode can be element-strided (RB as
 a Scalar, times
 the element index), or, if that is not enough,
-although potentially costly it may be possible to
+although potentially costly it is possible to
 use `svstep` to compute a Vector RB sequence of
 Indices, then activate either `sz` or `dz` as required, as a workaround
 for LDST Immediate only having `zz`.