[AArch64] Pass a mode to some SVE immediate queries

It helps the SVE2 ACLE support if aarch64_sve_arith_immediate_p and
aarch64_sve_sqadd_sqsub_immediate_p accept scalars as well as vectors.

2020-01-09  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p)
	(aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument.
	* config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p)
	(aarch64_sve_sqadd_sqsub_immediate_p): Likewise.  Handle scalar
	immediates as well as vector ones.
	* config/aarch64/predicates.md (aarch64_sve_arith_immediate)
	(aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate)
	(aarch64_sve_qsub_immediate): Update calls accordingly.

From-SVN: r280059

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8910d8622bf2269e76eeaf4855ba5a777a000f40..de59d4c098528ab305153e8a783717ed6a8f56be 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2020-01-09  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p)
+       (aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument.
+       * config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p)
+       (aarch64_sve_sqadd_sqsub_immediate_p): Likewise.  Handle scalar
+       immediates as well as vector ones.
+       * config/aarch64/predicates.md (aarch64_sve_arith_immediate)
+       (aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate)
+       (aarch64_sve_qsub_immediate): Update calls accordingly.
+
 2020-01-09  Richard Sandiford  <richard.sandiford@arm.com>
 
        * config/aarch64/aarch64-sve2.md: Add banner comments.

diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index a4004309fdb848b9fb4227511ea41f37abf603d7..3c9e5da6e15820a25a3012a4dad66c31959f4997 100644 (file)
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -550,8 +550,8 @@ bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *,
                        enum simd_immediate_check w = AARCH64_CHECK_MOV);
 rtx aarch64_check_zero_based_sve_index_immediate (rtx);
 bool aarch64_sve_index_immediate_p (rtx);
-bool aarch64_sve_arith_immediate_p (rtx, bool);
-bool aarch64_sve_sqadd_sqsub_immediate_p (rtx, bool);
+bool aarch64_sve_arith_immediate_p (machine_mode, rtx, bool);
+bool aarch64_sve_sqadd_sqsub_immediate_p (machine_mode, rtx, bool);
 bool aarch64_sve_bitmask_immediate_p (rtx);
 bool aarch64_sve_dup_immediate_p (rtx);
 bool aarch64_sve_cmp_immediate_p (rtx, bool);

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index e3bbf128736d65d0305357d7887b608c618ddee5..f83764fc420f799bc3fca556cd03168739985e61 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -16407,22 +16407,20 @@ aarch64_sve_index_immediate_p (rtx base_or_step)
          && IN_RANGE (INTVAL (base_or_step), -16, 15));
 }
 
-/* Return true if X is a valid immediate for the SVE ADD and SUB
-   instructions.  Negate X first if NEGATE_P is true.  */
+/* Return true if X is a valid immediate for the SVE ADD and SUB instructions
+   when applied to mode MODE.  Negate X first if NEGATE_P is true.  */
 
 bool
-aarch64_sve_arith_immediate_p (rtx x, bool negate_p)
+aarch64_sve_arith_immediate_p (machine_mode mode, rtx x, bool negate_p)
 {
-  rtx elt;
-
-  if (!const_vec_duplicate_p (x, &elt)
-      || !CONST_INT_P (elt))
+  rtx elt = unwrap_const_vec_duplicate (x);
+  if (!CONST_INT_P (elt))
     return false;
 
   HOST_WIDE_INT val = INTVAL (elt);
   if (negate_p)
     val = -val;
-  val &= GET_MODE_MASK (GET_MODE_INNER (GET_MODE (x)));
+  val &= GET_MODE_MASK (GET_MODE_INNER (mode));
 
   if (val & 0xff)
     return IN_RANGE (val, 0, 0xff);
@@ -16430,23 +16428,19 @@ aarch64_sve_arith_immediate_p (rtx x, bool negate_p)
 }
 
 /* Return true if X is a valid immediate for the SVE SQADD and SQSUB
-   instructions.  Negate X first if NEGATE_P is true.  */
+   instructions when applied to mode MODE.  Negate X first if NEGATE_P
+   is true.  */
 
 bool
-aarch64_sve_sqadd_sqsub_immediate_p (rtx x, bool negate_p)
+aarch64_sve_sqadd_sqsub_immediate_p (machine_mode mode, rtx x, bool negate_p)
 {
-  rtx elt;
-
-  if (!const_vec_duplicate_p (x, &elt)
-      || !CONST_INT_P (elt))
-    return false;
-
-  if (!aarch64_sve_arith_immediate_p (x, negate_p))
+  if (!aarch64_sve_arith_immediate_p (mode, x, negate_p))
     return false;
 
   /* After the optional negation, the immediate must be nonnegative.
      E.g. a saturating add of -127 must be done via SQSUB Zn.B, Zn.B, #127
      instead of SQADD Zn.B, Zn.B, #129.  */
+  rtx elt = unwrap_const_vec_duplicate (x);
   return negate_p == (INTVAL (elt) < 0);
 }
 

diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 23605b6754f3c252eb9a3cfc376671eb665f5fda..8e8c5ee5cd8e0daa932db437edf8af0cafa148a8 100644 (file)
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -636,19 +636,19 @@
 
 (define_predicate "aarch64_sve_arith_immediate"
   (and (match_code "const,const_vector")
-       (match_test "aarch64_sve_arith_immediate_p (op, false)")))
+       (match_test "aarch64_sve_arith_immediate_p (mode, op, false)")))
 
 (define_predicate "aarch64_sve_sub_arith_immediate"
   (and (match_code "const,const_vector")
-       (match_test "aarch64_sve_arith_immediate_p (op, true)")))
+       (match_test "aarch64_sve_arith_immediate_p (mode, op, true)")))
 
 (define_predicate "aarch64_sve_qadd_immediate"
   (and (match_code "const,const_vector")
-       (match_test "aarch64_sve_sqadd_sqsub_immediate_p (op, false)")))
+       (match_test "aarch64_sve_sqadd_sqsub_immediate_p (mode, op, false)")))
 
 (define_predicate "aarch64_sve_qsub_immediate"
   (and (match_code "const,const_vector")
-       (match_test "aarch64_sve_sqadd_sqsub_immediate_p (op, true)")))
+       (match_test "aarch64_sve_sqadd_sqsub_immediate_p (mode, op, true)")))
 
 (define_predicate "aarch64_sve_vector_inc_dec_immediate"
   (and (match_code "const,const_vector")