(no commit message)

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 1e14c7748e1605e5dfe63051a60974c9253697d4..493fb3f24ae0af7c85c36e41ef2e7a4578316213 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -940,7 +940,8 @@ required.*
 
 Some operations in the Power ISA already target two 64-bit scalar
 registers: `lq` for example. Some mathematical algorithms are more
-efficient when there are two outputs rather than one.  64-bit multiply
+efficient when there are two outputs rather than one, providing
+feedback loops between elements.  64-bit multiply
 for example actually internally produces a 128 bit result, which clearly
 cannot be stored in a single 64 bit register.  Some ISAs recommend
 "macro op fusion": the practice of setting a convention whereby if
@@ -950,8 +951,13 @@ selects the high part, then optimised micro-architectures may
 "fuse" those two instructions together, using Micro-coding techniques,
 internally.
 
-Macro-op fusion would be perfect for Scalar Multiply Lo/Hi if it
-was not for SVP64 Horizontal-First Loops.
+The practice and convention of macro-op fusion however is not compatible
+with SVP64 Horizontal-First, because Horizontal Mode may only
+be applied to a single instruction at a time.  Thus it becomes
+necessary to add explicit more complex single instructions with
+more operands than would normally be seen in another ISA. If it
+was not for Power ISA already having LD/ST with update as well as
+Condition Codes and `lq` this would be hard to justify.
 
 * [[isa/svfixedarith]]
 * [[isa/svfparith]]