RISC-V: Fix riscv gas/ld testsuites failures for big endian.

Add riscv_choose_[ilp32|lp64]_emul, and use them to choose the correct
linker script rather than set elf[32|64]lriscv directly.

gas/
    * testsuite/gas/riscv/li32.d: Accept bigriscv in addition
    to littleriscv.
    * testsuite/gas/riscv/li64.d: Likewise.
    * testsuite/gas/riscv/lla32.d: Likewise.
    * testsuite/gas/riscv/lla64.d: Likewise.
    * testsuite/gas/riscv/march-ok-g2.d: Likewise.
    * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
    * testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
    * testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
    * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
    * testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise.
    * testsuite/gas/riscv/march-ok-two-nse.d: Likewise.

ld/
    * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added
    riscv_choose_[ilp32|lp64]_emul to choose the correct linker script.
    * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call
    riscv_choose_[ilp32|lp64]_emul instead of hardcoding elf[32|64]lriscv.
    * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise.
    * testsuite/ld-riscv-elf/c-lui-2.d: Likewise.
    * testsuite/ld-riscv-elf/c-lui.d: Likewise.
    * testsuite/ld-riscv-elf/call-relax.d: Likewise.
    * testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise.
    * testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise.
    * testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition
    to littleriscv.
    * testsuite/ld-riscv-elf/weakref64.d: Likewise.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 57bc038a563c520635911d96229dcef3f5e2014c..4c500edaa87af525356b27ab1e6b6d9064a6d000 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,18 @@
+2021-01-06  Marcus Comstedt  <marcus@mc.pp.se>
+
+       * testsuite/gas/riscv/li32.d: Accept bigriscv in addition
+       to littleriscv.
+       * testsuite/gas/riscv/li64.d: Likewise.
+       * testsuite/gas/riscv/lla32.d: Likewise.
+       * testsuite/gas/riscv/lla64.d: Likewise.
+       * testsuite/gas/riscv/march-ok-g2.d: Likewise.
+       * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
+       * testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
+       * testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
+       * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
+       * testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise.
+       * testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
+
 2021-01-06  Marcus Comstedt  <marcus@mc.pp.se>
 
        * config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv and

diff --git a/gas/testsuite/gas/riscv/li32.d b/gas/testsuite/gas/riscv/li32.d
index ff0827dde996b29b2d8feb9055e817d7f94de96e..947ea4f754a7b165cdd1bbf423a0850808a05f02 100644 (file)
--- a/gas/testsuite/gas/riscv/li32.d
+++ b/gas/testsuite/gas/riscv/li32.d
@@ -1,7 +1,7 @@
 #as: -march=rv32ic -mabi=ilp32
 #objdump: -dr
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv
 
 
 Disassembly of section .text:

diff --git a/gas/testsuite/gas/riscv/li64.d b/gas/testsuite/gas/riscv/li64.d
index 54213031cc51d230b3b4b7ea16ffcc5c25d67950..498b2e513d98567bb5c1bcb3f95808c550257096 100644 (file)
--- a/gas/testsuite/gas/riscv/li64.d
+++ b/gas/testsuite/gas/riscv/li64.d
@@ -1,7 +1,7 @@
 #as: -march=rv64ic -mabi=lp64
 #objdump: -dr
 
-.*:     file format elf64-littleriscv
+.*:     file format elf64-(little|big)riscv
 
 
 Disassembly of section .text:

diff --git a/gas/testsuite/gas/riscv/lla32.d b/gas/testsuite/gas/riscv/lla32.d
index ab766b4e3b6272db4b4b433dd2e904a9e25d8f73..9d8756290642617be041714cc78648674a2e4e49 100644 (file)
--- a/gas/testsuite/gas/riscv/lla32.d
+++ b/gas/testsuite/gas/riscv/lla32.d
@@ -1,7 +1,7 @@
 #as: -march=rv32i -mabi=ilp32
 #objdump: -dr
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv
 
 
 Disassembly of section .text:

diff --git a/gas/testsuite/gas/riscv/lla64.d b/gas/testsuite/gas/riscv/lla64.d
index 7848eecdfb032adc951f7401eb02dc31e8b4f69f..c3b958186253fb93ee2f661d7c395b35c84e41a5 100644 (file)
--- a/gas/testsuite/gas/riscv/lla64.d
+++ b/gas/testsuite/gas/riscv/lla64.d
@@ -1,7 +1,7 @@
 #as: -march=rv64i -mabi=lp64
 #objdump: -dr
 
-.*:     file format elf64-littleriscv
+.*:     file format elf64-(little|big)riscv
 
 
 Disassembly of section .text:

diff --git a/gas/testsuite/gas/riscv/march-ok-g2.d b/gas/testsuite/gas/riscv/march-ok-g2.d
index 38541ad6a6c9c5fff9458056582bcfcb2157b8a0..7c92bc8bcb149953ccb833115d50482f085f875d 100644 (file)
--- a/gas/testsuite/gas/riscv/march-ok-g2.d
+++ b/gas/testsuite/gas/riscv/march-ok-g2.d
@@ -2,4 +2,4 @@
 #objdump: -dr
 #source: empty.s
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv

diff --git a/gas/testsuite/gas/riscv/march-ok-g2_p1.d b/gas/testsuite/gas/riscv/march-ok-g2_p1.d
index cd9e127e66958139864f404b4a665427018c7395..da2247c9d9e8f5622627406280ca9ee9b54f4a17 100644 (file)
--- a/gas/testsuite/gas/riscv/march-ok-g2_p1.d
+++ b/gas/testsuite/gas/riscv/march-ok-g2_p1.d
@@ -2,4 +2,4 @@
 #objdump: -dr
 #source: empty.s
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv

diff --git a/gas/testsuite/gas/riscv/march-ok-g2p0.d b/gas/testsuite/gas/riscv/march-ok-g2p0.d
index b439314ccf52e95f1a7f3f4e208b3e0533ce4a0f..a11d55e4990a58f278d85fa6e4f3961780313529 100644 (file)
--- a/gas/testsuite/gas/riscv/march-ok-g2p0.d
+++ b/gas/testsuite/gas/riscv/march-ok-g2p0.d
@@ -2,4 +2,4 @@
 #objdump: -dr
 #source: empty.s
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv

diff --git a/gas/testsuite/gas/riscv/march-ok-i2p0.d b/gas/testsuite/gas/riscv/march-ok-i2p0.d
index eb8309c7e2837d5d8c9f352663ccbcc1e601678d..e413e09f88d87b8f6732e0b318921b97066ecc9e 100644 (file)
--- a/gas/testsuite/gas/riscv/march-ok-i2p0.d
+++ b/gas/testsuite/gas/riscv/march-ok-i2p0.d
@@ -2,4 +2,4 @@
 #objdump: -dr
 #source: empty.s
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv

diff --git a/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d b/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d
index 6658417b0fb97d063e277bee84eac88ea1974455..11960ba5bfa0d1657dc3c93c2f6db674fa90f0a0 100644 (file)
--- a/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d
+++ b/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d
@@ -2,4 +2,4 @@
 #objdump: -dr
 #source: empty.s
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv

diff --git a/gas/testsuite/gas/riscv/march-ok-nse-with-version.d b/gas/testsuite/gas/riscv/march-ok-nse-with-version.d
index bdca7fb18db0e9c57d347d898bcc6cab44dd999b..8e2110cef4ec875c4cf7d7667b1d8a99188e2bed 100644 (file)
--- a/gas/testsuite/gas/riscv/march-ok-nse-with-version.d
+++ b/gas/testsuite/gas/riscv/march-ok-nse-with-version.d
@@ -2,4 +2,4 @@
 #objdump: -dr
 #source: empty.s
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv

diff --git a/gas/testsuite/gas/riscv/march-ok-two-nse.d b/gas/testsuite/gas/riscv/march-ok-two-nse.d
index e78cf9dd09bed2a968430b4e7084c36158df236f..8cdf316f048b275109cedc244e8bb5cb79b2d287 100644 (file)
--- a/gas/testsuite/gas/riscv/march-ok-two-nse.d
+++ b/gas/testsuite/gas/riscv/march-ok-two-nse.d
@@ -2,4 +2,4 @@
 #objdump: -dr
 #source: empty.s
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv

diff --git a/ld/ChangeLog b/ld/ChangeLog
index 2e51333bb1b353f1e928e1f4d4727c9a6f5f0535..23a07195318ecdb43e18e16cb96f61191514cfe3 100644 (file)
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,22 @@
+2021-01-06  Marcus Comstedt  <marcus@mc.pp.se>
+
+       * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added
+       riscv_choose_[ilp32|lp64]_emul to choose the correct linker script.
+       * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call
+       riscv_choose_[ilp32|lp64]_emul instead of hardcoding elf[32|64]lriscv.
+       * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
+       * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
+       * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise.
+       * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise.
+       * testsuite/ld-riscv-elf/c-lui-2.d: Likewise.
+       * testsuite/ld-riscv-elf/c-lui.d: Likewise.
+       * testsuite/ld-riscv-elf/call-relax.d: Likewise.
+       * testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise.
+       * testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise.
+       * testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition
+       to littleriscv.
+       * testsuite/ld-riscv-elf/weakref64.d: Likewise.
+
 2021-01-06  Marcus Comstedt  <marcus@mc.pp.se>
 
        * configure.tgt: Added riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*,

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
index 5baaba4c16f9545cd25dfd59fadfbbf0869dedeb..c148cdbc4f425fe07449794cdc2c0859c22a3990 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
@@ -1,7 +1,7 @@
 #source: attr-merge-arch-01a.s
 #source: attr-merge-arch-01b.s
 #as:
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
 #readelf: -A
 
 Attribute Section: riscv

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
index a7d79a1ea2bf7bf0dd44eb3105228a7e8dcdd555..bc0e0fd13841f113887c79a13d69531655a0b032 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
@@ -1,7 +1,7 @@
 #source: attr-merge-arch-02a.s
 #source: attr-merge-arch-02b.s
 #as:
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
 #readelf: -A
 
 Attribute Section: riscv

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
index d46dee808de3637e268c0014e6b304ee23e8d4a0..374a043c69ed9613365651dd56e2b622cc2a6c61 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
@@ -1,7 +1,7 @@
 #source: attr-merge-arch-03a.s
 #source: attr-merge-arch-03b.s
 #as:
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
 #readelf: -A
 
 Attribute Section: riscv

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
index 4b312388f72e5d8799b6f13e61c8e0b5dd9e3955..669a13920677adc05ac1885ef19899e1d52af9c7 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
@@ -1,7 +1,7 @@
 #source: attr-merge-arch-failed-01a.s
 #source: attr-merge-arch-failed-01b.s
 #as: -march-attr
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
 #warning: .*mis-matched ISA version 3.0 for 'a' extension, the output version is 2.0
 #readelf: -A
 

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
index 880ee1547379684814ef41debf6df8f6a67cf73a..3f4935df54c7b08ce4c73de1aaf46edf333d475a 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
@@ -3,7 +3,7 @@
 #source: attr-merge-arch-failed-02c.s
 #source: attr-merge-arch-failed-02d.s
 #as: -march-attr
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
 #warning: .*mis-matched ISA version 3.0 for 'i' extension, the output version is 2.0
 #warning: .*mis-matched ISA version 3.0 for 'm' extension, the output version is 2.0
 #warning: .*mis-matched ISA version 3.0 for 'a' extension, the output version is 2.0

diff --git a/ld/testsuite/ld-riscv-elf/c-lui-2.d b/ld/testsuite/ld-riscv-elf/c-lui-2.d
index 622c0f7a31db5ac73fc25dfa2cacc0550fac0f55..d363da10c33ddcee4748e8581de0ebf99af330c8 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/c-lui-2.d
+++ b/ld/testsuite/ld-riscv-elf/c-lui-2.d
@@ -1,7 +1,7 @@
 #name: c.lui to c.li relaxation
 #source: c-lui-2.s
 #as: -march=rv32ic
-#ld: -melf32lriscv -Tc-lui-2.ld
+#ld: -m[riscv_choose_ilp32_emul] -Tc-lui-2.ld
 #objdump: -d -M no-aliases,numeric
 
 .*:     file format .*

diff --git a/ld/testsuite/ld-riscv-elf/c-lui.d b/ld/testsuite/ld-riscv-elf/c-lui.d
index 382eca88dc204a19103c054472b94e7fbf7341fb..f1cf0b42c309597a3a6868341328520b11669a9b 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/c-lui.d
+++ b/ld/testsuite/ld-riscv-elf/c-lui.d
@@ -1,7 +1,7 @@
 #name: lui to c.lui relaxation
 #source: c-lui.s
 #as: -march=rv32ic
-#ld: -melf32lriscv
+#ld: -m[riscv_choose_ilp32_emul]
 #objdump: -d -M no-aliases,numeric
 
 .*:     file format .*

diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d
index 597ff67535353415653fa3942459b096298b2163..c6022bec262a4a5bf1aaf46a294af4784bb12d45 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/call-relax.d
+++ b/ld/testsuite/ld-riscv-elf/call-relax.d
@@ -4,6 +4,6 @@
 #source: call-relax-2.s
 #source: call-relax-3.s
 #as: -march=rv32ic -mno-arch-attr
-#ld: -melf32lriscv
+#ld: -m[riscv_choose_ilp32_emul]
 #objdump: -d
 #pass

diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index eb3df7673ac924481c4ecf17ea0ce47ee125cdd4..7081af1e8e3622abf76e4c2c8f1e77e66aff7e07 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -19,6 +19,24 @@
 # MA 02110-1301, USA.
 #
 
+proc riscv_choose_ilp32_emul {} {
+    if { [istarget "riscvbe-*"] \
+        || [istarget "riscv32be-*"] \
+        || [istarget "riscv64be-*"] } {
+        return "elf32briscv"
+    }
+    return "elf32lriscv"
+}
+
+proc riscv_choose_lp64_emul {} {
+    if { [istarget "riscvbe-*"] \
+        || [istarget "riscv32be-*"] \
+        || [istarget "riscv64be-*"] } {
+        return "elf64briscv"
+    }
+    return "elf64lriscv"
+}
+
 # target: rv32 or rv64.
 # output: Which output you want?  (exe, pie, .so)
 proc run_dump_test_ifunc { name target output} {
@@ -42,11 +60,11 @@ proc run_dump_test_ifunc { name target output} {
     switch -- $target {
        rv32 {
            set asflags "$asflags -march=rv32i -mabi=ilp32"
-           set ldflags "$ldflags -melf32lriscv"
+           set ldflags "$ldflags -m[riscv_choose_ilp32_emul]"
        }
        rv64 {
            set asflags "$asflags -march=rv64i -mabi=lp64 -defsym __64_bit__=1"
-           set ldflags "$ldflags -melf64lriscv"
+           set ldflags "$ldflags -m[riscv_choose_lp64_emul]"
        }
     }
 
@@ -89,21 +107,20 @@ if [istarget "riscv*-*-*"] {
     run_dump_test "attr-merge-priv-spec-failed-04"
     run_dump_test "attr-merge-priv-spec-failed-05"
     run_dump_test "attr-merge-priv-spec-failed-06"
-    run_ld_link_tests {
-       { "Weak reference 32" "-T weakref.ld -melf32lriscv" ""
-           "-march=rv32i -mabi=ilp32" {weakref32.s}
-           {{objdump -d weakref32.d}} "weakref32"}
-       { "Weak reference 64" "-T weakref.ld -melf64lriscv" ""
-           "-march=rv64i -mabi=lp64" {weakref64.s}
-           {{objdump -d weakref64.d}} "weakref64"}
-    }
+    run_ld_link_tests [list \
+       [list "Weak reference 32" "-T weakref.ld -m[riscv_choose_ilp32_emul]" "" \
+           "-march=rv32i -mabi=ilp32" {weakref32.s} \
+           {{objdump -d weakref32.d}} "weakref32"] \
+       [list "Weak reference 64" "-T weakref.ld -m[riscv_choose_lp64_emul]" "" \
+           "-march=rv64i -mabi=lp64" {weakref64.s} \
+           {{objdump -d weakref64.d}} "weakref64"]]
 
     # The following tests require shared library support.
     if ![check_shared_lib_support] {
        return
     }
 
-    set abis { rv32gc ilp32 elf32lriscv rv64gc lp64 elf64lriscv }
+    set abis [list rv32gc ilp32 [riscv_choose_ilp32_emul] rv64gc lp64 [riscv_choose_lp64_emul]]
     foreach { arch abi emul } $abis {
        # This checks whether our linker scripts handle __global_pointer$
        # correctly.  It should be defined in executables and PIE, but not

diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d
index 039de102c3ade82438a0067380b351157e7ebb99..895c6cc5814cbb7b51d3d09e9a6f6ce28642cd1d 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d
+++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d
@@ -1,5 +1,5 @@
 #name: %pcrel_lo overflow with an addend
 #source: pcrel-lo-addend-2.s
 #as: -march=rv32ic
-#ld: -melf32lriscv --no-relax
+#ld: -m[riscv_choose_ilp32_emul] --no-relax
 #error: .*dangerous relocation: %pcrel_lo overflow with an addend

diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d
index ad658be844ea903a4ad33b1ac0c48a3e665a7c16..92d41528a4a3430726a16a67ccd179fa8c1d5357 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d
+++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d
@@ -1,5 +1,5 @@
 #name: %pcrel_lo section symbol with an addend
 #source: pcrel-lo-addend.s
 #as: -march=rv32ic
-#ld: -melf32lriscv
+#ld: -m[riscv_choose_ilp32_emul]
 #error: .*dangerous relocation: %pcrel_lo section symbol with an addend

diff --git a/ld/testsuite/ld-riscv-elf/weakref32.d b/ld/testsuite/ld-riscv-elf/weakref32.d
index eaeb6dae7e358aa93eac557e45fc522351bfb128..279481d2233156e519f754e6e6962e944b8e48f2 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/weakref32.d
+++ b/ld/testsuite/ld-riscv-elf/weakref32.d
@@ -1,5 +1,5 @@
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv
 
 
 Disassembly of section \.text:

diff --git a/ld/testsuite/ld-riscv-elf/weakref64.d b/ld/testsuite/ld-riscv-elf/weakref64.d
index cc718a91a31f9a60b197ec4deda2b3c228c8c5e5..c8f4c103398c753ad8aa2cd637c320a685fbb103 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/weakref64.d
+++ b/ld/testsuite/ld-riscv-elf/weakref64.d
@@ -1,5 +1,5 @@
 
-.*:     file format elf64-littleriscv
+.*:     file format elf64-(little|big)riscv
 
 
 Disassembly of section \.text: