re PR target/80569 (i686: "shrx" instruction generated in 16-bit mode)
authorUros Bizjak <uros@gcc.gnu.org>
Sun, 23 Jul 2017 10:28:26 +0000 (12:28 +0200)
committerUros Bizjak <uros@gcc.gnu.org>
Sun, 23 Jul 2017 10:28:26 +0000 (12:28 +0200)
PR target/80569
* config/i386/i386.c (ix86_option_override_internal): Disable
BMI, BMI2 and TBM instructions for -m16.

testsuite/ChangeLog:

PR target/80569
* gcc.target/i386/pr80569.c: New test.

From-SVN: r250459

gcc/ChangeLog
gcc/config/i386/i386.c
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/i386/pr80569.c [new file with mode: 0644]

index 8ec7a798b1d066131af5b9b8f10f5d691b562e4e..4554109cc391c70ea108f910550b74ba85efe154 100644 (file)
@@ -1,3 +1,9 @@
+2017-07-23  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/80569
+       * config/i386/i386.c (ix86_option_override_internal): Disable
+       BMI, BMI2 and TBM instructions for -m16.
+
 2017-07-21  Carl Love  <cel@us.ibm.com>
 
        * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
 
 2017-07-18  Robin Dapp  <rdapp@linux.vnet.ibm.com>
 
-        * tree-vect-data-refs.c (vect_enhance_data_refs_alignment): Remove
+       * tree-vect-data-refs.c (vect_enhance_data_refs_alignment): Remove
        body_cost_vec from _vect_peel_extended_info.
        (vect_peeling_hash_get_lowest_cost): Do not set body_cost_vec.
-        (vect_peeling_hash_choose_best_peeling): Remove body_cost_vec and
+       (vect_peeling_hash_choose_best_peeling): Remove body_cost_vec and
        npeel.
 
 2017-07-18  Bin Cheng  <bin.cheng@arm.com>
 
 2017-07-17  Yury Gribov  <tetra2005@gmail.com>
 
-        * tree-vrp.c (compare_assert_loc): Fix comparison function
+       * tree-vrp.c (compare_assert_loc): Fix comparison function
        to return predictable results.
 
 2017-07-17  Claudiu Zissulescu  <claziss@synopsys.com>
 2017-06-27  Jerome Lambourg  <lambourg@adacore.com>
 
        * config/vxworks.h (VXWORKS_LIBS_RTP): Alternative definition for
-       64bit configurations.
-       (PTR_DIFF_TYPE): Alternative definition for TARGET_LP64.
-       (SIZE_TYPE): Likewise.
-       * config/vxworks.c (vxworks_emutls_var_fields): Use
-       long_unsigned_type_node instead of unsigned_type_node as the offset
+       64bit configurations.
+       (PTR_DIFF_TYPE): Alternative definition for TARGET_LP64.
+       (SIZE_TYPE): Likewise.
+       * config/vxworks.c (vxworks_emutls_var_fields): Use
+       long_unsigned_type_node instead of unsigned_type_node as the offset
        field type, which is "pointer" mode in emutls.c.
 
 2017-06-27  Jakub Jelinek  <jakub@redhat.com>
index ca29135d39f8a2c5a686cbe17a6c9044095c49c8..b7ef5544bfd17b3c42a82ab93f22fa33ea2bf65d 100644 (file)
@@ -6284,6 +6284,12 @@ ix86_option_override_internal (bool main_args_p,
     opts->x_ix86_isa_flags
       |= OPTION_MASK_ISA_LZCNT & ~opts->x_ix86_isa_flags_explicit;
 
+  /* Disable BMI, BMI2 and TBM instructions for -m16.  */
+  if (TARGET_16BIT_P(opts->x_ix86_isa_flags))
+    opts->x_ix86_isa_flags
+      &= ~((OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_BMI2 | OPTION_MASK_ISA_TBM)
+          & ~opts->x_ix86_isa_flags_explicit);
+
   /* Validate -mpreferred-stack-boundary= value or default it to
      PREFERRED_STACK_BOUNDARY_DEFAULT.  */
   ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
index b36cd5e6778a05c30e73c0e7181d5018d58f2a40..026323570961c5b0225944c8aef93a15276e0447 100644 (file)
@@ -1,3 +1,8 @@
+2017-07-23  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/80569
+       * gcc.target/i386/pr80569.c: New test.
+
 2017-07-21  Carl Love  <cel@us.ibm.com>
 
        * gcc.target/powerpc/builtins-2.c (vmulosh, vmulouh, vmulesh,
diff --git a/gcc/testsuite/gcc.target/i386/pr80569.c b/gcc/testsuite/gcc.target/i386/pr80569.c
new file mode 100644 (file)
index 0000000..8e11c40
--- /dev/null
@@ -0,0 +1,9 @@
+/* PR target/80569 */
+/* { dg-do assemble } */
+/* { dg-options "-O2 -m16 -march=haswell" } */
+
+void load_kernel(void *setup_addr)
+{
+    unsigned int seg = (unsigned int)setup_addr >> 4;
+    asm("movl %0, %%es" : : "r"(seg));
+}