i965/gen6/gs: Implement GS_OPCODE_SET_DWORD_2.
authorIago Toral Quiroga <itoral@igalia.com>
Thu, 17 Jul 2014 06:54:03 +0000 (08:54 +0200)
committerIago Toral Quiroga <itoral@igalia.com>
Fri, 19 Sep 2014 13:01:15 +0000 (15:01 +0200)
We had GS_OPCODE_SET_DWORD_2_IMMED but this required its source argument to be
an immediate. In gen6 we need to set dword 2 of the URB write message header
from values stored in separate register, so we need something more flexible.
This change replaces GS_OPCODE_SET_DWORD_2_IMMED with GS_OPCODE_SET_DWORD_2.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
src/mesa/drivers/dri/i965/brw_defines.h
src/mesa/drivers/dri/i965/brw_shader.cpp
src/mesa/drivers/dri/i965/brw_vec4.h
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp

index 72a21e85d161aeec506ab49456873bbca5fa84b6..1e5a12b6a06c11ca943e10ebdb0dcfc473300b36 100644 (file)
@@ -984,11 +984,9 @@ enum opcode {
    GS_OPCODE_SET_VERTEX_COUNT,
 
    /**
-    * Set DWORD 2 of dst to the immediate value in src.  Used by geometry
-    * shaders to initialize DWORD 2 of R0, which needs to be 0 in order for
-    * scratch reads and writes to operate correctly.
+    * Set DWORD 2 of dst to the value in src.
     */
-   GS_OPCODE_SET_DWORD_2_IMMED,
+   GS_OPCODE_SET_DWORD_2,
 
    /**
     * Prepare the dst register for storage in the "Channel Mask" fields of a
index b23524684508b627a77d40a2fd6ee7b534d3871f..1c8bdb6ecd9c3ea6eecbfecc3e6c2032e389d624 100644 (file)
@@ -516,8 +516,8 @@ brw_instruction_name(enum opcode op)
       return "set_write_offset";
    case GS_OPCODE_SET_VERTEX_COUNT:
       return "set_vertex_count";
-   case GS_OPCODE_SET_DWORD_2_IMMED:
-      return "set_dword_2_immed";
+   case GS_OPCODE_SET_DWORD_2:
+      return "set_dword_2";
    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
       return "prepare_channel_masks";
    case GS_OPCODE_SET_CHANNEL_MASKS:
index cb863c8059567ed3e052d184d6cb0e56a44f84fb..82e91a9a50332fde4c62411fd0c801ac4615e97d 100644 (file)
@@ -653,7 +653,7 @@ private:
                                      struct brw_reg src1);
    void generate_gs_set_vertex_count(struct brw_reg dst,
                                      struct brw_reg src);
-   void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
+   void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
    void generate_gs_prepare_channel_masks(struct brw_reg dst);
    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
    void generate_gs_get_instance_id(struct brw_reg dst);
index ebc54916c122f10f805d8f238aadc1042bf6058e..168536cd5e22a6a7fb089fe9eed7d49e0ee46cda 100644 (file)
@@ -574,16 +574,12 @@ vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
 }
 
 void
-vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst,
-                                              struct brw_reg src)
+vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src)
 {
-   assert(src.file == BRW_IMMEDIATE_VALUE);
-
    brw_push_insn_state(p);
    brw_set_default_access_mode(p, BRW_ALIGN_1);
    brw_set_default_mask_control(p, BRW_MASK_DISABLE);
-   brw_MOV(p, suboffset(vec1(dst), 2), src);
-   brw_set_default_access_mode(p, BRW_ALIGN_16);
+   brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
    brw_pop_insn_state(p);
 }
 
@@ -1355,8 +1351,8 @@ vec4_generator::generate_code(const cfg_t *cfg)
          generate_gs_ff_sync(inst, dst, src[0]);
          break;
 
-      case GS_OPCODE_SET_DWORD_2_IMMED:
-         generate_gs_set_dword_2_immed(dst, src[0]);
+      case GS_OPCODE_SET_DWORD_2:
+         generate_gs_set_dword_2(dst, src[0]);
          break;
 
       case GS_OPCODE_PREPARE_CHANNEL_MASKS:
index ad3204fcfe2444dc16bc3dfae6ae64fa3b6383d3..e0fd420647415ff568f01a8cf2d55ae3e9ddf8b3 100644 (file)
@@ -149,7 +149,7 @@ vec4_gs_visitor::emit_prolog()
     */
    this->current_annotation = "clear r0.2";
    dst_reg r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD));
-   vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2_IMMED, r0, 0u);
+   vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, 0u);
    inst->force_writemask_all = true;
 
    /* Create a virtual register to hold the vertex count */