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Merge pull request #1386 from YosysHQ/clifford/fix1360
authorClifford Wolf <clifford@clifford.at>
Fri, 20 Sep 2019 11:30:28 +0000 (13:30 +0200)
committerGitHub <noreply@github.com>
Fri, 20 Sep 2019 11:30:28 +0000 (13:30 +0200)
Fix handling of read_verilog config in AstModule::reprocess_module()


Trivial merge