ifdefed ev5 vs. ev6 differences so Tlaser can work in the linux tree

arch/alpha/alpha_memory.cc:
arch/alpha/ev5.hh:
    Ifdefed TLASER code
arch/alpha/vtophys.cc:
    added back some code andrew removed and couldn't remember why.

--HG--
extra : convert_revision : f00d255f7a8a7bdb6e74f061dd014188e3b39e73

diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index f8be89cbe3fbda1045dee3036bf67aa2bd12d05f..a40ad7a5c80809293506bb66b06b476b92aa617d 100644 (file)
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -101,18 +101,34 @@ AlphaTLB::checkCacheability(MemReqPtr &req)
      * to catch a weird case where both are used, which shouldn't happen.
      */
 
+
+#ifdef ALPHA_TLASER
+    if (req->paddr & PA_UNCACHED_BIT_39) {
+#else
     if (req->paddr & PA_UNCACHED_BIT_43) {
+#endif
         // IPR memory space not implemented
-        if (PA_IPR_SPACE(req->paddr))
-            if (!req->xc->misspeculating())
-                panic("IPR memory space not implemented! PA=%x\n",
-                      req->paddr);
-
-        // mark request as uncacheable
-        req->flags |= UNCACHEABLE;
+        if (PA_IPR_SPACE(req->paddr)) {
+            if (!req->xc->misspeculating()) {
+                switch (req->paddr) {
+                  case ULL(0xFFFFF00188):
+                    req->data = 0;
+                    break;
+
+                  default:
+                    panic("IPR memory space not implemented! PA=%x\n",
+                          req->paddr);
+                }
+            }
+        } else {
+            // mark request as uncacheable
+            req->flags |= UNCACHEABLE;
 
-        // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
-        req->paddr &= PA_UNCACHED_MASK;
+#ifndef ALPHA_TLASER
+            // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
+            req->paddr &= PA_UNCACHED_MASK;
+#endif
+        }
     }
 }
 
@@ -301,7 +317,13 @@ AlphaITB::translate(MemReqPtr &req) const
 
         // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
         // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
+#ifdef ALPHA_TLASER
+        if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
+               VA_SPACE_EV5(req->vaddr) == 2) {
+#else
         if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
+#endif
+
 
             // only valid in kernel mode
             if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) {
@@ -312,11 +334,13 @@ AlphaITB::translate(MemReqPtr &req) const
 
             req->paddr = req->vaddr & PA_IMPL_MASK;
 
+#ifndef ALPHA_TLASER
             // sign extend the physical address properly
             if (req->paddr & PA_UNCACHED_BIT_40)
                 req->paddr |= ULL(0xf0000000000);
             else
                 req->paddr &= ULL(0xffffffffff);
+#endif
 
         } else {
             // not a physical address: need to look up pte
@@ -486,7 +510,12 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
         }
 
         // Check for "superpage" mapping
+#ifdef ALPHA_TLASER
+        if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
+               VA_SPACE_EV5(req->vaddr) == 2) {
+#else
         if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
+#endif
 
             // only valid in kernel mode
             if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
@@ -498,11 +527,13 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
 
             req->paddr = req->vaddr & PA_IMPL_MASK;
 
+#ifndef ALPHA_TLASER
             // sign extend the physical address properly
             if (req->paddr & PA_UNCACHED_BIT_40)
                 req->paddr |= ULL(0xf0000000000);
             else
                 req->paddr &= ULL(0xffffffffff);
+#endif
 
         } else {
             if (write)

diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh
index 517e1111f081d9cfb86b9102f1f0bfb674383d40..5b27dd3dcd979016ef0d6c1043073fbb1dea91b6 100644 (file)
--- a/arch/alpha/ev5.hh
+++ b/arch/alpha/ev5.hh
@@ -32,8 +32,15 @@
 #define ALT_MODE_AM(X)                 (((X) >> 3) & 0x3)
 
 #define DTB_CM_CM(X)                   (((X) >> 3) & 0x3)
+
+#ifdef ALPHA_TLASER
+#define DTB_ASN_ASN(X)          (((X) >> 57) & 0x7f)
+#define DTB_PTE_PPN(X)          (((X) >> 32) & 0x07ffffff)
+#else
 #define DTB_ASN_ASN(X)                 (((X) >> 57) & 0xff)
 #define DTB_PTE_PPN(X)                 (((X) >> 32) & 0x07fffffff)
+#endif
+
 #define DTB_PTE_XRE(X)                 (((X) >> 8) & 0xf)
 #define DTB_PTE_XWE(X)                 (((X) >> 12) & 0xf)
 #define DTB_PTE_FONR(X)                        (((X) >> 1) & 0x1)
@@ -41,9 +48,16 @@
 #define DTB_PTE_GH(X)                  (((X) >> 5) & 0x3)
 #define DTB_PTE_ASMA(X)                        (((X) >> 4) & 0x1)
 
-#define ICM_CM(X)                      (((X) >> 3) & 0x3)
+#define ICM_CM(X)                              (((X) >> 3) & 0x3)
+
+#ifdef ALPHA_TLASER
+#define ITB_ASN_ASN(X)          (((X) >> 4) & 0x7f)
+#define ITB_PTE_PPN(X)          (((X) >> 32) & 0x07ffffff)
+#else
 #define ITB_ASN_ASN(X)                 (((X) >> 4) & 0xff)
 #define ITB_PTE_PPN(X)                 (((X) >> 32) & 0x07fffffff)
+#endif
+
 #define ITB_PTE_XRE(X)                 (((X) >> 8) & 0xf)
 #define ITB_PTE_FONR(X)                        (((X) >> 1) & 0x1)
 #define ITB_PTE_FONW(X)                        (((X) >> 2) & 0x1)
@@ -52,18 +66,23 @@
 
 #define VA_UNIMPL_MASK                 ULL(0xfffff80000000000)
 #define VA_IMPL_MASK                   ULL(0x000007ffffffffff)
-#define VA_IMPL(X)                     ((X) & VA_IMPL_MASK)
-#define VA_VPN(X)                      (VA_IMPL(X) >> 13)
+#define VA_IMPL(X)                             ((X) & VA_IMPL_MASK)
+#define VA_VPN(X)                              (VA_IMPL(X) >> 13)
 #define VA_SPACE_EV5(X)                        (((X) >> 41) & 0x3)
-#define VA_SPACE_EV6(X)                (((X) >> 41) & 0x7f)
-#define VA_POFS(X)                     ((X) & 0x1fff)
+#define VA_SPACE_EV6(X)            (((X) >> 41) & 0x7f)
+#define VA_POFS(X)                             ((X) & 0x1fff)
 
-#define PA_IMPL_MASK                   ULL(0xfffffffffff) // for Tsunami
 #define PA_UNCACHED_BIT_39             ULL(0x8000000000)
 #define PA_UNCACHED_BIT_40             ULL(0x10000000000)
 #define PA_UNCACHED_BIT_43             ULL(0x80000000000)
 #define PA_UNCACHED_MASK                ULL(0x807ffffffff) // Clear PA<42:35>
+#ifdef ALPHA_TLASER
+#define PA_IPR_SPACE(X)         ((X) >= ULL(0xFFFFF00000))
+#define PA_IMPL_MASK                   ULL(0xffffffffff)
+#else
 #define PA_IPR_SPACE(X)                        ((X) >= ULL(0xFFFFFF00000))
+#define PA_IMPL_MASK                   ULL(0xfffffffffff) // for Tsunami
+#endif
 
 #define PA_PFN2PA(X)                   ((X) << 13)
 

diff --git a/arch/alpha/vtophys.cc b/arch/alpha/vtophys.cc
index cf2ebbf8034d7cc603e7302560545e7a58e09ffe..7a38b296b9a76c8be395112e268552855a7344cc 100644 (file)
--- a/arch/alpha/vtophys.cc
+++ b/arch/alpha/vtophys.cc
@@ -96,20 +96,23 @@ vtophys(ExecContext *xc, Addr vaddr)
 {
     Addr ptbr = xc->regs.ipr[AlphaISA::IPR_PALtemp20];
     Addr paddr = 0;
-//    if (PC_PAL(vaddr)) {
-//     paddr = vaddr & ~ULL(1);
-//    } else {
+    //@todo Andrew couldn't remember why he commented some of this code
+    //so I put it back in. Perhaps something to do with gdb debugging?
+    if (PC_PAL(vaddr)) {
+        paddr = vaddr & ~ULL(1);
+    } else if (!ptbr) {
+        paddr = vaddr;
+    } else {
         if (vaddr >= ALPHA_K0SEG_BASE && vaddr <= ALPHA_K0SEG_END) {
             paddr = ALPHA_K0SEG_TO_PHYS(vaddr);
-        } else if (!ptbr) {
-            paddr = vaddr;
         } else {
             Addr pte = kernel_pte_lookup(xc->physmem, ptbr, vaddr);
             uint64_t entry = xc->physmem->phys_read_qword(pte);
             if (pte && entry_valid(entry))
                 paddr = PMAP_PTE_PA(entry) | (vaddr & PGOFSET);
         }
-//    }
+    }
+
 
     DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);