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tests/xilinx: fix flaky mux test
author
Marcin Kościelnicki
<mwk@0x04.net>
Wed, 18 Dec 2019 14:53:20 +0000
(15:53 +0100)
committer
Marcin Kościelnicki
<mwk@0x04.net>
Wed, 18 Dec 2019 14:53:29 +0000
(15:53 +0100)
tests/arch/xilinx/mux.ys
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diff --git
a/tests/arch/xilinx/mux.ys
b/tests/arch/xilinx/mux.ys
index 821d0fab7381fa035f6446c68c9acc893879e5cf..388272449ca1870dba8ecbc880afac8d85d89922 100644
(file)
--- a/
tests/arch/xilinx/mux.ys
+++ b/
tests/arch/xilinx/mux.ys
@@
-40,6
+40,8
@@
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 5 t:LUT6
+select -assert-min 5 t:LUT6
+select -assert-max 7 t:LUT6
+select -assert-max 2 t:MUXF7
-select -assert-none t:LUT6 %% t:* %D
+select -assert-none t:LUT6
t:MUXF7
%% t:* %D