integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with...

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index bd896e0bdd6cef99849cd0f333e9f534d1023db3..127aecec8b340a3735716f32e19ffe81cb9d3d85 100755 (executable)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1001,4 +1001,5 @@ class LiteXSoC(SoC):
             self.add_config("L2_SIZE", l2_cache_size)
 
             # Wishbone Slave <--> LiteDRAM bridge --------------------------------------------------
-            self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port)
+            self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port,
+                base_address = self.bus.regions["main_ram"].origin)