(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index cd49217b5b494022a5bde5dd6b0da1c9212f8601..97f68aff4e1d99e388eb1348fc60b17081d11b02 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -263,6 +263,10 @@ Once the basics of this concept have sunk in, early
 advancements quickly follow naturally from analysis
 of the problem-space:
 
+* Expanding the size of GPR, FPR and CR register files to
+  provide 128 entries in each. This is a bare minimum for GPUs
+  in order to keep processing workloads as close to a LOAD-COMPUTE-STORE
+  batching as possible.
 * Predication (an absolutely critical component for a Vector ISA),
   then the next logical advancement is to allow separate predication masks
   to be applied to *both* the source *and* the destination, independently.