* <https://opencores.org/projects/sdr_ctrl>
* WIP <https://gitlab.com/jock_tanner/asceticore/-/blob/master/control.py#L24-31>
* simulation verilator https://github.com/ZipCPU/xulalx25soc/blob/master/bench/cpp/sdramsim.cpp
-* breakout board for FPGA <https://rlx.sk/en/breakout-boards-shields/5155-sdram-board-b-waveshare-8mx16bit-sdram-h57v1262gtr.html>
+* breakout board for FPGA
+ - <https://rlx.sk/en/breakout-boards-shields/5155-sdram-board-b-waveshare-8mx16bit-sdram-h57v1262gtr.html>
+ - <https://rarecomponents.com/store/sdram-board-b>
+ - <https://hackaday.io/project/20053-anacon-xc/log/54443-sdram-breakout-board-designed>