sim: riscv: move arch-specific settings to internal header

There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.

We can also move the machs.h include out since the model logic was all
generalized from compile-time to runtime last year.

diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c
index 6bd0bf2a41a68a1adf34d85617305477e6d8a0aa..a49ad0476c4553291aefdfdd54ef4154ba14e228 100644 (file)
--- a/sim/riscv/interp.c
+++ b/sim/riscv/interp.c
@@ -27,6 +27,8 @@
 #include "sim-main.h"
 #include "sim-options.h"
 #include "target-newlib-syscall.h"
+
+#include "riscv-sim.h"
 \f
 void
 sim_engine_run (SIM_DESC sd,

diff --git a/sim/riscv/machs.c b/sim/riscv/machs.c
index ea099ed02dea1d331e5facdf2602abfd16f5f01b..4951f480e3111b6c5747058babf950919fd0733e 100644 (file)
--- a/sim/riscv/machs.c
+++ b/sim/riscv/machs.c
@@ -22,6 +22,7 @@
 #include "defs.h"
 
 #include "sim-main.h"
+#include "machs.h"
 
 static void
 riscv_model_init (SIM_CPU *cpu)

diff --git a/sim/riscv/riscv-sim.h b/sim/riscv/riscv-sim.h
new file mode 100644 (file)
index 0000000..2139e37
--- /dev/null
+++ b/sim/riscv/riscv-sim.h
@@ -0,0 +1,78 @@
+/* RISC-V simulator.
+
+   Copyright (C) 2005-2022 Free Software Foundation, Inc.
+   Contributed by Mike Frysinger.
+
+   This file is part of the GNU simulators.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#ifndef RISCV_MAIN_H
+#define RISCV_MAIN_H
+
+struct riscv_sim_cpu {
+  union {
+    unsigned_word regs[32];
+    struct {
+      /* These are the ABI names.  */
+      unsigned_word zero, ra, sp, gp, tp;
+      unsigned_word t0, t1, t2;
+      unsigned_word s0, s1;
+      unsigned_word a0, a1, a2, a3, a4, a5, a6, a7;
+      unsigned_word s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
+      unsigned_word t3, t4, t5, t6;
+    };
+  };
+  union {
+    unsigned_word fpregs[32];
+    struct {
+      /* These are the ABI names.  */
+      unsigned_word ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7;
+      unsigned_word fs0, fs1;
+      unsigned_word fa0, fa1, fa2, fa3, fa4, fa5, fa6, fa7;
+      unsigned_word fs2, fs3, fs4, fs5, fs6, fs7, fs8, fs9, fs10, fs11;
+      unsigned_word ft8, ft9, ft10, ft11;
+    };
+  };
+  sim_cia pc;
+
+  struct {
+#define DECLARE_CSR(name, ...) unsigned_word name;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+  } csr;
+};
+#define RISCV_SIM_CPU(cpu) ((struct riscv_sim_cpu *) CPU_ARCH_DATA (cpu))
+
+struct atomic_mem_reserved_list;
+struct atomic_mem_reserved_list {
+  struct atomic_mem_reserved_list *next;
+  address_word addr;
+};
+
+struct riscv_sim_state {
+  struct atomic_mem_reserved_list *amo_reserved_list;
+};
+#define RISCV_SIM_STATE(sd) ((struct riscv_sim_state *) STATE_ARCH_DATA (sd))
+
+extern void step_once (SIM_CPU *);
+extern void initialize_cpu (SIM_DESC, SIM_CPU *, int);
+extern void initialize_env (SIM_DESC, const char * const *argv,
+                           const char * const *env);
+
+#define DEFAULT_MEM_SIZE (64 * 1024 * 1024)
+
+#define RISCV_XLEN(cpu) MACH_WORD_BITSIZE (CPU_MACH (cpu))
+
+#endif

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 4e7358b113a53a7825ca2302510748e30a5648fd..95950ee5977bf447939fecbbe677b5681d967484 100644 (file)
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -34,6 +34,8 @@
 #include "opcode/riscv.h"
 
 #include "sim/sim-riscv.h"
+
+#include "riscv-sim.h"
 \f
 #define TRACE_REG(cpu, reg) \
   TRACE_REGISTER (cpu, "wrote %s = %#" PRIxTW, riscv_gpr_names_abi[reg], \

diff --git a/sim/riscv/sim-main.h b/sim/riscv/sim-main.h
index 48ea452fb0b18ae8a39e23fee7f35f8c8845e812..a6de53cdccdbd6c40c4b5da070b43d98e5160a27 100644 (file)
--- a/sim/riscv/sim-main.h
+++ b/sim/riscv/sim-main.h
@@ -22,61 +22,6 @@
 #define SIM_MAIN_H
 
 #include "sim-basics.h"
-#include "machs.h"
 #include "sim-base.h"
 
-struct riscv_sim_cpu {
-  union {
-    unsigned_word regs[32];
-    struct {
-      /* These are the ABI names.  */
-      unsigned_word zero, ra, sp, gp, tp;
-      unsigned_word t0, t1, t2;
-      unsigned_word s0, s1;
-      unsigned_word a0, a1, a2, a3, a4, a5, a6, a7;
-      unsigned_word s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
-      unsigned_word t3, t4, t5, t6;
-    };
-  };
-  union {
-    unsigned_word fpregs[32];
-    struct {
-      /* These are the ABI names.  */
-      unsigned_word ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7;
-      unsigned_word fs0, fs1;
-      unsigned_word fa0, fa1, fa2, fa3, fa4, fa5, fa6, fa7;
-      unsigned_word fs2, fs3, fs4, fs5, fs6, fs7, fs8, fs9, fs10, fs11;
-      unsigned_word ft8, ft9, ft10, ft11;
-    };
-  };
-  sim_cia pc;
-
-  struct {
-#define DECLARE_CSR(name, ...) unsigned_word name;
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR
-  } csr;
-};
-#define RISCV_SIM_CPU(cpu) ((struct riscv_sim_cpu *) CPU_ARCH_DATA (cpu))
-
-struct atomic_mem_reserved_list;
-struct atomic_mem_reserved_list {
-  struct atomic_mem_reserved_list *next;
-  address_word addr;
-};
-
-struct riscv_sim_state {
-  struct atomic_mem_reserved_list *amo_reserved_list;
-};
-#define RISCV_SIM_STATE(sd) ((struct riscv_sim_state *) STATE_ARCH_DATA (sd))
-
-extern void step_once (SIM_CPU *);
-extern void initialize_cpu (SIM_DESC, SIM_CPU *, int);
-extern void initialize_env (SIM_DESC, const char * const *argv,
-                           const char * const *env);
-
-#define DEFAULT_MEM_SIZE (64 * 1024 * 1024)
-
-#define RISCV_XLEN(cpu) MACH_WORD_BITSIZE (CPU_MACH (cpu))
-
 #endif