| - | - | ----- | --- |---------|----------------- |
|sz |SNZ| 00 | 0 | dz / | normal mode |
| / | / | 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 |
-| / | / | 00 | 1 | 1 CRM | parallel reduce mode (mapreduce), SUBVL=1 |
+| / | / | 00 | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 |
| / | / | 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 |
|sz |SNZ| 01/10 | inv | CR-bit | Ffirst 3-bit mode |
|sz |SNZ| 01/10 | inv | dz / | Ffirst 5-bit mode |
* **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
* **RG** inverts the Vector Loop order (VL-1 downto 0) rather
than the normal 0..VL-1
-* **CRM** affects the CR on reduce mode when Rc=1
* **SVM** sets "subvector" reduce mode
* **VLi** VL inclusive: in fail-first mode, the truncation of
VL *includes* the current element at the failure point rather
than excludes it from the count.
-
# Data-dependent fail-first on CR operations
The principle of data-dependent fail-first is that if a Condition Test