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diff --git a/openpower/atomics.mdwn b/openpower/atomics.mdwn
index 0ac92a5566d6df60e6f50553bfbcf825caf886a2..77d063f606c317f779d35a9c141cb672690bd2c1 100644 (file)
--- a/openpower/atomics.mdwn
+++ b/openpower/atomics.mdwn
@@ -7,9 +7,15 @@
 Power ISA currently has some issues with its atomic operations support:
 
 ### Power ISA's current atomic operations are inefficient
-Implementations have a hard time recognizing existing atomic operations via macro-op fusion because they would often have to detect and fuse a large number of instructions, including branches.
 
-There is also the issue that PowerISA's memory fences are unnecessarily strong, particularly `isync` which is used for a lot of `acquire` and stronger fences. `isync` forces the cpu to do a full pipeline flush, which is unnecessary when all that is needed is a memory barrier.
+Implementations have a hard time recognizing existing atomic operations
+via macro-op fusion because they would often have to detect and fuse a
+large number of instructions, including branches.
+
+There is also the issue that PowerISA's memory fences are unnecessarily
+strong, particularly `isync` which is used for a lot of `acquire` and
+stronger fences. `isync` forces the cpu to do a full pipeline flush,
+which is unnecessary when all that is needed is a memory barrier.
 
 `atomic_fetch_add_seq_cst` is 6 instructions including a loop:
 
@@ -25,7 +31,8 @@ loop:
 # output in r3
 ```
 
-`atomic_load_seq_cst` is 5 instructions, including a branch, and an unnecessarily-strong memory fence:
+`atomic_load_seq_cst` is 5 instructions, including a branch, and an
+unnecessarily-strong memory fence:
 
 ```
 # address in r3
@@ -38,7 +45,8 @@ skip:
 # output in r3
 ```
 
-`atomic_compare_exchange_strong_seq_cst` is 7 instructions, including a loop with 2 branches, and an unnecessarily-strong memory fence:
+`atomic_compare_exchange_strong_seq_cst` is 7 instructions, including
+a loop with 2 branches, and an unnecessarily-strong memory fence:
 
 ```
 # address in r4, compared-to value in r5, replacement value in r6
@@ -54,7 +62,8 @@ not_eq:
 # output loaded value in r3, store-occurred flag in cr0.eq
 ```
 
-`atomic_load_acquire` is 4 instructions, including a branch and an unnecessarily-strong memory fence:
+`atomic_load_acquire` is 4 instructions, including a branch and an
+unnecessarily-strong memory fence:
 
 ```
 # address in r3
@@ -86,7 +95,9 @@ Having single atomic operations is useful for implementations that want to send
 
 PowerISA v3.1 Book II section 4.5: Atomic Memory Operations
 
-They are still missing better fences, combined operation/fence instructions, and operations on 8/16-bit values, as well as issues with unnecessary restrictions:
+They are still missing better fences, combined operation/fence
+instructions, and operations on 8/16-bit values, as well as issues with
+unnecessary restrictions:
 
 it has only 32-bit and 64-bit atomic operations.
 
@@ -108,12 +119,25 @@ fetch-and-increment-equal
 fetch-and-decrement-bounded
 store-twin
 
-The spec also basically says that the atomic memory operations are only intended for when you want to do atomic operations on memory, but don't want that memory to be loaded into your L1 cache.
+The spec also basically says that the atomic memory operations are only
+intended for when you want to do atomic operations on memory, but don't
+want that memory to be loaded into your L1 cache.
 
-imho that restriction is specifically *not* wanted, because there are plenty of cases where atomic operations should happen in your L1 cache.
+imho that restriction is specifically *not* wanted, because there are
+plenty of cases where atomic operations should happen in your L1 cache.
 
-I'd guess that part of why those atomic operations weren't included in gcc or clang as the default implementation of atomic operations (when the appropriate ISA feature is enabled) is because of that restriction.
+I'd guess that part of why those atomic operations weren't included in
+gcc or clang as the default implementation of atomic operations (when
+the appropriate ISA feature is enabled) is because of that restriction.
 
-imho the cpu should be able to (but not required to) predict whether to send an atomic operation to L2-cache/L3-cache/etc./memory or to execute it directly in the L1 cache. The prediction could be based on how often that cache block was accessed from different cpus, e.g. by having a small saturating counter and a last-accessing-cpu field, where it would count how many times the same cpu accessed it in a row, sending it to the L1 cache if that's more than some limit, otherwise doing the operation in the L2/L3/etc.-cache if the limit wasn't reached or a different cpu tried to access it.
+imho the cpu should be able to (but not required to) predict whether to
+send an atomic operation to L2-cache/L3-cache/etc./memory or to execute
+it directly in the L1 cache. The prediction could be based on how often
+that cache block was accessed from different cpus, e.g. by having a
+small saturating counter and a last-accessing-cpu field, where it would
+count how many times the same cpu accessed it in a row, sending it to the
+L1 cache if that's more than some limit, otherwise doing the operation
+in the L2/L3/etc.-cache if the limit wasn't reached or a different cpu
+tried to access it.
 
-# TODO: add list of proposed instructions
\ No newline at end of file
+# TODO: add list of proposed instructions