+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * config/tc-aarch64.c (process_omitted_operand):
+ Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2
+ and AARCH64_OPND_IMM_2.
+ (parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
+ AARCH64_OPND_IMM_2, AARCH64_OPND_MASK
+ and AARCH64_OPND_ADDR_OFFSET.
+
2017-11-09 Tamar Christina <tamar.christina@arm.com>
* config/tc-aarch64.c (aarch64_arch_option_table): Add armv8.4-a.
case AARCH64_OPND_Sd:
case AARCH64_OPND_Sn:
case AARCH64_OPND_Sm:
+ case AARCH64_OPND_Va:
case AARCH64_OPND_Vd:
case AARCH64_OPND_Vn:
case AARCH64_OPND_Vm:
case AARCH64_OPND_Ed:
case AARCH64_OPND_En:
case AARCH64_OPND_Em:
+ case AARCH64_OPND_SM3_IMM2:
operand->reglane.regno = default_value;
break;
case AARCH64_OPND_UIMM3_OP1:
case AARCH64_OPND_UIMM3_OP2:
case AARCH64_OPND_IMM:
+ case AARCH64_OPND_IMM_2:
case AARCH64_OPND_WIDTH:
case AARCH64_OPND_UIMM7:
case AARCH64_OPND_NZCV:
reg_type = REG_TYPE_ZN;
goto vector_reg;
+ case AARCH64_OPND_Va:
case AARCH64_OPND_Vd:
case AARCH64_OPND_Vn:
case AARCH64_OPND_Vm:
case AARCH64_OPND_Ed:
case AARCH64_OPND_En:
case AARCH64_OPND_Em:
+ case AARCH64_OPND_SM3_IMM2:
reg_type = REG_TYPE_VN;
vector_reg_index:
val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
case AARCH64_OPND_UIMM3_OP2:
case AARCH64_OPND_IMM_VLSL:
case AARCH64_OPND_IMM:
+ case AARCH64_OPND_IMM_2:
case AARCH64_OPND_WIDTH:
case AARCH64_OPND_SVE_INV_LIMM:
case AARCH64_OPND_SVE_LIMM:
break;
case AARCH64_OPND_IDX:
+ case AARCH64_OPND_MASK:
case AARCH64_OPND_BIT_NUM:
case AARCH64_OPND_IMMR:
case AARCH64_OPND_IMMS:
break;
case AARCH64_OPND_ADDR_SIMM10:
+ case AARCH64_OPND_ADDR_OFFSET:
po_misc_or_fail (parse_address (&str, info));
if (info->addr.pcrel || info->addr.offset.is_reg
|| !info->addr.preind || info->addr.postind)
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * opcode/aarch64.h:
+ (aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK,
+ AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET
+ and AARCH64_OPND_SM3_IMM2.
+ (aarch64_insn_class): Add cryptosm3 and cryptosm4.
+ (arch64_feature_set): Make uint64_t.
+
2017-11-09 Tamar Christina <tamar.christina@arm.com>
* opcode/aarch64.h:
AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
+ AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
+ AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
AARCH64_OPND_IMM, /* Immediate. */
+ AARCH64_OPND_IMM_2, /* Immediate. */
AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
+ AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
AARCH64_OPND_SYSREG, /* System register operand. */
AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
+ AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
};
/* Qualifier constrains an operand. It either specifies a variant of an
sve_size_hsd,
sve_size_sd,
testbranch,
+ cryptosm3,
+ cryptosm4,
dotproduct,
};
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-asm.h (ins_addr_offset): New.
+ * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
+ (aarch64_ins_addr_offset): New.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis.h (ext_addr_offset): New.
+ * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
+ (aarch64_ext_addr_offset): New.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
+ FLD_imm4_2 and FLD_SM3_imm2.
+ * aarch64-opc.c (fields): Add FLD_imm6_2,
+ FLD_imm4_2 and FLD_SM3_imm2.
+ (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
+ (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
+ AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
+ * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
+ * aarch64-tbl.h
+ (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
+
2017-11-09 Tamar Christina <tamar.christina@arm.com>
* aarch64-tbl.h
case 26:
case 27:
case 28:
- case 147:
- case 148:
- case 149:
- case 150:
+ case 29:
case 151:
case 152:
case 153:
case 154:
case 155:
case 156:
- case 169:
- case 170:
- case 171:
- case 172:
+ case 157:
+ case 158:
+ case 159:
+ case 160:
case 173:
case 174:
case 175:
case 176:
case 177:
+ case 178:
+ case 179:
+ case 180:
case 181:
- case 184:
+ case 185:
+ case 188:
return aarch64_ins_regno (self, info, code, inst);
case 13:
return aarch64_ins_reg_extended (self, info, code, inst);
return aarch64_ins_reg_shifted (self, info, code, inst);
case 19:
return aarch64_ins_ft (self, info, code, inst);
- case 29:
case 30:
case 31:
- return aarch64_ins_reglane (self, info, code, inst);
case 32:
- return aarch64_ins_reglist (self, info, code, inst);
+ case 190:
+ return aarch64_ins_reglane (self, info, code, inst);
case 33:
- return aarch64_ins_ldst_reglist (self, info, code, inst);
+ return aarch64_ins_reglist (self, info, code, inst);
case 34:
- return aarch64_ins_ldst_reglist_r (self, info, code, inst);
+ return aarch64_ins_ldst_reglist (self, info, code, inst);
case 35:
- return aarch64_ins_ldst_elemlist (self, info, code, inst);
+ return aarch64_ins_ldst_reglist_r (self, info, code, inst);
case 36:
+ return aarch64_ins_ldst_elemlist (self, info, code, inst);
case 37:
case 38:
- case 48:
- case 49:
+ case 39:
+ case 40:
case 50:
case 51:
case 52:
case 58:
case 59:
case 60:
- case 72:
- case 73:
- case 74:
+ case 61:
+ case 62:
+ case 63:
case 75:
- case 144:
- case 146:
- case 161:
- case 162:
- case 163:
- case 164:
+ case 76:
+ case 77:
+ case 78:
+ case 148:
+ case 150:
case 165:
case 166:
case 167:
case 168:
+ case 169:
+ case 170:
+ case 171:
+ case 172:
return aarch64_ins_imm (self, info, code, inst);
- case 39:
- case 40:
- return aarch64_ins_advsimd_imm_shift (self, info, code, inst);
case 41:
case 42:
+ return aarch64_ins_advsimd_imm_shift (self, info, code, inst);
case 43:
+ case 44:
+ case 45:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst);
- case 47:
- case 135:
+ case 49:
+ case 139:
return aarch64_ins_fpimm (self, info, code, inst);
- case 61:
- case 142:
+ case 64:
+ case 146:
return aarch64_ins_limm (self, info, code, inst);
- case 62:
+ case 65:
return aarch64_ins_aimm (self, info, code, inst);
- case 63:
- return aarch64_ins_imm_half (self, info, code, inst);
- case 64:
- return aarch64_ins_fbits (self, info, code, inst);
case 66:
+ return aarch64_ins_imm_half (self, info, code, inst);
case 67:
- case 140:
- return aarch64_ins_imm_rotate2 (self, info, code, inst);
- case 68:
- case 139:
- return aarch64_ins_imm_rotate1 (self, info, code, inst);
+ return aarch64_ins_fbits (self, info, code, inst);
case 69:
case 70:
+ case 144:
+ return aarch64_ins_imm_rotate2 (self, info, code, inst);
+ case 71:
+ case 143:
+ return aarch64_ins_imm_rotate1 (self, info, code, inst);
+ case 72:
+ case 73:
return aarch64_ins_cond (self, info, code, inst);
- case 76:
- case 83:
- return aarch64_ins_addr_simple (self, info, code, inst);
- case 77:
- return aarch64_ins_addr_regoff (self, info, code, inst);
- case 78:
case 79:
+ case 86:
+ return aarch64_ins_addr_simple (self, info, code, inst);
case 80:
- return aarch64_ins_addr_simm (self, info, code, inst);
+ return aarch64_ins_addr_regoff (self, info, code, inst);
case 81:
- return aarch64_ins_addr_simm10 (self, info, code, inst);
case 82:
- return aarch64_ins_addr_uimm12 (self, info, code, inst);
+ case 83:
+ return aarch64_ins_addr_simm (self, info, code, inst);
case 84:
- return aarch64_ins_simd_addr_post (self, info, code, inst);
+ return aarch64_ins_addr_simm10 (self, info, code, inst);
case 85:
- return aarch64_ins_sysreg (self, info, code, inst);
- case 86:
- return aarch64_ins_pstatefield (self, info, code, inst);
+ return aarch64_ins_addr_uimm12 (self, info, code, inst);
case 87:
+ return aarch64_ins_addr_offset (self, info, code, inst);
case 88:
+ return aarch64_ins_simd_addr_post (self, info, code, inst);
case 89:
+ return aarch64_ins_sysreg (self, info, code, inst);
case 90:
- return aarch64_ins_sysins_op (self, info, code, inst);
+ return aarch64_ins_pstatefield (self, info, code, inst);
case 91:
case 92:
- return aarch64_ins_barrier (self, info, code, inst);
case 93:
- return aarch64_ins_prfop (self, info, code, inst);
case 94:
- return aarch64_ins_hint (self, info, code, inst);
+ return aarch64_ins_sysins_op (self, info, code, inst);
case 95:
- return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst);
case 96:
+ return aarch64_ins_barrier (self, info, code, inst);
case 97:
+ return aarch64_ins_prfop (self, info, code, inst);
case 98:
+ return aarch64_ins_hint (self, info, code, inst);
case 99:
- return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst);
+ return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst);
case 100:
- return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst);
case 101:
- return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst);
case 102:
case 103:
+ return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst);
case 104:
+ return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst);
case 105:
- return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
+ return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst);
case 106:
case 107:
case 108:
case 109:
+ return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
case 110:
case 111:
case 112:
case 115:
case 116:
case 117:
- return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
case 118:
case 119:
case 120:
case 121:
+ return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
case 122:
case 123:
case 124:
case 125:
- return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
case 126:
case 127:
case 128:
case 129:
- return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
+ return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
case 130:
- return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
case 131:
- return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
case 132:
- return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
case 133:
- return aarch64_ins_sve_aimm (self, info, code, inst);
+ return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
case 134:
- return aarch64_ins_sve_asimm (self, info, code, inst);
+ return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
+ case 135:
+ return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
case 136:
- return aarch64_ins_sve_float_half_one (self, info, code, inst);
+ return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
case 137:
- return aarch64_ins_sve_float_half_two (self, info, code, inst);
+ return aarch64_ins_sve_aimm (self, info, code, inst);
case 138:
- return aarch64_ins_sve_float_zero_one (self, info, code, inst);
+ return aarch64_ins_sve_asimm (self, info, code, inst);
+ case 140:
+ return aarch64_ins_sve_float_half_one (self, info, code, inst);
case 141:
+ return aarch64_ins_sve_float_half_two (self, info, code, inst);
+ case 142:
+ return aarch64_ins_sve_float_zero_one (self, info, code, inst);
+ case 145:
return aarch64_ins_inv_limm (self, info, code, inst);
- case 143:
+ case 147:
return aarch64_ins_sve_limm_mov (self, info, code, inst);
- case 145:
+ case 149:
return aarch64_ins_sve_scale (self, info, code, inst);
- case 157:
- case 158:
+ case 161:
+ case 162:
return aarch64_ins_sve_shlimm (self, info, code, inst);
- case 159:
- case 160:
+ case 163:
+ case 164:
return aarch64_ins_sve_shrimm (self, info, code, inst);
- case 178:
- case 179:
- case 180:
- return aarch64_ins_sve_quad_index (self, info, code, inst);
case 182:
- return aarch64_ins_sve_index (self, info, code, inst);
case 183:
- case 185:
+ case 184:
+ return aarch64_ins_sve_quad_index (self, info, code, inst);
+ case 186:
+ return aarch64_ins_sve_index (self, info, code, inst);
+ case 187:
+ case 189:
return aarch64_ins_sve_reglist (self, info, code, inst);
default: assert (0); abort ();
}
assert (0);
}
}
+ else if (inst->opcode->iclass == cryptosm3)
+ {
+ /* index for e.g. SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>S[<imm2>]. */
+ unsigned reglane_index = info->reglane.index;
+ assert (reglane_index < 4);
+ insert_field (FLD_SM3_imm2, code, reglane_index, 0);
+ }
else
{
/* index for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
return NULL;
}
+/* Encode the address operand for e.g.
+ stlur <Xt>, [<Xn|SP>{, <amount>}]. */
+const char *
+aarch64_ins_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* Rn */
+ insert_field (self->fields[0], code, info->addr.base_regno, 0);
+
+ /* simm9 */
+ int imm = info->addr.offset.imm;
+ insert_field (self->fields[1], code, imm, 0);
+
+ /* writeback */
+ if (info->addr.writeback)
+ {
+ assert (info->addr.preind == 1 && info->addr.postind == 0);
+ insert_field (self->fields[2], code, 1, 0);
+ }
+ return NULL;
+}
+
/* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!. */
const char *
aarch64_ins_addr_simm (const aarch64_operand *self,
AARCH64_DECL_OPD_INSERTER (ins_inv_limm);
AARCH64_DECL_OPD_INSERTER (ins_ft);
AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
+AARCH64_DECL_OPD_INSERTER (ins_addr_offset);
AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
AARCH64_DECL_OPD_INSERTER (ins_addr_simm);
AARCH64_DECL_OPD_INSERTER (ins_addr_simm10);
case 26:
case 27:
case 28:
- case 147:
- case 148:
- case 149:
- case 150:
+ case 29:
case 151:
case 152:
case 153:
case 154:
case 155:
case 156:
- case 169:
- case 170:
- case 171:
- case 172:
+ case 157:
+ case 158:
+ case 159:
+ case 160:
case 173:
case 174:
case 175:
case 176:
case 177:
+ case 178:
+ case 179:
+ case 180:
case 181:
- case 184:
+ case 185:
+ case 188:
return aarch64_ext_regno (self, info, code, inst);
case 8:
return aarch64_ext_regrt_sysins (self, info, code, inst);
return aarch64_ext_reg_shifted (self, info, code, inst);
case 19:
return aarch64_ext_ft (self, info, code, inst);
- case 29:
case 30:
case 31:
- return aarch64_ext_reglane (self, info, code, inst);
case 32:
- return aarch64_ext_reglist (self, info, code, inst);
+ case 190:
+ return aarch64_ext_reglane (self, info, code, inst);
case 33:
- return aarch64_ext_ldst_reglist (self, info, code, inst);
+ return aarch64_ext_reglist (self, info, code, inst);
case 34:
- return aarch64_ext_ldst_reglist_r (self, info, code, inst);
+ return aarch64_ext_ldst_reglist (self, info, code, inst);
case 35:
- return aarch64_ext_ldst_elemlist (self, info, code, inst);
+ return aarch64_ext_ldst_reglist_r (self, info, code, inst);
case 36:
+ return aarch64_ext_ldst_elemlist (self, info, code, inst);
case 37:
case 38:
- case 48:
- case 49:
+ case 39:
+ case 40:
case 50:
case 51:
case 52:
case 58:
case 59:
case 60:
- case 71:
- case 72:
- case 73:
+ case 61:
+ case 62:
+ case 63:
case 74:
case 75:
- case 144:
- case 146:
- case 161:
- case 162:
- case 163:
- case 164:
+ case 76:
+ case 77:
+ case 78:
+ case 148:
+ case 150:
case 165:
case 166:
case 167:
case 168:
+ case 169:
+ case 170:
+ case 171:
+ case 172:
return aarch64_ext_imm (self, info, code, inst);
- case 39:
- case 40:
- return aarch64_ext_advsimd_imm_shift (self, info, code, inst);
case 41:
case 42:
+ return aarch64_ext_advsimd_imm_shift (self, info, code, inst);
case 43:
- return aarch64_ext_advsimd_imm_modified (self, info, code, inst);
case 44:
+ case 45:
+ return aarch64_ext_advsimd_imm_modified (self, info, code, inst);
+ case 46:
return aarch64_ext_shll_imm (self, info, code, inst);
- case 47:
- case 135:
+ case 49:
+ case 139:
return aarch64_ext_fpimm (self, info, code, inst);
- case 61:
- case 142:
+ case 64:
+ case 146:
return aarch64_ext_limm (self, info, code, inst);
- case 62:
+ case 65:
return aarch64_ext_aimm (self, info, code, inst);
- case 63:
- return aarch64_ext_imm_half (self, info, code, inst);
- case 64:
- return aarch64_ext_fbits (self, info, code, inst);
case 66:
+ return aarch64_ext_imm_half (self, info, code, inst);
case 67:
- case 140:
- return aarch64_ext_imm_rotate2 (self, info, code, inst);
- case 68:
- case 139:
- return aarch64_ext_imm_rotate1 (self, info, code, inst);
+ return aarch64_ext_fbits (self, info, code, inst);
case 69:
case 70:
+ case 144:
+ return aarch64_ext_imm_rotate2 (self, info, code, inst);
+ case 71:
+ case 143:
+ return aarch64_ext_imm_rotate1 (self, info, code, inst);
+ case 72:
+ case 73:
return aarch64_ext_cond (self, info, code, inst);
- case 76:
- case 83:
- return aarch64_ext_addr_simple (self, info, code, inst);
- case 77:
- return aarch64_ext_addr_regoff (self, info, code, inst);
- case 78:
case 79:
+ case 86:
+ return aarch64_ext_addr_simple (self, info, code, inst);
case 80:
- return aarch64_ext_addr_simm (self, info, code, inst);
+ return aarch64_ext_addr_regoff (self, info, code, inst);
case 81:
- return aarch64_ext_addr_simm10 (self, info, code, inst);
case 82:
- return aarch64_ext_addr_uimm12 (self, info, code, inst);
+ case 83:
+ return aarch64_ext_addr_simm (self, info, code, inst);
case 84:
- return aarch64_ext_simd_addr_post (self, info, code, inst);
+ return aarch64_ext_addr_simm10 (self, info, code, inst);
case 85:
- return aarch64_ext_sysreg (self, info, code, inst);
- case 86:
- return aarch64_ext_pstatefield (self, info, code, inst);
+ return aarch64_ext_addr_uimm12 (self, info, code, inst);
case 87:
+ return aarch64_ext_addr_offset (self, info, code, inst);
case 88:
+ return aarch64_ext_simd_addr_post (self, info, code, inst);
case 89:
+ return aarch64_ext_sysreg (self, info, code, inst);
case 90:
- return aarch64_ext_sysins_op (self, info, code, inst);
+ return aarch64_ext_pstatefield (self, info, code, inst);
case 91:
case 92:
- return aarch64_ext_barrier (self, info, code, inst);
case 93:
- return aarch64_ext_prfop (self, info, code, inst);
case 94:
- return aarch64_ext_hint (self, info, code, inst);
+ return aarch64_ext_sysins_op (self, info, code, inst);
case 95:
- return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst);
case 96:
+ return aarch64_ext_barrier (self, info, code, inst);
case 97:
+ return aarch64_ext_prfop (self, info, code, inst);
case 98:
+ return aarch64_ext_hint (self, info, code, inst);
case 99:
- return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst);
+ return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst);
case 100:
- return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst);
case 101:
- return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst);
case 102:
case 103:
+ return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst);
case 104:
+ return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst);
case 105:
- return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst);
+ return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst);
case 106:
case 107:
case 108:
case 109:
+ return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst);
case 110:
case 111:
case 112:
case 115:
case 116:
case 117:
- return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst);
case 118:
case 119:
case 120:
case 121:
+ return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst);
case 122:
case 123:
case 124:
case 125:
- return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst);
case 126:
case 127:
case 128:
case 129:
- return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst);
+ return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst);
case 130:
- return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst);
case 131:
- return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst);
case 132:
- return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst);
case 133:
- return aarch64_ext_sve_aimm (self, info, code, inst);
+ return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst);
case 134:
- return aarch64_ext_sve_asimm (self, info, code, inst);
+ return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst);
+ case 135:
+ return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst);
case 136:
- return aarch64_ext_sve_float_half_one (self, info, code, inst);
+ return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst);
case 137:
- return aarch64_ext_sve_float_half_two (self, info, code, inst);
+ return aarch64_ext_sve_aimm (self, info, code, inst);
case 138:
- return aarch64_ext_sve_float_zero_one (self, info, code, inst);
+ return aarch64_ext_sve_asimm (self, info, code, inst);
+ case 140:
+ return aarch64_ext_sve_float_half_one (self, info, code, inst);
case 141:
+ return aarch64_ext_sve_float_half_two (self, info, code, inst);
+ case 142:
+ return aarch64_ext_sve_float_zero_one (self, info, code, inst);
+ case 145:
return aarch64_ext_inv_limm (self, info, code, inst);
- case 143:
+ case 147:
return aarch64_ext_sve_limm_mov (self, info, code, inst);
- case 145:
+ case 149:
return aarch64_ext_sve_scale (self, info, code, inst);
- case 157:
- case 158:
+ case 161:
+ case 162:
return aarch64_ext_sve_shlimm (self, info, code, inst);
- case 159:
- case 160:
+ case 163:
+ case 164:
return aarch64_ext_sve_shrimm (self, info, code, inst);
- case 178:
- case 179:
- case 180:
- return aarch64_ext_sve_quad_index (self, info, code, inst);
case 182:
- return aarch64_ext_sve_index (self, info, code, inst);
case 183:
- case 185:
+ case 184:
+ return aarch64_ext_sve_quad_index (self, info, code, inst);
+ case 186:
+ return aarch64_ext_sve_index (self, info, code, inst);
+ case 187:
+ case 189:
return aarch64_ext_sve_reglist (self, info, code, inst);
default: assert (0); abort ();
}
return 0;
}
}
+ else if (inst->opcode->iclass == cryptosm3)
+ {
+ /* index for e.g. SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>S[<imm2>]. */
+ info->reglane.index = extract_field (FLD_SM3_imm2, code, 0);
+ }
else
{
/* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
return 1;
}
+/* Decode the address operand for e.g.
+ stlur <Xt>, [<Xn|SP>{, <amount>}]. */
+int
+aarch64_ext_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code, const aarch64_inst *inst)
+{
+ info->qualifier = get_expected_qualifier (inst, info->idx);
+
+ /* Rn */
+ info->addr.base_regno = extract_field (self->fields[0], code, 0);
+
+ /* simm9 */
+ aarch64_insn imm = extract_fields (code, 0, 1, self->fields[1]);
+ info->addr.offset.imm = sign_extend (imm, 8);
+ if (extract_field (self->fields[2], code, 0) == 1) {
+ info->addr.writeback = 1;
+ info->addr.preind = 1;
+ }
+ return 1;
+}
+
/* Decode the address operand for e.g.
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
int
AARCH64_DECL_OPD_EXTRACTOR (ext_inv_limm);
AARCH64_DECL_OPD_EXTRACTOR (ext_ft);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple);
+AARCH64_DECL_OPD_EXTRACTOR (ext_addr_offset);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_regoff);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm10);
{AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD scalar register"},
{AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD scalar register"},
{AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD scalar register"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "Va", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a SIMD vector register"},
{AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector register"},
{AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register"},
{AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector register"},
{AARCH64_OPND_CLASS_IMMEDIATE, "CRn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"},
{AARCH64_OPND_CLASS_IMMEDIATE, "CRm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4}, "an immediate as the index of the least significant byte"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "MASK", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_2}, "an immediate as the index of the least significant byte"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a left shift amount for an AdvSIMD register"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a right shift amount for an AdvSIMD register"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the leftmost bit number to be moved from the source"},
{AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the width of the bit-field"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "an immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_2}, "an immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with 10-bit scaled, signed immediate offset"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm9,FLD_index}, "an address with an optional 8-bit signed immediate offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a post-indexed address with immediate or register increment"},
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a system register"},
{AARCH64_OPND_CLASS_SYSTEM, "PSTATEFIELD", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a PSTATE field name"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
};
{ 22, 2 }, /* type: floating point type field in fp data inst. */
{ 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
{ 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
+ { 15, 6 }, /* imm6_2: in rmif instructions. */
{ 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
+ { 0, 4 }, /* imm4_2: in rmif instructions. */
{ 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
{ 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
{ 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
{ 11, 2 }, /* rotate1: FCMLA immediate rotate. */
{ 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
{ 12, 1 }, /* rotate3: FCADD immediate rotate. */
+ { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
};
enum aarch64_operand_class
return 0;
}
break;
+ case AARCH64_OPND_ADDR_OFFSET:
case AARCH64_OPND_ADDR_SIMM9:
/* Unscaled signed 9 bits immediate offset. */
if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
opnd->reg.regno);
break;
+ case AARCH64_OPND_Va:
case AARCH64_OPND_Vd:
case AARCH64_OPND_Vn:
case AARCH64_OPND_Vm:
case AARCH64_OPND_Ed:
case AARCH64_OPND_En:
case AARCH64_OPND_Em:
+ case AARCH64_OPND_SM3_IMM2:
snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
aarch64_get_qualifier_name (opnd->qualifier),
opnd->reglane.index);
break;
case AARCH64_OPND_IDX:
+ case AARCH64_OPND_MASK:
case AARCH64_OPND_IMM:
+ case AARCH64_OPND_IMM_2:
case AARCH64_OPND_WIDTH:
case AARCH64_OPND_UIMM3_OP1:
case AARCH64_OPND_UIMM3_OP2:
case AARCH64_OPND_ADDR_SIMM9:
case AARCH64_OPND_ADDR_SIMM9_2:
case AARCH64_OPND_ADDR_SIMM10:
+ case AARCH64_OPND_ADDR_OFFSET:
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
FLD_type,
FLD_ldst_size,
FLD_imm6,
+ FLD_imm6_2,
FLD_imm4,
+ FLD_imm4_2,
FLD_imm5,
FLD_imm7,
FLD_imm8,
FLD_rotate1,
FLD_rotate2,
FLD_rotate3,
+ FLD_SM3_imm2
};
/* Field description. */
Y(SISD_REG, regno, "Sd", 0, F(FLD_Rd), "a SIMD scalar register") \
Y(SISD_REG, regno, "Sn", 0, F(FLD_Rn), "a SIMD scalar register") \
Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \
+ Y(SIMD_REG, regno, "Va", 0, F(FLD_Ra), "a SIMD vector register") \
Y(SIMD_REG, regno, "Vd", 0, F(FLD_Rd), "a SIMD vector register") \
Y(SIMD_REG, regno, "Vn", 0, F(FLD_Rn), "a SIMD vector register") \
Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register") \
"a 4-bit opcode field named for historical reasons C0 - C15") \
Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4), \
"an immediate as the index of the least significant byte") \
+ Y(IMMEDIATE, imm, "MASK", 0, F(FLD_imm4_2), \
+ "an immediate as the index of the least significant byte") \
Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSL", 0, F(), \
"a left shift amount for an AdvSIMD register") \
Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSR", 0, F(), \
"the leftmost bit number to be moved from the source") \
Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6), \
"the width of the bit-field") \
- Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6), "an immediate") \
+ Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6), "an immediate") \
+ Y(IMMEDIATE, imm, "IMM_2", 0, F(FLD_imm6_2), "an immediate") \
Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD_op1), \
"a 3-bit unsigned immediate") \
Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD_op2), \
"an address with scaled, unsigned immediate offset") \
Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \
"an address with base register (no offset)") \
+ Y(ADDRESS, addr_offset, "ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9,FLD_index),\
+ "an address with an optional 8-bit signed immediate offset") \
Y(ADDRESS, simd_addr_post, "SIMD_ADDR_POST", 0, F(), \
"a post-indexed address with immediate or register increment") \
Y(SYSTEM, sysreg, "SYSREG", 0, F(), "a system register") \
Y(SVE_REG, regno, "SVE_Zt", 0, F(FLD_SVE_Zt), \
"an SVE vector register") \
Y(SVE_REG, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \
- "a list of SVE vector registers")
+ "a list of SVE vector registers") \
+ Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \
+ "an indexed SM3 vector immediate")
projects / binutils-gdb.git / commitdiff