soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function...

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index 4f60e2dfd4f1dce8d002e4ce73689e463d78c723..4687c0344d178b72f93495f58ff0218dce6fc038 100644 (file)
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -53,6 +53,8 @@ class SDRAMSoC(SoC):
         # XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories.
         main_ram_size = min(main_ram_size, 256*1024*1024)
         l2_size = self.sdram_controller_settings.l2_size
+        if l2_size:
+            self.add_constant("L2_SIZE", l2_size)
 
         # add a Wishbone interface to the DRAM
         wb_sdram = wishbone.Interface()

diff --git a/software/bios/main.c b/software/bios/main.c
index bb854df042c3c992bcc355035974e172930785c5..9f80f5f02ab53a0b97b4315b0531557403f4b1d6 100644 (file)
--- a/software/bios/main.c
+++ b/software/bios/main.c
@@ -355,7 +355,10 @@ static void do_command(char *c)
        else if(strcmp(token, "mw") == 0) mw(get_token(&c), get_token(&c), get_token(&c));
        else if(strcmp(token, "mc") == 0) mc(get_token(&c), get_token(&c), get_token(&c));
        else if(strcmp(token, "crc") == 0) crc(get_token(&c), get_token(&c));
+
+#ifdef L2_SIZE
        else if(strcmp(token, "flushl2") == 0) flush_l2_cache();
+#endif
 
 #ifdef FLASH_BOOT_ADDRESS
        else if(strcmp(token, "flashboot") == 0) flashboot();

diff --git a/software/libbase/system.c b/software/libbase/system.c
index 0bf3099696aec72b6a61badb340c8a64cbb5fe59..3f19c23d4cb9872269ae7d23a8ba6ab98fe490fa 100644 (file)
--- a/software/libbase/system.c
+++ b/software/libbase/system.c
@@ -67,16 +67,14 @@ void flush_cpu_dcache(void)
 #endif
 }
 
-#ifdef CSR_L2_CACHE_BASE
+#ifdef L2_SIZE
 void flush_l2_cache(void)
 {
-       unsigned int l2_nwords;
        unsigned int i;
        register unsigned int addr;
        register unsigned int dummy;
 
-       l2_nwords = 1 << l2_cache_size_read();
-       for(i=0;i<2*l2_nwords;i++) {
+       for(i=0;i<2*L2_SIZE;i++) {
                addr = MAIN_RAM_BASE + i*4;
 #if defined (__lm32__)
                __asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
@@ -87,8 +85,4 @@ void flush_l2_cache(void)
 #endif
        }
 }
-#else
-void flush_l2_cache(void)
-{
-}
 #endif