style: fix line lengths and include ordering

The style checker complains about line length and ordering for these
files. This fix should make these two files kosher.

Change-Id: I822a0518a98d9e379a543d2017e90c4e9666a58d
Reviewed-on: https://gem5-review.googlesource.com/3380
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index b5ad977d5723b094f52243b6486a4c388aff5697..d60d7cec1fe03280e3ea405668791fc091ac83b6 100644 (file)
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -477,7 +477,8 @@ class MetaSimObject(type):
             if isinstance(c, MetaSimObject):
                 bTotal += 1
             if bTotal > 1:
-                raise TypeError, "SimObjects do not support multiple inheritance"
+                raise TypeError, \
+                      "SimObjects do not support multiple inheritance"
 
         base = bases[0]
 
@@ -679,9 +680,10 @@ class MetaSimObject(type):
         code('''#include "pybind11/pybind11.h"
 #include "pybind11/stl.h"
 
-#include "sim/sim_object.hh"
 #include "params/$cls.hh"
 #include "sim/init.hh"
+#include "sim/sim_object.hh"
+
 #include "${{cls.cxx_header}}"
 
 ''')
@@ -982,7 +984,8 @@ class SimObject(object):
 
                     if keys in self._hr_values\
                        and keys in self._values\
-                       and not isinstance(self._values[keys], m5.proxy.BaseProxy):
+                       and not isinstance(self._values[keys],
+                                          m5.proxy.BaseProxy):
                         cmd_str = cmd_line_str + keys
                         acc_str = access_str + keys
                         flags_dict[cmd_str] = ParamInfo(ptype,
@@ -1182,8 +1185,9 @@ class SimObject(object):
         self._parent = parent
         self._name = name
 
-    # Return parent object of this SimObject, not implemented by SimObjectVector
-    # because the elements in a SimObjectVector may not share the same parent
+    # Return parent object of this SimObject, not implemented by
+    # SimObjectVector because the elements in a SimObjectVector may not share
+    # the same parent
     def get_parent(self):
         return self._parent
 
@@ -1275,7 +1279,8 @@ class SimObject(object):
                 match_obj = self._values[pname]
                 if found_obj != None and found_obj != match_obj:
                     raise AttributeError, \
-                          'parent.any matched more than one: %s and %s' % (found_obj.path, match_obj.path)
+                          'parent.any matched more than one: %s and %s' % \
+                          (found_obj.path, match_obj.path)
                 found_obj = match_obj
         return found_obj, found_obj != None
 

diff --git a/util/m5/m5.c b/util/m5/m5.c
index d39098c687dd4519c1bc76f8b1b77dedda974845..bd39041d3f9db8b362f5dfd4f4cd5ed36fec8754 100644 (file)
--- a/util/m5/m5.c
+++ b/util/m5/m5.c
@@ -43,6 +43,7 @@
 #ifdef linux
 #define _GNU_SOURCE
 #include <sched.h>
+
 #endif
 
 #include <err.h>
@@ -348,7 +349,8 @@ struct MainFunc mainfuncs[] = {
     { "checkpoint",     do_checkpoint,       "[delay [period]]" },
     { "addsymbol",      do_addsymbol,        "<address> <symbol>" },
     { "loadsymbol",     do_loadsymbol,       "" },
-    { "initparam",      do_initparam,        "[key] // key must be shorter than 16 chars" },
+    { "initparam",      do_initparam,        "[key] // key must be shorter"
+                                             " than 16 chars" },
     { "sw99param",      do_sw99param,        "" },
 #ifdef linux
     { "pin",            do_pin,              "<cpu> <program> [args ...]" }
@@ -384,7 +386,8 @@ map_m5_mem()
         exit(1);
     }
 
-    m5_mem = mmap(NULL, 0x10000, PROT_READ | PROT_WRITE, MAP_SHARED, fd, M5OP_ADDR);
+    m5_mem = mmap(NULL, 0x10000, PROT_READ | PROT_WRITE, MAP_SHARED, fd,
+                  M5OP_ADDR);
     if (!m5_mem) {
         perror("Can't mmap /dev/mem");
         exit(1);