fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU.

This was to support port proxies and getInstPort and getDataPort. With
some recent upstream changes, getInstPort and getDataPort are only used
for CPU switching which we can't support (TLM ports are bound
permanently), and with the sendFunctional delegate for port proxies,
we don't need to have a traditional gem5 port lying around.

This gets rid of the "mem" port and all its plumbing.

Change-Id: Ic68a40a26b24aa05b33da0510c9f4b7621cbf578
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21048
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

diff --git a/src/arch/arm/fastmodel/arm/FastModelArch.py b/src/arch/arm/fastmodel/arm/FastModelArch.py
index efc40b2d853ccf12af9f0f4252cda0b3de2d2f2e..b2869563fbffe44477250e31a1852b61d2472747 100644 (file)
--- a/src/arch/arm/fastmodel/arm/FastModelArch.py
+++ b/src/arch/arm/fastmodel/arm/FastModelArch.py
@@ -36,5 +36,3 @@ class FastModelArmCPU(IrisArmCPU):
     cxx_header = 'arch/arm/fastmodel/arm/cpu.hh'
 
     cntfrq = Param.UInt64("Value for the CNTFRQ timer register")
-
-    mem = RequestPort('Port for port proxies to attach to.')

diff --git a/src/arch/arm/fastmodel/arm/cpu.cc b/src/arch/arm/fastmodel/arm/cpu.cc
index 47420368f4968b4b14cae98e3ca607db0d59b63b..c87c2ac5f011ca225b74fe869770ac016e244244 100644 (file)
--- a/src/arch/arm/fastmodel/arm/cpu.cc
+++ b/src/arch/arm/fastmodel/arm/cpu.cc
@@ -35,8 +35,7 @@ namespace FastModel
 {
 
 ArmCPU::ArmCPU(FastModelArmCPUParams *params) :
-    Iris::ArmCPU(params, scx::scx_get_iris_connection_interface()),
-    mem(name() + ".mem", this)
+    Iris::ArmCPU(params, scx::scx_get_iris_connection_interface())
 {
 }
 
@@ -48,14 +47,6 @@ ArmCPU::initState()
         tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, cntfrq);
 }
 
-Port &
-ArmCPU::getPort(const std::string &if_name, PortID idx)
-{
-    if (if_name == "mem")
-        return mem;
-    return Iris::ArmCPU::getPort(if_name, idx);
-}
-
 } // namespace FastModel
 
 FastModel::ArmCPU *

diff --git a/src/arch/arm/fastmodel/arm/cpu.hh b/src/arch/arm/fastmodel/arm/cpu.hh
index 1d9d585c3785f996630f27f9003e79efa9e8d702..379174ec3fb6ae2d684f2183edafd74e33faf0b4 100644 (file)
--- a/src/arch/arm/fastmodel/arm/cpu.hh
+++ b/src/arch/arm/fastmodel/arm/cpu.hh
@@ -39,36 +39,10 @@ namespace FastModel
 // This class adds non-Iris, gem5 functionality to this CPU model.
 class ArmCPU : public Iris::ArmCPU
 {
-  private:
-    class MemPort : public MasterPort
-    {
-      public:
-        using MasterPort::MasterPort;
-
-        bool
-        recvTimingResp(PacketPtr pkt) override
-        {
-            panic("%s.%s not implemented.\n", name(), __FUNCTION__);
-        }
-
-        void
-        recvReqRetry() override
-        {
-            panic("%s.%s not implemented.\n", name(), __FUNCTION__);
-        }
-    };
-
-    MemPort mem;
-
   public:
     ArmCPU(FastModelArmCPUParams *params);
 
     void initState() override;
-    Port &getPort(const std::string &if_name,
-                  PortID idx=InvalidPortID) override;
-
-    Port &getDataPort() override { return mem; }
-    Port &getInstPort() override { return mem; }
 };
 
 } // namespace FastModel