arm: Don't consult the TLB test iface for functional translations

Don't consult the TLB test interface for PA's returned by functional
translations by the AT instruction. We implement this by chaning the
ISA code to synthesize 0-length functional reads for the TLB lookup.
The TLB then bypasses the final PA check in the tester if the size is
zero.

Change-Id: I2487b7f829cea88c37e229e9fc7a4543aced961b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index d3286a6b0a288e8441be5c32594901a817827a47..0b753087e923944df783bacd0e78909d8e092646 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1520,7 +1520,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
               // can't be an atomic translation because that causes problems
               // with unexpected atomic snoop requests.
               warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
-              Request req(0, val, 1, flags,  Request::funcMasterId,
+              Request req(0, val, 0, flags,  Request::funcMasterId,
                           tc->pcState().pc(), tc->contextId());
               fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType);
               TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
@@ -1765,7 +1765,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 // can't be an atomic translation because that causes problems
                 // with unexpected atomic snoop requests.
                 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
-                req->setVirt(0, val, 1, flags,  Request::funcMasterId,
+                req->setVirt(0, val, 0, flags,  Request::funcMasterId,
                                tc->pcState().pc());
                 req->setContext(tc->contextId());
                 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode,

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index f4d51546c8d97bff7f735cffbdfa09e1900ad5d0..a499900e0a671c00d97a06b5318bb64bad8bea4d 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1423,7 +1423,7 @@ TLB::setTestInterface(SimObject *_ti)
 Fault
 TLB::testTranslation(RequestPtr req, Mode mode, TlbEntry::DomainType domain)
 {
-    if (!test) {
+    if (!test || !req->hasSize() || req->getSize() == 0) {
         return NoFault;
     } else {
         return test->translationCheck(req, isPriv, mode, domain);