* TODO: is this true on earlier gen's?
*/
compiler->max_const_compute = 256;
+
+ if (compiler->gpu_id == 650)
+ compiler->tess_use_shared = true;
} else {
compiler->max_const_pipeline = 512;
compiler->max_const_geom = 512;
*/
bool samgq_workaround;
+ /* on a650, vertex shader <-> tess control io uses LDL/STL */
+ bool tess_use_shared;
+
/* The maximum number of constants, in vec4's, across the entire graphics
* pipeline.
*/
create_immed(b, intr->num_components), 0,
create_immed(b, base), 0);
+ /* for a650, use LDL for tess ctrl inputs: */
+ if (ctx->so->type == MESA_SHADER_TESS_CTRL && ctx->compiler->tess_use_shared)
+ load->opc = OPC_LDL;
+
load->cat6.type = utype_dst(intr->dest);
load->regs[0]->wrmask = MASK(intr->num_components);
ir3_create_collect(ctx, value, intr->num_components), 0,
create_immed(b, intr->num_components), 0);
+ /* for a650, use STL for vertex outputs used by tess ctrl shader: */
+ if (ctx->so->type == MESA_SHADER_VERTEX && ctx->so->key.tessellation &&
+ ctx->compiler->tess_use_shared)
+ store->opc = OPC_STL;
+
store->cat6.dst_offset = nir_intrinsic_base(intr);
store->cat6.type = utype_src(intr->src[0]);
store->barrier_class = IR3_BARRIER_SHARED_W;
break;
case MESA_SHADER_TESS_CTRL:
NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, so, so->key.tessellation);
- NIR_PASS_V(s, ir3_nir_lower_to_explicit_input);
+ NIR_PASS_V(s, ir3_nir_lower_to_explicit_input, so->shader->compiler);
progress = true;
break;
case MESA_SHADER_TESS_EVAL:
progress = true;
break;
case MESA_SHADER_GEOMETRY:
- NIR_PASS_V(s, ir3_nir_lower_to_explicit_input);
+ NIR_PASS_V(s, ir3_nir_lower_to_explicit_input, so->shader->compiler);
progress = true;
break;
default:
void ir3_nir_lower_to_explicit_output(nir_shader *shader,
struct ir3_shader_variant *v, unsigned topology);
-void ir3_nir_lower_to_explicit_input(nir_shader *shader);
+void ir3_nir_lower_to_explicit_input(nir_shader *shader, struct ir3_compiler *compiler);
void ir3_nir_lower_tess_ctrl(nir_shader *shader, struct ir3_shader_variant *v, unsigned topology);
void ir3_nir_lower_tess_eval(nir_shader *shader, unsigned topology);
void ir3_nir_lower_gs(nir_shader *shader);
struct exec_list old_outputs;
struct exec_list emit_outputs;
+
+ /* tess ctrl shader on a650 gets the local primitive id at different bits: */
+ bool local_primitive_id_start;
};
static nir_ssa_def *
static nir_ssa_def *
build_local_primitive_id(nir_builder *b, struct state *state)
{
- return bitfield_extract(b, state->header, 0, 63);
+ return bitfield_extract(b, state->header, state->local_primitive_id_start, 63);
}
static nir_variable *
}
void
-ir3_nir_lower_to_explicit_input(nir_shader *shader)
+ir3_nir_lower_to_explicit_input(nir_shader *shader, struct ir3_compiler *compiler)
{
struct state state = { };
+ /* when using stl/ldl (instead of stlw/ldlw) for linking VS and HS,
+ * HS uses a different primitive id, which starts at bit 16 in the header
+ */
+ if (shader->info.stage == MESA_SHADER_TESS_CTRL && compiler->tess_use_shared)
+ state.local_primitive_id_start = 16;
+
nir_function_impl *impl = nir_shader_get_entrypoint(shader);
assert(impl);