move add to its own simple example

diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn
index 5032eb51a63024ab29b4f682ec914b27314837f5..2143b8cafdb7f0dcd2f78d32679ea3ffd1277506 100644 (file)
--- a/simple_v_extension/abridged_spec.mdwn
+++ b/simple_v_extension/abridged_spec.mdwn
@@ -239,6 +239,16 @@ to be set.
 
 See [[appendix]] for more details on fail-on-first modes.
 
+# Simplified Pseudo-code example
+
+A greatly simplified example illustrating (just) the VL hardware for-loop
+is as follows:
+[[!inline raw="yes" pages="simple_v_extension/simple_add_example" ]]
+
+Note that zeroing, elwidth handling, SUBVL and PCVLIW have all been
+left out, for clarity.  For examples on how to handle each, see
+[[appendix]].
+
 # Vector Block Format <a name="vliw-format"></a>
 
 The Vector Block format uses the RISC-V 80-192 bit format from Section 1.5

diff --git a/simple_v_extension/appendix.mdwn b/simple_v_extension/appendix.mdwn
index 6e883137c349c42a1b9c891cda4d8e13faaf89d4..55e1cd58636757dff9fb9ea611a8e64b9386ef4d 100644 (file)
--- a/simple_v_extension/appendix.mdwn
+++ b/simple_v_extension/appendix.mdwn
@@ -105,23 +105,10 @@ attention must be paid.
 Example pseudo-code for an integer ADD operation (including scalar
 operations).  Floating-point uses the FP Register Table.
 
-    function op_add(rd, rs1, rs2) # add not VADD!
-      int i, id=0, irs1=0, irs2=0;
-      predval = get_pred_val(FALSE, rd);
-      rd  = int_vec[rd ].isvector ? int_vec[rd ].regidx : rd;
-      rs1 = int_vec[rs1].isvector ? int_vec[rs1].regidx : rs1;
-      rs2 = int_vec[rs2].isvector ? int_vec[rs2].regidx : rs2;
-      for (i = 0; i < VL; i++)
-        xSTATE.srcoffs = i # save context
-        if (predval & 1<<i) # predication uses intregs
-           ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
-           if (!int_vec[rd ].isvector) break;
-        if (int_vec[rd ].isvector)  { id += 1; }
-        if (int_vec[rs1].isvector)  { irs1 += 1; }
-        if (int_vec[rs2].isvector)  { irs2 += 1; }
+[[!inline raw="yes" pages="simple_v_extension/simple_add_example" ]]
 
 Note that for simplicity there is quite a lot missing from the above
-pseudo-code: element widths, zeroing on predication, dimensional
+pseudo-code: PCVBLK, element widths, zeroing on predication, dimensional
 reshaping and offsets and so on.  However it demonstrates the basic
 principle.  Augmentations that produce the full pseudo-code are covered in
 other sections.

diff --git a/simple_v_extension/simple_add_example.mdwn b/simple_v_extension/simple_add_example.mdwn
new file mode 100644 (file)
index 0000000..41e7377
--- /dev/null
+++ b/simple_v_extension/simple_add_example.mdwn
@@ -0,0 +1,20 @@
+    function op_add(rd, rs1, rs2) # add not VADD!
+      int i, id=0, irs1=0, irs2=0;
+      predval = get_pred_val(FALSE, rd);
+      rd  = int_vec[rd ].isvector ? int_vec[rd ].regidx : rd;
+      rs1 = int_vec[rs1].isvector ? int_vec[rs1].regidx : rs1;
+      rs2 = int_vec[rs2].isvector ? int_vec[rs2].regidx : rs2;
+      for (i = 0; i < VL; i++)
+        xSTATE.srcoffs = i # save context
+        if (predval & 1<<i) # predication uses intregs
+           ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
+           if (!int_vec[rd ].isvector) break;
+        if (int_vec[rd ].isvector)  { id += 1; }
+        if (int_vec[rs1].isvector)  { irs1 += 1; }
+        if (int_vec[rs2].isvector)  { irs2 += 1; }
+        if (id == VL or irs1 == VL or irs2 == VL) {
+          # end VL hardware loop
+          xSTATE.srcoffs = 0; # reset
+          xSTATE.ssvoffs = 0; # reset
+          return;
+        }