projects / yosys.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | combined (merge: 0c69f1d 7fe770a)
Merge pull request #729 from whitequark/write_verilog_initial
authorClifford Wolf <clifford@clifford.at>
Sun, 16 Dec 2018 14:50:16 +0000 (15:50 +0100)
committerGitHub <noreply@github.com>
Sun, 16 Dec 2018 14:50:16 +0000 (15:50 +0100)
write_verilog: correctly map RTLIL `sync init`


Trivial merge