Use clk pin definition from upstream nmigen-boards

diff --git a/examples/ecpix5_85.py b/examples/ecpix5_85.py
index 5f9cf900317f9eebd2ffb2c3847849dc9b91390a..62f06ef38660a1d61c76233aa170eaed7afdc26a 100644 (file)
--- a/examples/ecpix5_85.py
+++ b/examples/ecpix5_85.py
@@ -56,8 +56,7 @@ class _ECPIX5Platform(LatticeECP5Platform):
         Resource("eth_int", 0, PinsN("B13", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
 
         Resource("ddr3", 0,
-            Subsignal("clk", Pins("H3", dir="o")),
-            #Subsignal("clk",    DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")),
+            Subsignal("clk",    DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")),
             Subsignal("clk_en", Pins("P1", dir="o")),
             Subsignal("we",   PinsN("R3", dir="o")),
             Subsignal("ras",  PinsN("T3", dir="o")),