Arm64: correct 64-bit element fmmla encoding

There's just one bit of difference to the 32-bit element form, as
per the documentation.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 86134cb5b66c16c1d98efda439c96202f7f5e462..933c17e60366768ae7ed703adcfdb32a7d61f75b 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2020-01-03  Jan Beulich  <jbeulich@suse.com>
+
+       * testsuite/gas/aarch64/f64mm.d,
+       testsuite/gas/aarch64/sve-movprfx-mm.d: Adjust expectations.
+
 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 
        * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add

diff --git a/gas/testsuite/gas/aarch64/f64mm.d b/gas/testsuite/gas/aarch64/f64mm.d
index a09179a93be5a64c809c02df4a15c926c8709fcd..b2aa86132ac0db62259190ee4f0b4af56cce19f5 100644 (file)
--- a/gas/testsuite/gas/aarch64/f64mm.d
+++ b/gas/testsuite/gas/aarch64/f64mm.d
@@ -6,8 +6,8 @@
 Disassembly of section \.text:
 
 0+ <\.text>:
- *[0-9a-f]+:   64dbe6b1        fmmla   z17\.d, z21\.d, z27\.d
- *[0-9a-f]+:   64c0e400        fmmla   z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:   64fbe6b1        fmmla   z17\.d, z21\.d, z27\.d
+ *[0-9a-f]+:   64e0e400        fmmla   z0\.d, z0\.d, z0\.d
  *[0-9a-f]+:   a43b17f1        ld1rob  {z17\.b}, p5/z, \[sp, x27\]
  *[0-9a-f]+:   a42003e0        ld1rob  {z0\.b}, p0/z, \[sp, x0\]
  *[0-9a-f]+:   a4bb17f1        ld1roh  {z17\.h}, p5/z, \[sp, x27\]

diff --git a/gas/testsuite/gas/aarch64/sve-movprfx-mm.d b/gas/testsuite/gas/aarch64/sve-movprfx-mm.d
index 88415ef098fee4dce7d0b753c390777fcf8caa4b..f2b480dfe48e41bbaa411d2d974b3788da5c7add 100644 (file)
--- a/gas/testsuite/gas/aarch64/sve-movprfx-mm.d
+++ b/gas/testsuite/gas/aarch64/sve-movprfx-mm.d
@@ -21,4 +21,4 @@ Disassembly of section \.text:
  *[0-9a-f]+:   0420bc11        movprfx z17, z0
  *[0-9a-f]+:   64bbe6b1        fmmla   z17\.s, z21\.s, z27\.s
  *[0-9a-f]+:   0420bc11        movprfx z17, z0
- *[0-9a-f]+:   64dbe6b1        fmmla   z17\.d, z21\.d, z27\.d
+ *[0-9a-f]+:   64fbe6b1        fmmla   z17\.d, z21\.d, z27\.d

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e3be019ec9d6fbfee99a506776ed50d49339d0e7..bf031a76d8085072d9a1ed3711fc10239cdd2401 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2020-01-03  Jan Beulich  <jbeulich@suse.com>
+
+       * opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
+       FMMLA encoding.
+       * opcodes/aarch64-dis-2.c: Re-generate.
+
 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 
        * z80-dis.c: Add support for eZ80 and Z80 instructions.

diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 3de1dc3dca6e01c219b6d841850a9f31e26c963d..950a5f2e99b067db985b0701a999edbf8eed402e 100644 (file)
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -8839,9 +8839,9 @@ aarch64_opcode_lookup_1 (uint32_t word)
                                         }
                                       else
                                         {
-                                          if (((word >> 22) & 0x1) == 0)
+                                          if (((word >> 20) & 0x1) == 0)
                                             {
-                                              if (((word >> 20) & 0x1) == 0)
+                                              if (((word >> 22) & 0x1) == 0)
                                                 {
                                                   /* 33222222222211111111110000000000
                                                      10987654321098765432109876543210
@@ -8855,69 +8855,58 @@ aarch64_opcode_lookup_1 (uint32_t word)
                                                     {
                                                       /* 33222222222211111111110000000000
                                                          10987654321098765432109876543210
-                                                         x11001x00001xxxx111xxxxxxxxxxxxx
-                                                         stnt1b.  */
-                                                      return 1933;
+                                                         x11001x00100xxxx111xxxxxxxxxxxxx
+                                                         st1b.  */
+                                                      return 1872;
                                                     }
                                                   else
                                                     {
                                                       /* 33222222222211111111110000000000
                                                          10987654321098765432109876543210
-                                                         x11001x01001xxxx111xxxxxxxxxxxxx
-                                                         stnt1h.  */
-                                                      return 1937;
+                                                         x11001x01100xxxx111xxxxxxxxxxxxx
+                                                         st1h.  */
+                                                      return 1893;
                                                     }
                                                 }
                                             }
                                           else
                                             {
-                                              if (((word >> 23) & 0x1) == 0)
+                                              if (((word >> 22) & 0x1) == 0)
                                                 {
-                                                  if (((word >> 20) & 0x1) == 0)
+                                                  if (((word >> 23) & 0x1) == 0)
                                                     {
                                                       /* 33222222222211111111110000000000
                                                          10987654321098765432109876543210
-                                                         x11001x00100xxxx111xxxxxxxxxxxxx
-                                                         st1b.  */
-                                                      return 1872;
+                                                         x11001x00001xxxx111xxxxxxxxxxxxx
+                                                         stnt1b.  */
+                                                      return 1933;
                                                     }
                                                   else
                                                     {
                                                       /* 33222222222211111111110000000000
                                                          10987654321098765432109876543210
-                                                         x11001x00101xxxx111xxxxxxxxxxxxx
-                                                         st3b.  */
-                                                      return 1917;
+                                                         x11001x01001xxxx111xxxxxxxxxxxxx
+                                                         stnt1h.  */
+                                                      return 1937;
                                                     }
                                                 }
                                               else
                                                 {
-                                                  if (((word >> 31) & 0x1) == 0)
+                                                  if (((word >> 23) & 0x1) == 0)
                                                     {
                                                       /* 33222222222211111111110000000000
                                                          10987654321098765432109876543210
-                                                         011001x0110xxxxx111xxxxxxxxxxxxx
-                                                         fmmla.  */
-                                                      return 2398;
+                                                         x11001x00101xxxx111xxxxxxxxxxxxx
+                                                         st3b.  */
+                                                      return 1917;
                                                     }
                                                   else
                                                     {
-                                                      if (((word >> 20) & 0x1) == 0)
-                                                        {
-                                                          /* 33222222222211111111110000000000
-                                                             10987654321098765432109876543210
-                                                             111001x01100xxxx111xxxxxxxxxxxxx
-                                                             st1h.  */
-                                                          return 1893;
-                                                        }
-                                                      else
-                                                        {
-                                                          /* 33222222222211111111110000000000
-                                                             10987654321098765432109876543210
-                                                             111001x01101xxxx111xxxxxxxxxxxxx
-                                                             st3h.  */
-                                                          return 1921;
-                                                        }
+                                                      /* 33222222222211111111110000000000
+                                                         10987654321098765432109876543210
+                                                         x11001x01101xxxx111xxxxxxxxxxxxx
+                                                         st3h.  */
+                                                      return 1921;
                                                     }
                                                 }
                                             }
@@ -9780,21 +9769,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
                                                 }
                                               else
                                                 {
-                                                  if (((word >> 20) & 0x1) == 0)
+                                                  if (((word >> 31) & 0x1) == 0)
                                                     {
                                                       /* 33222222222211111111110000000000
                                                          10987654321098765432109876543210
-                                                         x11001x01110xxxx111xxxxxxxxxxxxx
-                                                         st1h.  */
-                                                      return 1895;
+                                                         011001x0111xxxxx111xxxxxxxxxxxxx
+                                                         fmmla.  */
+                                                      return 2398;
                                                     }
                                                   else
                                                     {
-                                                      /* 33222222222211111111110000000000
-                                                         10987654321098765432109876543210
-                                                         x11001x01111xxxx111xxxxxxxxxxxxx
-                                                         st4h.  */
-                                                      return 1929;
+                                                      if (((word >> 20) & 0x1) == 0)
+                                                        {
+                                                          /* 33222222222211111111110000000000
+                                                             10987654321098765432109876543210
+                                                             111001x01110xxxx111xxxxxxxxxxxxx
+                                                             st1h.  */
+                                                          return 1895;
+                                                        }
+                                                      else
+                                                        {
+                                                          /* 33222222222211111111110000000000
+                                                             10987654321098765432109876543210
+                                                             111001x01111xxxx111xxxxxxxxxxxxx
+                                                             st4h.  */
+                                                          return 1929;
+                                                        }
                                                     }
                                                 }
                                             }

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 6a8f794909c615f3423338b4b15924c5c0c56526..8a74777eedbbd7c34eae85af520ef6288f4566a4 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5073,7 +5073,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
   INT8MATMUL_SVE_INSNC ("usdot",  0x44a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
   INT8MATMUL_SVE_INSNC ("sudot",  0x44a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
   F32MATMUL_SVE_INSNC ("fmmla",   0x64a0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0),
-  F64MATMUL_SVE_INSNC ("fmmla",   0x64c0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0),
+  F64MATMUL_SVE_INSNC ("fmmla",   0x64e0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0),
   F64MATMUL_SVE_INSN ("ld1rob",  0xa4200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX),  OP_SVE_BZU, F_OD(1), 0),
   F64MATMUL_SVE_INSN ("ld1roh",  0xa4a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX),  OP_SVE_HZU, F_OD(1), 0),
   F64MATMUL_SVE_INSN ("ld1row",  0xa5200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX),  OP_SVE_SZU, F_OD(1), 0),