add primitives decoding in test_identify to ease debug

diff --git a/targets/test.py b/targets/test.py
index ee140955006e561c57866d363d87f36b63d37d86..a048594ce3f5a8ca8936048677c9db3154d08c3e 100644 (file)
--- a/targets/test.py
+++ b/targets/test.py
@@ -157,8 +157,18 @@ class IdentifyRequester(Module, AutoCSR):
                self._req = CSRStorage()
                req = self._req.storage
 
+               req_d = Signal()
+
+               self.sync += [
+                       req_d.eq(req),
+                       If(req & ~req_d,
+                               sata_con.sink.stb.eq(1)
+                       ).Elif(sata_con.sink.ack,
+                               sata_con.sink.stb.eq(0)
+                       )
+               ]
+
                self.comb += [
-                       sata_con.sink.stb.eq(req),
                        sata_con.sink.sop.eq(1),
                        sata_con.sink.eop.eq(1),
                        sata_con.sink.identify.eq(1),
@@ -182,7 +192,7 @@ class TestDesign(UART2WB, AutoCSR):
                UART2WB.__init__(self, platform, clk_freq)
                self.crg = _CRG(platform)
 
-               self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, host=True, speed="SATA1")
+               self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, host=True, speed="SATA2")
                self.sata_con = SATACON(self.sata_phy, sector_size=512, max_count=8)
 
                self.identify_requester = IdentifyRequester(self.sata_con)

diff --git a/test/test_identify.py b/test/test_identify.py
index 5585b822bcf44b4a70fa25b2bae4728b48b82e58..72c97c0348c15d7d9f05559966383fc134fdff6e 100644 (file)
--- a/test/test_identify.py
+++ b/test/test_identify.py
@@ -1,5 +1,6 @@
 import time
 from config import *
+from miscope.host.dump import *
 from miscope.host.drivers import MiLaDriver
 
 mila = MiLaDriver(wb.regs, "mila", use_rle=False)
@@ -13,13 +14,58 @@ mila.prog_term(port=0, trigger=trigger0, mask=mask0)
 mila.prog_sum("term")
 
 # Trigger / wait / receive
-mila.trigger(offset=32, length=1024)
+mila.trigger(offset=32, length=256)
 regs.identify_requester_req.write(1)
-time.sleep(0.1)
 regs.identify_requester_req.write(0)
 mila.wait_done()
 mila.read()
 mila.export("dump.vcd")
 mila.export("dump.csv")
+mila.export("dump.py")
 ###
 wb.close()
+
+###
+
+primitives = {
+       "ALIGN" :       0x7B4A4ABC,
+       "CONT"  :       0X9999AA7C,
+       "SYNC"  :       0xB5B5957C,
+       "R_RDY" :       0x4A4A957C,
+       "R_OK"  :       0x3535B57C,
+       "R_ERR" :       0x5656B57C,
+       "R_IP"  :       0X5555B57C,
+       "X_RDY" :       0x5757B57C,
+       "CONT"  :       0x9999AA7C,
+       "WTRM"  :       0x5858B57C,
+       "SOF"   :       0x3737B57C,
+       "EOF"   :       0xD5D5B57C,
+       "HOLD"  :       0xD5D5AA7C,
+       "HOLDA" :       0X9595AA7C
+}
+
+def decode_primitive(dword):
+       for k, v in primitives.items():
+               if dword == v:
+                       return k
+       return ""
+
+dump = Dump()
+dump.add_from_layout(mila.layout, mila.dat)
+
+for var in dump.vars:
+       if var.name == "sata_phy_sink_sink_payload_data":
+               tx_data = var.values
+       if var.name == "sata_phy_source_source_payload_data":
+               rx_data = var.values
+
+for i in range(len(tx_data)):
+       tx = "%08x " %tx_data[i]
+       tx += decode_primitive(tx_data[i])
+       tx += " "*(16-len(tx))
+
+       rx = "%08x " %rx_data[i]
+       rx += decode_primitive(rx_data[i])
+       rx += " "*(16-len(rx))
+
+       print(tx + rx)