gas: blackfin: reject invalid 16bit acc add insns

The 16bit acc add insn cannot assign the two results to the same dreg,
so make sure gas rejects attempts to use this insn variant.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 6ccff48ee28065f03db6fb6f585fb3e25436b2b9..fe0c4668b36562901aaa63aa614a8cd0a557ca42 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2011-03-28  Mike Frysinger  <vapier@gentoo.org>
+
+       * config/bfin-parse.y (16bit acc add): Return yyerror when dest
+       reg $1 is the same as dest reg $7.
+
 2011-03-28  H.J. Lu  <hongjiu.lu@intel.com>
 
        * config/tc-i386.c (handle_quad): New.

diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
index 803afd1c55299c2cc1628f4f5d4978b5f3158837..fa81a61dd8f46cbc7f27a60cf0e4a3a302336400 100644 (file)
--- a/gas/config/bfin-parse.y
+++ b/gas/config/bfin-parse.y
@@ -886,6 +886,9 @@ asm_1:
        | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
          REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
        {
+         if (REG_SAME ($1, $7))
+           return yyerror ("Illegal dest register combination");
+
          if (IS_DREG ($1) && IS_DREG ($7))
            {
              notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h  \n");

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 4f69afaca4825d58aad9cddc538185fec10184fe..b4bdca15bfe01cbf89021ce0658a1be507324c9e 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2011-03-28  Mike Frysinger  <vapier@gentoo.org>
+
+       * gas/bfin/expected_errors.s: Add invalid 16bit acc add insn tests.
+       * gas/bfin/expected_errors.l: Add new error messages.
+       * testsuite/gas/bfin/video2.s: Drop invalid 16bit acc add insn.
+       * testsuite/gas/bfin/video2.d: Updated disassembly output.
+
 2011-03-28  H.J. Lu  <hongjiu.lu@intel.com>
 
        * gas/i386/ilp32/inval.s: Remove .quad.

diff --git a/gas/testsuite/gas/bfin/expected_errors.l b/gas/testsuite/gas/bfin/expected_errors.l
index 863b30bdadc28f980935c5ffd7d1f53b3269b4fa..2f746db460b8d5b426694f7f7eb4024e2823b922 100644 (file)
--- a/gas/testsuite/gas/bfin/expected_errors.l
+++ b/gas/testsuite/gas/bfin/expected_errors.l
@@ -100,3 +100,4 @@
 .*:126: Error: Resource conflict in dest reg.
 .*:127: Error: Differing source registers.
 .*:129: Error: Register mismatch.
+.*:131: Error: Illegal dest register combination. Input text was A0.H.

diff --git a/gas/testsuite/gas/bfin/expected_errors.s b/gas/testsuite/gas/bfin/expected_errors.s
index 46be66c3a4728d7ee0b534fb06cd8126554f57b4..f6e3f6f05c0ea52342a42fae720f967fb63c70fc 100644 (file)
--- a/gas/testsuite/gas/bfin/expected_errors.s
+++ b/gas/testsuite/gas/bfin/expected_errors.s
@@ -127,3 +127,5 @@
        R7 = R3 +|- R4, R1 = R1 -|+ R2;
 
        R0 = R3 + R4, R1 = R5 - R6;
+
+       R7 = A1.L + A1.H, R7 = A0.L + A0.H;

diff --git a/gas/testsuite/gas/bfin/video2.d b/gas/testsuite/gas/bfin/video2.d
index b9830d9e8cece5345dfff4fdc8c4ffdccf7b02f7..98f22395fdb8b79e8844c1178d6b5a379c5da2ac 100644 (file)
--- a/gas/testsuite/gas/bfin/video2.d
+++ b/gas/testsuite/gas/bfin/video2.d
@@ -50,7 +50,6 @@ Disassembly of section .text:
 [ 0-9a-f]+:    37 c4 10 0a     R5 = BYTEOP3P \(R3:2, R1:0\) \(HI\);
 [ 0-9a-f]+:    17 c4 10 2c     R6 = BYTEOP3P \(R3:2, R1:0\) \(LO, R\);
 [ 0-9a-f]+:    37 c4 10 2e     R7 = BYTEOP3P \(R3:2, R1:0\) \(HI, R\);
-[ 0-9a-f]+:    0c c4 00 40     R0 = A1.L \+ A1.H, R0 = A0.L \+ A0.H;
 [ 0-9a-f]+:    0c c4 00 42     R0 = A1.L \+ A1.H, R1 = A0.L \+ A0.H;
 [ 0-9a-f]+:    0c c4 80 46     R2 = A1.L \+ A1.H, R3 = A0.L \+ A0.H;
 [ 0-9a-f]+:    0c c4 00 4b     R4 = A1.L \+ A1.H, R5 = A0.L \+ A0.H;

diff --git a/gas/testsuite/gas/bfin/video2.s b/gas/testsuite/gas/bfin/video2.s
index 22fb50f3e5979aca660b07f1bf0475a73fb74f73..4ec9f75e0102bf95c7780baaf4eb442060b21949 100755 (executable)
--- a/gas/testsuite/gas/bfin/video2.s
+++ b/gas/testsuite/gas/bfin/video2.s
@@ -68,7 +68,6 @@ r7 = byteop3p (r3:2, r1:0) (hi, r) ;
 
 //Dreg = A1.L + A1.H, Dreg = A0.L + A0.H ; /* (b) */
 
-R0 = A1.L + A1.H, R0= A0.L + A0.H ;
 R0 = A1.L + A1.H, R1= A0.L + A0.H ;
 R2 = A1.L + A1.H, R3= A0.L + A0.H ;
 R4 = A1.L + A1.H, R5= A0.L + A0.H ;