fix div_mod test

diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys
index 96753b4efed2a15a137c040bfdd5ba0c9574bf59..f55490572b211d60131a0c2e95fc0076df9a7a20 100644 (file)
--- a/tests/ice40/div_mod.ys
+++ b/tests/ice40/div_mod.ys
@@ -4,6 +4,6 @@ flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 88 t:SB_LUT4
+select -assert-count 62 t:SB_LUT4
 select -assert-count 65 t:SB_CARRY
 select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D