Add "whitebox" attribute, add "read_verilog -wb"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/README.md b/README.md
index d000c5d6356c801c005d5cd559e140c15deac036..5c94c34e5d66e5ec5f21c17752f20ca34ba2d2d5 100644 (file)
--- a/README.md
+++ b/README.md
@@ -312,6 +312,10 @@ Verilog Attributes and non-standard features
   passes to identify input and output ports of cells. The Verilog backend
   also does not output blackbox modules on default.
 
+- The ``whitebox`` attribute on modules triggers the same behavior as
+  ``blackbox``, but is for whitebox modules, i.e. library modules that
+  contain a behavioral model of the cell type.
+
 - The ``dynports`` attribute is used by the Verilog front-end to mark modules
   that have ports with a width that depends on a parameter.
 

diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index 0db5ff27c48a43bed19032a9694c184ea17ccd5e..b6dbd84cb0dffda618692d87d0ce14c39df41abc 100644 (file)
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -140,7 +140,7 @@ struct BlifDumper
                        return "subckt";
                if (!design->modules_.count(RTLIL::escape_id(cell_type)))
                        return "gate";
-               if (design->modules_.at(RTLIL::escape_id(cell_type))->get_bool_attribute("\\blackbox"))
+               if (design->modules_.at(RTLIL::escape_id(cell_type))->get_blackbox_attribute())
                        return "gate";
                return "subckt";
        }
@@ -196,7 +196,7 @@ struct BlifDumper
                }
                f << stringf("\n");
 
-               if (module->get_bool_attribute("\\blackbox")) {
+               if (module->get_blackbox_attribute()) {
                        f << stringf(".blackbox\n");
                        f << stringf(".end\n");
                        return;
@@ -640,7 +640,7 @@ struct BlifBackend : public Backend {
                for (auto module_it : design->modules_)
                {
                        RTLIL::Module *module = module_it.second;
-                       if (module->get_bool_attribute("\\blackbox") && !config.blackbox_mode)
+                       if (module->get_blackbox_attribute() && !config.blackbox_mode)
                                continue;
 
                        if (module->processes.size() != 0)

diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 7e30b67af6f29a9f6359e45943dd076f6cc0ec4f..6d9469538eba648522d775a5eb38ac91b02f829d 100644 (file)
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -178,7 +178,7 @@ struct EdifBackend : public Backend {
                for (auto module_it : design->modules_)
                {
                        RTLIL::Module *module = module_it.second;
-                       if (module->get_bool_attribute("\\blackbox"))
+                       if (module->get_blackbox_attribute())
                                continue;
 
                        if (top_module_name.empty())
@@ -192,7 +192,7 @@ struct EdifBackend : public Backend {
                        for (auto cell_it : module->cells_)
                        {
                                RTLIL::Cell *cell = cell_it.second;
-                               if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
+                               if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_blackbox_attribute()) {
                                        lib_cell_ports[cell->type];
                                        for (auto p : cell->connections())
                                                lib_cell_ports[cell->type][p.first] = GetSize(p.second);
@@ -302,7 +302,7 @@ struct EdifBackend : public Backend {
                *f << stringf("    (technology (numberDefinition))\n");
                for (auto module : sorted_modules)
                {
-                       if (module->get_bool_attribute("\\blackbox"))
+                       if (module->get_blackbox_attribute())
                                continue;
 
                        SigMap sigmap(module);

diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 2eb08dbe99aba2432ce227e16e7c74b967097922..b0e3cd252a47db5db1e684bb367c22bfbb09259a 100644 (file)
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -127,7 +127,7 @@ struct IntersynthBackend : public Backend {
                        RTLIL::Module *module = module_it.second;
                        SigMap sigmap(module);
 
-                       if (module->get_bool_attribute("\\blackbox"))
+                       if (module->get_blackbox_attribute())
                                continue;
                        if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells_.size() == 0)
                                continue;

diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index 688535f33a7b3489a9dbad0fc9717d174215f2ad..e318a40517eefcf4d2cd288cd89b96269fd7cc82 100644 (file)
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -1543,7 +1543,7 @@ struct Smt2Backend : public Backend {
 
                for (auto module : sorted_modules)
                {
-                       if (module->get_bool_attribute("\\blackbox") || module->has_memories_warn() || module->has_processes_warn())
+                       if (module->get_blackbox_attribute() || module->has_memories_warn() || module->has_processes_warn())
                                continue;
 
                        log("Creating SMT-LIBv2 representation of module %s.\n", log_id(module));

diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc
index f379c9c4866bed5dd1889006f7ccfb6fcd63dddf..d75456c1b43098c0307c3a3b5846bddc8f1aed91 100644 (file)
--- a/backends/smv/smv.cc
+++ b/backends/smv/smv.cc
@@ -739,7 +739,7 @@ struct SmvBackend : public Backend {
                pool<Module*> modules;
 
                for (auto module : design->modules())
-                       if (!module->get_bool_attribute("\\blackbox") && !module->has_memories_warn() && !module->has_processes_warn())
+                       if (!module->get_blackbox_attribute() && !module->has_memories_warn() && !module->has_processes_warn())
                                modules.insert(module);
 
                if (template_f.is_open())

diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index b6a3f1e77b70202a07a39d7f9f01d3f4a6c64fbd..6738a4bbd6c4a9e7bd10b5847f0bb337283079a9 100644 (file)
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -212,7 +212,7 @@ struct SpiceBackend : public Backend {
                for (auto module_it : design->modules_)
                {
                        RTLIL::Module *module = module_it.second;
-                       if (module->get_bool_attribute("\\blackbox"))
+                       if (module->get_blackbox_attribute())
                                continue;
 
                        if (module->processes.size() != 0)

diff --git a/backends/table/table.cc b/backends/table/table.cc
index b75169ea4637bc99e831ac4affaca8215e1c0e1d..796f18059ff8a7ec584da49f4e56c2f682949850 100644 (file)
--- a/backends/table/table.cc
+++ b/backends/table/table.cc
@@ -67,7 +67,7 @@ struct TableBackend : public Backend {
 
                for (auto module : design->modules())
                {
-                       if (module->get_bool_attribute("\\blackbox"))
+                       if (module->get_blackbox_attribute())
                                continue;
 
                        SigMap sigmap(module);

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 83d83f488090eb81e94726d14b354ae379820557..855409d0b2a1fda22d10425757d818d960f21eaf 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1770,7 +1770,7 @@ struct VerilogBackend : public Backend {
 
                *f << stringf("/* Generated by %s */\n", yosys_version_str);
                for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
-                       if (it->second->get_bool_attribute("\\blackbox") != blackboxes)
+                       if (it->second->get_blackbox_attribute() != blackboxes)
                                continue;
                        if (selected && !design->selected_whole_module(it->first)) {
                                if (design->selected_module(it->first))

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index d489961677c2cfa12dc6df54142c0ab966717c87..720b3f3d15b1df265728a174b196d4028c9af396 100644 (file)
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -46,7 +46,7 @@ namespace AST {
 // instantiate global variables (private API)
 namespace AST_INTERNAL {
        bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
-       bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
+       bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_wb, flag_noopt, flag_icells, flag_autowire;
        AstNode *current_ast, *current_ast_mod;
        std::map<std::string, AstNode*> current_scope;
        const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
@@ -956,7 +956,18 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
                        log("--- END OF AST DUMP ---\n");
                }
 
+               if (flag_wb) {
+                       if (!ast->attributes.count("\\whitebox"))
+                               goto blackbox_module;
+                       AstNode *n = ast->attributes.at("\\whitebox");
+                       if (n->type != AST_CONSTANT)
+                               log_file_error(ast->filename, ast->linenum, "Whitebox attribute with non-constant value!\n");
+                       if (!n->asBool())
+                               goto blackbox_module;
+               }
+
                if (flag_lib) {
+       blackbox_module:
                        std::vector<AstNode*> new_children;
                        for (auto child : ast->children) {
                                if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
@@ -970,6 +981,10 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
                                }
                        }
                        ast->children.swap(new_children);
+                       if (ast->attributes.count("\\whitebox")) {
+                               delete ast->attributes.at("\\whitebox");
+                               ast->attributes.erase("\\whitebox");
+                       }
                        ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
                }
 
@@ -1010,6 +1025,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
        current_module->nomem2reg = flag_nomem2reg;
        current_module->mem2reg = flag_mem2reg;
        current_module->lib = flag_lib;
+       current_module->wb = flag_wb;
        current_module->noopt = flag_noopt;
        current_module->icells = flag_icells;
        current_module->autowire = flag_autowire;
@@ -1026,7 +1042,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 
 // create AstModule instances for all modules in the AST tree and add them to 'design'
 void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil,
-               bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire)
+               bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool wb, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire)
 {
        current_ast = ast;
        flag_dump_ast1 = dump_ast1;
@@ -1040,6 +1056,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
        flag_nomem2reg = nomem2reg;
        flag_mem2reg = mem2reg;
        flag_lib = lib;
+       flag_wb = wb;
        flag_noopt = noopt;
        flag_icells = icells;
        flag_autowire = autowire;
@@ -1374,6 +1391,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
        flag_nomem2reg = nomem2reg;
        flag_mem2reg = mem2reg;
        flag_lib = lib;
+       flag_wb = wb;
        flag_noopt = noopt;
        flag_icells = icells;
        flag_autowire = autowire;

diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index ddd59d4be8174dcb28a1aab7703b2ce4644d977e..610e00fbf290c45c3483a818694aed37751f748d 100644 (file)
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -283,13 +283,13 @@ namespace AST
 
        // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
        void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit,
-                       bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire);
+                       bool nomem2reg, bool mem2reg, bool lib, bool wb, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire);
 
        // parametric modules are supported directly by the AST library
        // therefore we need our own derivate of RTLIL::Module with overloaded virtual functions
        struct AstModule : RTLIL::Module {
                AstNode *ast;
-               bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
+               bool nolatches, nomeminit, nomem2reg, mem2reg, lib, wb, noopt, icells, autowire;
                ~AstModule() YS_OVERRIDE;
                RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE;
                RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail) YS_OVERRIDE;

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 504f8b3f3f2d844876fe9bc550a4f28efab8d479..4e2c5abb5b8297d6f2fa5a83d5851a045bd8d699 100644 (file)
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -148,6 +148,10 @@ struct VerilogFrontend : public Frontend {
                log("    -lib\n");
                log("        only create empty blackbox modules. This implies -DBLACKBOX.\n");
                log("\n");
+               log("    -wb\n");
+               log("        like -lib, except do not touch modules with the whitebox\n");
+               log("        attribute set. This also implies -DBLACKBOX.\n");
+               log("\n");
                log("    -noopt\n");
                log("        don't perform basic optimizations (such as const folding) in the\n");
                log("        high-level front-end.\n");
@@ -228,6 +232,7 @@ struct VerilogFrontend : public Frontend {
                norestrict_mode = false;
                assume_asserts_mode = false;
                lib_mode = false;
+               wb_mode = false;
                default_nettype_wire = true;
 
                log_header(design, "Executing Verilog-2005 frontend.\n");
@@ -329,11 +334,16 @@ struct VerilogFrontend : public Frontend {
                                flag_nodpi = true;
                                continue;
                        }
-                       if (arg == "-lib") {
+                       if (arg == "-lib" && !wb_mode) {
                                lib_mode = true;
                                defines_map["BLACKBOX"] = string();
                                continue;
                        }
+                       if (arg == "-wb" && !lib_mode) {
+                               wb_mode = true;
+                               defines_map["BLACKBOX"] = string();
+                               continue;
+                       }
                        if (arg == "-noopt") {
                                flag_noopt = true;
                                continue;
@@ -429,7 +439,7 @@ struct VerilogFrontend : public Frontend {
                if (flag_nodpi)
                        error_on_dpi_function(current_ast);
 
-               AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
+               AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, wb_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
 
                if (!flag_nopp)
                        delete lexin;

diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h
index 523bbc89786defa4166302fda5c405850ca476d6..b5cf70c5798943cb3e5680de4c2f69ce772d7b16 100644 (file)
--- a/frontends/verilog/verilog_frontend.h
+++ b/frontends/verilog/verilog_frontend.h
@@ -72,6 +72,9 @@ namespace VERILOG_FRONTEND
        // running in -lib mode
        extern bool lib_mode;
 
+       // running in -wb mode
+       extern bool wb_mode;
+
        // lexer input stream
        extern std::istream *lexin;
 }

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 52685f6374df2cce3572af49faf18e7d585936c5..122eb123047fe3d13a741173b568722f26107cdd 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -59,7 +59,7 @@ namespace VERILOG_FRONTEND {
        std::vector<char> case_type_stack;
        bool do_not_require_port_stubs;
        bool default_nettype_wire;
-       bool sv_mode, formal_mode, lib_mode;
+       bool sv_mode, formal_mode, lib_mode, wb_mode;
        bool noassert_mode, noassume_mode, norestrict_mode;
        bool assume_asserts_mode, assert_assumes_mode;
        bool current_wire_rand, current_wire_const;
@@ -1906,7 +1906,7 @@ basic_expr:
                if ($4->substr(0, 1) != "'")
                        frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
                AstNode *bits = $2;
-               AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
+               AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode && !wb_mode);
                if (val == NULL)
                        log_error("Value conversion failed: `%s'\n", $4->c_str());
                $$ = new AstNode(AST_TO_BITS, bits, val);
@@ -1917,7 +1917,7 @@ basic_expr:
                        frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
                AstNode *bits = new AstNode(AST_IDENTIFIER);
                bits->str = *$1;
-               AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
+               AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode && !wb_mode);
                if (val == NULL)
                        log_error("Value conversion failed: `%s'\n", $2->c_str());
                $$ = new AstNode(AST_TO_BITS, bits, val);
@@ -1925,14 +1925,14 @@ basic_expr:
                delete $2;
        } |
        TOK_CONSTVAL TOK_CONSTVAL {
-               $$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
+               $$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode && !wb_mode);
                if ($$ == NULL || (*$2)[0] != '\'')
                        log_error("Value conversion failed: `%s%s'\n", $1->c_str(), $2->c_str());
                delete $1;
                delete $2;
        } |
        TOK_CONSTVAL {
-               $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
+               $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode && !wb_mode);
                if ($$ == NULL)
                        log_error("Value conversion failed: `%s'\n", $1->c_str());
                delete $1;

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 9ae20a317451922b28865393caf158a25bbec37e..2f8715755442b91ac59707c7056756bf832c2679 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -589,7 +589,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
        std::vector<RTLIL::Module*> result;
        result.reserve(modules_.size());
        for (auto &it : modules_)
-               if (selected_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
+               if (selected_module(it.first) && !it.second->get_blackbox_attribute())
                        result.push_back(it.second);
        return result;
 }
@@ -599,7 +599,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
        std::vector<RTLIL::Module*> result;
        result.reserve(modules_.size());
        for (auto &it : modules_)
-               if (selected_whole_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
+               if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
                        result.push_back(it.second);
        return result;
 }
@@ -609,7 +609,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
        std::vector<RTLIL::Module*> result;
        result.reserve(modules_.size());
        for (auto &it : modules_)
-               if (it.second->get_bool_attribute("\\blackbox"))
+               if (it.second->get_blackbox_attribute())
                        continue;
                else if (selected_whole_module(it.first))
                        result.push_back(it.second);

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index fb045bc7213ffda120c87c3d88b89f55b51a056c..176dc3fc2d5940d8e3e5f885592c4e9f6eafa43b 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -569,6 +569,10 @@ struct RTLIL::AttrObject
        void set_bool_attribute(RTLIL::IdString id);
        bool get_bool_attribute(RTLIL::IdString id) const;
 
+       bool get_blackbox_attribute() const {
+               return get_bool_attribute("\\blackbox") || get_bool_attribute("\\whitebox");
+       }
+
        void set_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
        void add_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
        pool<string> get_strpool_attribute(RTLIL::IdString id) const;

diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index cfccca966473cb75f842320ffb4cd1b491dc9514..af6f7043d38b4a478d23c06245a478501460d997 100644 (file)
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -71,7 +71,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
                RTLIL::Module *mod = design->modules_.at(it.second->type);
                if (!design->selected_whole_module(mod->name))
                        continue;
-               if (mod->get_bool_attribute("\\blackbox"))
+               if (mod->get_blackbox_attribute())
                        continue;
                if (it.second->hasPort(name))
                        continue;

diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc
index 606276e6438b751ec877ed10d90c9290d90efc81..4b22f6d2de3d18629f2bde2d7938bbfd63a89ad0 100644 (file)
--- a/passes/cmds/bugpoint.cc
+++ b/passes/cmds/bugpoint.cc
@@ -128,7 +128,7 @@ struct BugpointPass : public Pass {
                {
                        for (auto &it : design_copy->modules_)
                        {
-                               if (it.second->get_bool_attribute("\\blackbox"))
+                               if (it.second->get_blackbox_attribute())
                                        continue;
 
                                if (index++ == seed)
@@ -143,7 +143,7 @@ struct BugpointPass : public Pass {
                {
                        for (auto mod : design_copy->modules())
                        {
-                               if (mod->get_bool_attribute("\\blackbox"))
+                               if (mod->get_blackbox_attribute())
                                        continue;
 
                                for (auto wire : mod->wires())
@@ -168,7 +168,7 @@ struct BugpointPass : public Pass {
                {
                        for (auto mod : design_copy->modules())
                        {
-                               if (mod->get_bool_attribute("\\blackbox"))
+                               if (mod->get_blackbox_attribute())
                                        continue;
 
                                for (auto &it : mod->cells_)
@@ -186,7 +186,7 @@ struct BugpointPass : public Pass {
                {
                        for (auto mod : design_copy->modules())
                        {
-                               if (mod->get_bool_attribute("\\blackbox"))
+                               if (mod->get_blackbox_attribute())
                                        continue;
 
                                for (auto cell : mod->cells())

diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 58acd302d07ebde009addeb27614b18a59c84e4e..8b1b43f442d149c4301d3cedb6f59c28bd9b3dfb 100644 (file)
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -555,7 +555,7 @@ struct ShowWorker
                        if (!design->selected_module(module->name))
                                continue;
                        if (design->selected_whole_module(module->name)) {
-                               if (module->get_bool_attribute("\\blackbox")) {
+                               if (module->get_blackbox_attribute()) {
                                        // log("Skipping blackbox module %s.\n", id2cstr(module->name));
                                        continue;
                                } else
@@ -771,7 +771,7 @@ struct ShowPass : public Pass {
                if (format != "ps" && format != "dot") {
                        int modcount = 0;
                        for (auto &mod_it : design->modules_) {
-                               if (mod_it.second->get_bool_attribute("\\blackbox"))
+                               if (mod_it.second->get_blackbox_attribute())
                                        continue;
                                if (mod_it.second->cells_.empty() && mod_it.second->connections().empty())
                                        continue;

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 88c339e8ca72c8e9ea9c8fb106e3bb237dec05a4..b8ff99884b6e88cb4d4650eedd529c2a01bc4eb6 100644 (file)
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -346,9 +346,9 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
                }
                RTLIL::Module *mod = design->modules_[cell->type];
 
-               if (design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
+               if (design->modules_.at(cell->type)->get_blackbox_attribute()) {
                        if (flag_simcheck)
-                               log_error("Module `%s' referenced in module `%s' in cell `%s' is a blackbox module.\n",
+                               log_error("Module `%s' referenced in module `%s' in cell `%s' is a blackbox/whitebox module.\n",
                                                cell->type.c_str(), module->name.c_str(), cell->name.c_str());
                        continue;
                }
@@ -451,7 +451,7 @@ void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*, IdString::
 
        if (indent == 0)
                log("Top module:  %s\n", mod->name.c_str());
-       else if (!mod->get_bool_attribute("\\blackbox"))
+       else if (!mod->get_blackbox_attribute())
                log("Used module: %*s%s\n", indent, "", mod->name.c_str());
        used.insert(mod);
 
@@ -491,7 +491,7 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
 
        int del_counter = 0;
        for (auto mod : del_modules) {
-               if (!purge_lib && mod->get_bool_attribute("\\blackbox"))
+               if (!purge_lib && mod->get_blackbox_attribute())
                        continue;
                log("Removing unused module `%s'.\n", mod->name.c_str());
                design->modules_.erase(mod->name);
@@ -910,7 +910,7 @@ struct HierarchyPass : public Pass {
                        if (m == nullptr)
                                continue;
 
-                       if (m->get_bool_attribute("\\blackbox") && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) {
+                       if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) {
                                IdString new_m_name = m->derive(design, cell->parameters, true);
                                if (new_m_name.empty())
                                        continue;

diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc
index e6154e94f49e580293ddd4b6eec63bd4af0ccc97..ad3220918c8005ee126a972d7bfcc32376eacbdd 100644 (file)
--- a/passes/hierarchy/uniquify.cc
+++ b/passes/hierarchy/uniquify.cc
@@ -75,7 +75,7 @@ struct UniquifyPass : public Pass {
                                        if (tmod == nullptr)
                                                continue;
 
-                                       if (tmod->get_bool_attribute("\\blackbox"))
+                                       if (tmod->get_blackbox_attribute())
                                                continue;
 
                                        if (tmod->get_bool_attribute("\\unique") && newname == tmod->name)

diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 274177a684e023f14415dd75e050c5e7bb989366..b5c0498d00158524b4c04563b1a0398bc3a8fd12 100644 (file)
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -664,7 +664,7 @@ struct DfflibmapPass : public Pass {
                logmap_all();
 
                for (auto &it : design->modules_)
-                       if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox"))
+                       if (design->selected(it.second) && !it.second->get_blackbox_attribute())
                                dfflibmap(design, it.second, prepare_mode);
 
                cell_mappings.clear();

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index d0e5e22367184eb7f96dcca3690dd8d32361fa30..d694e8165e5fc154d186279bc2db23f8f8d2c639 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -472,7 +472,7 @@ struct TechmapWorker
                                RTLIL::Module *tpl = map->modules_[tpl_name];
                                std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
 
-                               if (tpl->get_bool_attribute("\\blackbox"))
+                               if (tpl->get_blackbox_attribute())
                                        continue;
 
                                if (!flatten_mode)
@@ -1209,7 +1209,7 @@ struct FlattenPass : public Pass {
 
                        dict<RTLIL::IdString, RTLIL::Module*> new_modules;
                        for (auto mod : vector<Module*>(design->modules()))
-                               if (used_modules[mod->name] || mod->get_bool_attribute("\\blackbox")) {
+                               if (used_modules[mod->name] || mod->get_blackbox_attribute()) {
                                        new_modules[mod->name] = mod;
                                } else {
                                        log("Deleting now unused module %s.\n", log_id(mod));