[AArch64] Update FPSR/FPCR fields for FPU and SVE

I noticed some missing flags/fields from FPSR and FPCR registers in
both the FPU and SVE target descriptions.

This patch adds those and makes the SVE versions of FPSR and FPCR
use the proper flags/bitfields types.

diff --git a/gdb/features/aarch64-fpu.c b/gdb/features/aarch64-fpu.c
index a80b7d4c1b8676571325ff9cb19723928a051338..27e75524cfee5184b62a7045dbe9e16b13e09823 100644 (file)
--- a/gdb/features/aarch64-fpu.c
+++ b/gdb/features/aarch64-fpu.c
@@ -126,8 +126,11 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum)
   tdesc_add_flag (type_with_fields, 10, "OFE");
   tdesc_add_flag (type_with_fields, 11, "UFE");
   tdesc_add_flag (type_with_fields, 12, "IXE");
+  tdesc_add_flag (type_with_fields, 13, "EBF");
   tdesc_add_flag (type_with_fields, 15, "IDE");
+  tdesc_add_bitfield (type_with_fields, "Len", 16, 18);
   tdesc_add_flag (type_with_fields, 19, "FZ16");
+  tdesc_add_bitfield (type_with_fields, "Stride", 20, 21);
   tdesc_add_bitfield (type_with_fields, "RMode", 22, 23);
   tdesc_add_flag (type_with_fields, 24, "FZ");
   tdesc_add_flag (type_with_fields, 25, "DN");

diff --git a/gdb/features/aarch64-fpu.xml b/gdb/features/aarch64-fpu.xml
index 4db5c50f2509773dd5093cc01a0afeca39a15528..89bbcc0a8556208abec6504748f6d25146c334e2 100644 (file)
--- a/gdb/features/aarch64-fpu.xml
+++ b/gdb/features/aarch64-fpu.xml
@@ -142,11 +142,25 @@
     <field name="UFE" start="11" end="11"/>
     <!-- Inexact floating-point exception trap enable.  -->
     <field name="IXE" start="12" end="12"/>
+    <!-- The value of this bit controls the numeric behaviors of BFloat16 dot
+        product calculations performed by the BFDOT, BFMMLA, BFMOPA, and
+        BFMOPS instructions when FEAT_EBF16 is implemented.  -->
+    <field name="EBF" start="13" end="13"/>
     <!-- Input Denormal floating-point exception trap enable.  -->
     <field name="IDE" start="15" end="15"/>
+    <!-- This field has no function in AArch64 state, and non-zero values are
+        ignored during execution in AArch64 state.
+        This field is included only for context saving and restoration of
+        the AArch32 FPSCR.Len field.  -->
+    <field name="Len" start="16" end="18"/>
     <!-- Flush-to-zero mode control bit on half-precision data-processing
          instructions.  -->
     <field name="FZ16" start="19" end="19"/>
+    <!-- This field has no function in AArch64 state, and non-zero values are
+        ignored during execution in AArch64 state.
+        This field is included only for context saving and restoration of the
+        AArch32 FPSCR.Stride field.  -->
+    <field name="Stride" start="20" end="21"/>
     <!-- Rounding Mode control field.  -->
     <field name="RMode" start="22" end="23"/>
     <!-- Flush-to-zero mode control bit.  -->

diff --git a/gdb/features/aarch64-sve.c b/gdb/features/aarch64-sve.c
index 54182e850903171125a09cfde046633515206ae5..fe25f812afc0bd08eb5c416dee705f35519943ea 100644 (file)
--- a/gdb/features/aarch64-sve.c
+++ b/gdb/features/aarch64-sve.c
@@ -121,6 +121,40 @@ create_feature_aarch64_sve (struct target_desc *result, long regnum,
   field_type = tdesc_named_type (feature, "uint8");
   tdesc_create_vector (feature, "svep", field_type, 2 * scale);
 
+  /* FPSR register type */
+  type_with_fields = tdesc_create_flags (feature, "fpsr_flags", 4);
+  tdesc_add_flag (type_with_fields, 0, "IOC");
+  tdesc_add_flag (type_with_fields, 1, "DZC");
+  tdesc_add_flag (type_with_fields, 2, "OFC");
+  tdesc_add_flag (type_with_fields, 3, "UFC");
+  tdesc_add_flag (type_with_fields, 4, "IXC");
+  tdesc_add_flag (type_with_fields, 7, "IDC");
+  tdesc_add_flag (type_with_fields, 27, "QC");
+  tdesc_add_flag (type_with_fields, 28, "V");
+  tdesc_add_flag (type_with_fields, 29, "C");
+  tdesc_add_flag (type_with_fields, 30, "Z");
+  tdesc_add_flag (type_with_fields, 31, "N");
+
+  /* FPCR register type */
+  type_with_fields = tdesc_create_flags (feature, "fpcr_flags", 4);
+  tdesc_add_flag (type_with_fields, 0, "FIZ");
+  tdesc_add_flag (type_with_fields, 1, "AH");
+  tdesc_add_flag (type_with_fields, 2, "NEP");
+  tdesc_add_flag (type_with_fields, 8, "IOE");
+  tdesc_add_flag (type_with_fields, 9, "DZE");
+  tdesc_add_flag (type_with_fields, 10, "OFE");
+  tdesc_add_flag (type_with_fields, 11, "UFE");
+  tdesc_add_flag (type_with_fields, 12, "IXE");
+  tdesc_add_flag (type_with_fields, 13, "EBF");
+  tdesc_add_flag (type_with_fields, 15, "IDE");
+  tdesc_add_bitfield (type_with_fields, "Len", 16, 18);
+  tdesc_add_flag (type_with_fields, 19, "FZ16");
+  tdesc_add_bitfield (type_with_fields, "Stride", 20, 21);
+  tdesc_add_bitfield (type_with_fields, "RMode", 22, 23);
+  tdesc_add_flag (type_with_fields, 24, "FZ");
+  tdesc_add_flag (type_with_fields, 25, "DN");
+  tdesc_add_flag (type_with_fields, 26, "AHP");
+
   tdesc_create_reg (feature, "z0", regnum++, 1, NULL, 128 * scale, "svev");
   tdesc_create_reg (feature, "z1", regnum++, 1, NULL, 128 * scale, "svev");
   tdesc_create_reg (feature, "z2", regnum++, 1, NULL, 128 * scale, "svev");
@@ -153,8 +187,8 @@ create_feature_aarch64_sve (struct target_desc *result, long regnum,
   tdesc_create_reg (feature, "z29", regnum++, 1, NULL, 128 * scale, "svev");
   tdesc_create_reg (feature, "z30", regnum++, 1, NULL, 128 * scale, "svev");
   tdesc_create_reg (feature, "z31", regnum++, 1, NULL, 128 * scale, "svev");
-  tdesc_create_reg (feature, "fpsr", regnum++, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "fpcr", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "fpsr", regnum++, 1, NULL, 32, "fpsr_flags");
+  tdesc_create_reg (feature, "fpcr", regnum++, 1, NULL, 32, "fpcr_flags");
   tdesc_create_reg (feature, "p0", regnum++, 1, NULL, 16 * scale, "svep");
   tdesc_create_reg (feature, "p1", regnum++, 1, NULL, 16 * scale, "svep");
   tdesc_create_reg (feature, "p2", regnum++, 1, NULL, 16 * scale, "svep");