(no commit message)

diff --git a/openpower/sv/microcontroller_power_isa_for_ai.mdwn b/openpower/sv/microcontroller_power_isa_for_ai.mdwn
index 76635dd1f5b3fc65829cd37308a92142cae8f409..15a13ade96ee82e1f3e0f36709879b00f7018565 100644 (file)
--- a/openpower/sv/microcontroller_power_isa_for_ai.mdwn
+++ b/openpower/sv/microcontroller_power_isa_for_ai.mdwn
@@ -107,6 +107,11 @@ the idea of using multiple instructions to construct bigger integer values is no
   * only 32 16-bit registers would be alarmingly resource pressured, particularly given that 4 of them would be needed to construct a 64 bit LD/ST address
   * 128 16-bit registers on the other hand are equivalent to 32 64-bit regs and Computer Science shows we are comfortable with that quantity.
 
+4. Power ISA already has load-quad and store-quad which span 2
+   registers: transparent seamless spanning of more than one
+   register to create larger operands and larger results is
+   therefore not even a foriegn concept to Power.
+
 given the ease with which both 32 and 64 bit addresses may be constructed, and 32 and 64 bit integer arithmetic (and beyond) may be created using multiple instructions *and* how much more efficient that can be done by leveraging SVP64, what at first sounded like an absolutely insane-to-the-point-of-laughable idea instead would be not only workable but combine General-Purpose Compute and AI workloads into a single hybrid ISA.
 
 as you are no doubt aware this has been the focus of so many unsuccessful ventures for so many decades, it would be nice to have one that worked. but, by definition, being "General" Purpose Compute (that happens to also be Supercomputing AI capable) it starts at the ISA and grows from there.