arm: Make the fp register types 64 bits.

This matches the other ISAs.

Change-Id: I84de91efde2529f4aecc7b26b84266d97459738c
Reviewed-on: https://gem5-review.googlesource.com/c/13622
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index e7defd1824061eba0c8efd060dce88b17126568a..3c675cf772c3bec542ab854bb540203003a9f7ef 100644 (file)
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -62,8 +62,8 @@ using ArmISAInst::MaxMiscDestRegs;
 typedef uint64_t IntReg;
 
 // floating point register file entry type
-typedef uint32_t FloatRegBits;
-typedef float FloatReg;
+typedef uint64_t FloatRegBits;
+typedef double FloatReg;
 
 // Number of VecElem per Vector Register, computed based on the vector length
 constexpr unsigned NumVecElemPerVecReg = 4;