sim: Add a << overload for the Port class which prints its name.

This makes it easier/less verbose to print the name of a port, it's
most important and identifying feature, in a DPRINTF or other stream
based output.

Change-Id: I050d102844612577f9a83d550e619736507a6781
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20234
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/sim/port.hh b/src/sim/port.hh
index 1114172637702fbaaa16e5b7be3b5d80604e67b1..2acdb7a7880cf2e119c105f83e359ea3019cf059 100644 (file)
--- a/src/sim/port.hh
+++ b/src/sim/port.hh
@@ -147,4 +147,11 @@ class Port
     }
 };
 
+static inline std::ostream &
+operator << (std::ostream &os, const Port &port)
+{
+    os << port.name();
+    return os;
+}
+
 #endif //__SIM_PORT_HH__