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lkcl
<lkcl@web>
Thu, 30 Jun 2022 19:48:08 +0000
(20:48 +0100)
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IkiWiki
<ikiwiki.info>
Thu, 30 Jun 2022 19:48:08 +0000
(20:48 +0100)
openpower/sv/mv.swizzle.mdwn
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diff --git
a/openpower/sv/mv.swizzle.mdwn
b/openpower/sv/mv.swizzle.mdwn
index 7273e46407b2ce201e128f7fd9a3797e7a18a28f..d82a18751f133a75830b654f1b1cd5135d674973 100644
(file)
--- a/
openpower/sv/mv.swizzle.mdwn
+++ b/
openpower/sv/mv.swizzle.mdwn
@@
-125,7
+125,9
@@
indivisible: an Exception or Interrupt may not occur during the Moves.
Note that unlike the Vectorised variant, when `RT=RA` the Scalar variant
*must* buffer (read) both 64-bit RA registers before writing to the
-RT pair. This ensures that register file corruption does not occur.
+RT pair (in an Out-of-Order Micro-architecture, both of the register
+pair must be "in-flight").
+This ensures that register file corruption does not occur.
**SVP64 Vectorised**