genrtlil: Fix displaying debug info in packages
authorKamil Rakoczy <krakoczy@antmicro.com>
Wed, 20 Oct 2021 07:07:22 +0000 (09:07 +0200)
committerZachary Snow <zachary.j.snow@gmail.com>
Wed, 10 Nov 2021 00:31:39 +0000 (01:31 +0100)
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
frontends/ast/genrtlil.cc

index a68bcd9ee6a47d7e169b8a29a7b6bddf1457c349..ed709aa33d34c726a2e3fecc5c78208c55849197 100644 (file)
@@ -1126,8 +1126,9 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 
        // everything should have been handled above -> print error if not.
        default:
+               AstNode *current_scope_ast = current_ast_mod == nullptr ? current_ast : current_ast_mod;
                for (auto f : log_files)
-                       current_ast_mod->dumpAst(f, "verilog-ast> ");
+                       current_scope_ast->dumpAst(f, "verilog-ast> ");
                log_file_error(filename, location.first_line, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
        }