ARM: fix some cases where instructions that write to fp reg 15 are accidently branches.

diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 2ccda65e17e8fbf8b186b80143e04adf6bc9d400..871378f3fd3f920e3b1fd27fa34cc21136c3d1dc 100644 (file)
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -1122,7 +1122,7 @@ def template LoadRegConstructor {{
 #if %(use_uops)d
         assert(numMicroops >= 2);
         uops = new StaticInstPtr[numMicroops];
-        if (_dest == INTREG_PC) {
+        if (_dest == INTREG_PC && !isFloating()) {
             IntRegIndex wbIndexReg = index;
             uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
                                        _shiftAmt, _shiftType, _index);
@@ -1156,7 +1156,7 @@ def template LoadRegConstructor {{
 
         }
 #else
-        if (_dest == INTREG_PC) {
+        if (_dest == INTREG_PC && !isFloating()) {
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (conditional)
@@ -1185,7 +1185,7 @@ def template LoadImmConstructor {{
 #if %(use_uops)d
         assert(numMicroops >= 2);
         uops = new StaticInstPtr[numMicroops];
-        if (_dest == INTREG_PC) {
+        if (_dest == INTREG_PC && !isFloating()) {
             uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
                                    _imm);
             uops[0]->setDelayedCommit();
@@ -1208,7 +1208,7 @@ def template LoadImmConstructor {{
             uops[1]->setLastMicroop();
         }
 #else
-        if (_dest == INTREG_PC) {
+        if (_dest == INTREG_PC && !isFloating()) {
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (conditional)

diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 918029cc26b423f1ed09ebdc434d11f29a4019ff..42f515a3c8ad85b1325abd42d355d57b4dd2de01 100644 (file)
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -77,7 +77,7 @@ def template DataImmConstructor {{
             }
         }
 
-        if (%(is_branch)s){
+        if (%(is_branch)s && !isFloating()){
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (condCode == COND_AL || condCode == COND_UC)
@@ -117,7 +117,7 @@ def template DataRegConstructor {{
             }
         }
 
-        if (%(is_branch)s){
+        if (%(is_branch)s && !isFloating()){
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (condCode == COND_AL || condCode == COND_UC)