instanciate GTXE2_COMMON (seems recommended in AR43339)

diff --git a/lib/sata/k7sataphy/crg.py b/lib/sata/k7sataphy/crg.py
index 1bbec2cbf5cf36e787d957b0a5e496cfd4a7d021..e71339f82d77947a485a088bd8234b642252fe2e 100644 (file)
--- a/lib/sata/k7sataphy/crg.py
+++ b/lib/sata/k7sataphy/crg.py
@@ -5,6 +5,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.fsm import FSM, NextState
 
 from lib.sata.k7sataphy.std import *
+from lib.sata.k7sataphy.gtx import GTXE2_COMMON
 
 class K7SATAPHYReconfig(Module):
        def __init__(self, channel_drp, mmcm_drp):
@@ -45,6 +46,15 @@ class K7SATAPHYCRG(Module):
                )
                self.comb += gtx.gtrefclk0.eq(refclk)
 
+       # QPLL
+               # not used be need to be there... see AR43339...
+               gtx_common = GTXE2_COMMON()
+               self.comb += [
+                       gtx_common.refclk0.eq(refclk),
+                       gtx.qpllclk.eq(gtx_common.qpllclk),
+                       gtx.qpllrefclk.eq(gtx_common.qpllrefclk),
+               ]
+
        # TX clocking
                # (SATA3) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 300MHz (16-bits)
                # (SATA2) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 150MHz (16-bits)

diff --git a/lib/sata/k7sataphy/gtx.py b/lib/sata/k7sataphy/gtx.py
index 2ba6f7c59651b534fea875e7ebda4e0faf9a8aef..90b97b5be62ff715f65ded48f43eeacfe18b8ab3 100644 (file)
--- a/lib/sata/k7sataphy/gtx.py
+++ b/lib/sata/k7sataphy/gtx.py
@@ -227,6 +227,10 @@ class K7SATAPHYGTX(Module):
                        self.rxphalignen.eq(0),
                ]
 
+       # QPLL input clock      
+               self.qpllclk = Signal()
+               self.qpllrefclk = Signal()
+
        # Instance
                gtxe2_channel_parameters = {
                                # Simulation-Only Attributes
@@ -542,8 +546,8 @@ class K7SATAPHYGTX(Module):
 
                                # Clocking Ports
                                        #o_GTREFCLKMONITOR=,
-                                       i_QPLLCLK=0,
-                                       i_QPLLREFCLK=0,
+                                       i_QPLLCLK=self.qpllclk,
+                                       i_QPLLREFCLK=self.qpllrefclk,
                                        i_RXSYSCLKSEL=0b00,
                                        i_TXSYSCLKSEL=0b00,
 
@@ -865,3 +869,105 @@ class K7SATAPHYGTX(Module):
 
                                        **gtxe2_channel_parameters
                        )
+
+
+class GTXE2_COMMON(Module):
+       def __init__(self, fbdiv=16):
+               self.refclk0 = Signal()
+
+               self.qpllclk = Signal()
+               self.qpllrefclk = Signal()
+
+               # fbdiv config
+               fbdiv_in_config = {
+                       16 :    0b0000100000,
+                       20 :    0b0000110000,
+                       32 :    0b0001100000,
+                       40 :    0b0010000000,
+                       64 :    0b0011100000,
+                       66 :    0b0101000000,
+                       80 :    0b0100100000,
+                       100 :   0b0101110000
+               }
+               fbdiv_in = fbdiv_in_config[fbdiv]
+
+               fbdiv_ratio_config = {
+                       16 :    0b1,
+                       20 :    0b1,
+                       32 :    0b1,
+                       40 :    0b1,
+                       64 :    0b1,
+                       66 :    0b0,
+                       80 :    0b1,
+                       100 :   0b1
+               }
+               fbdiv_ratio = fbdiv_ratio_config[fbdiv]
+
+               self.specials += \
+                       Instance("GTXE2_COMMON",
+                               # Simulation attributes
+                                       p_SIM_RESET_SPEEDUP="TRUE",
+                                       p_SIM_QPLLREFCLK_SEL=0b001,
+                                       p_SIM_VERSION="4.0",
+
+                               # Common block attributes
+                                       p_BIAS_CFG=0x0000040000001000,
+                                       p_COMMON_CFG=0,
+                                       p_QPLL_CFG=0x06801c1,
+                                       p_QPLL_CLKOUT_CFG=0,
+                                       p_QPLL_COARSE_FREQ_OVRD=0b010000,
+                                       p_QPLL_COARSE_FREQ_OVRD_EN=0,
+                                       p_QPLL_CP=0b0000011111,
+                                       p_QPLL_CP_MONITOR_EN=0,
+                                       p_QPLL_DMONITOR_SEL=0,
+                                       p_QPLL_FBDIV=fbdiv_in,
+                                       p_QPLL_FBDIV_MONITOR_EN=0,
+                                       p_QPLL_FBDIV_RATIO=fbdiv_ratio,
+                                       p_QPLL_INIT_CFG=0x000006,
+                                       p_QPLL_LOCK_CFG=0x21e9,
+                                       p_QPLL_LPF=0b1111,
+                                       p_QPLL_REFCLK_DIV=1,
+
+                               # Common block - Dynamic Reconfiguration Port (DRP)
+                                       i_DRPADDR=0,
+                                       i_DRPCLK=0,
+                                       i_DRPDI=0,
+                                       #o_DRPDO=,
+                                       i_DRPEN=0,
+                                       #o_DRPRDY=,
+                                       i_DRPWE=0,
+
+                               # Common block  - Ref Clock Ports
+                                       i_GTGREFCLK=0,
+                                       i_GTNORTHREFCLK0=0,
+                                       i_GTNORTHREFCLK1=0,
+                                       i_GTREFCLK0=self.refclk0,
+                                       i_GTREFCLK1=0,
+                                       i_GTSOUTHREFCLK0=0,
+                                       i_GTSOUTHREFCLK1=0,
+
+                               # Common block - QPLL Ports
+                                       #o_QPLLDMONITOR=,
+                                       #o_QPLLFBCLKLOST=,
+                                       #o_QPLLLOCK=,
+                                       i_QPLLLOCKDETCLK=0,
+                                       i_QPLLLOCKEN=1,
+                                       o_QPLLOUTCLK=self.qpllclk,
+                                       o_QPLLOUTREFCLK=self.qpllrefclk,
+                                       i_QPLLOUTRESET=0,
+                                       i_QPLLPD=0,
+                                       #o_QPLLREFCLKLOST=,
+                                       i_QPLLREFCLKSEL=0b001,
+                                       i_QPLLRESET=0,
+                                       i_QPLLRSVD1=0,
+                                       i_QPLLRSVD2=ones(5),
+                                       #o_REFCLKOUTMONITOR=,
+
+                               # Common block Ports
+                                       i_BGBYPASSB=1,
+                                       i_BGMONITORENB=1,
+                                       i_BGPDB=1,
+                                       i_BGRCALOVRD=0,
+                                       i_PMARSVD=0,
+                                       i_RCALENB=1
+                       )

diff --git a/targets/test.py b/targets/test.py
index b08987442e79748bea9597d80305503b0fb3e013..1e4fa8dc491e35652b31edb90c7f35923d2cade2 100644 (file)
--- a/targets/test.py
+++ b/targets/test.py
@@ -99,7 +99,7 @@ class TestDesign(UART2WB):
                self.submodules.crg = _CRG(platform)
 
                self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, 
-                       host=True, default_speed="SATA1")
+                       host=True, default_speed="SATA3")
                self.comb += [
                        self.sataphy_host.sink.stb.eq(1),
                        self.sataphy_host.sink.d.eq(0x12345678)

diff --git a/test/test_mila.py b/test/test_mila.py
index 79834a63ac967842b3b578ca932ee6063ba32917..2aed4403f42edce6b601c1a9d871816cec445e8e 100644 (file)
--- a/test/test_mila.py
+++ b/test/test_mila.py
@@ -1,7 +1,7 @@
 from config import *
 from miscope.host.drivers import MiLaDriver
 
-mila = MiLaDriver(wb.regs, "mila", use_rle=True)
+mila = MiLaDriver(wb.regs, "mila", use_rle=False)
 wb.open()
 ###
 trigger0 = mila.sataphy_host_gtx_txcominit0_o
@@ -11,7 +11,7 @@ mila.prog_term(port=0, trigger=trigger0, mask=mask0)
 mila.prog_sum("term")
 
 # Trigger / wait / receive
-mila.trigger(offset=8, length=64)
+mila.trigger(offset=8, length=512)
 mila.wait_done()
 mila.read()
 mila.export("dump.vcd")