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Merge pull request #834 from YosysHQ/clifford/siminit
authorClifford Wolf <clifford@clifford.at>
Thu, 28 Feb 2019 23:03:55 +0000 (15:03 -0800)
committerGitHub <noreply@github.com>
Thu, 28 Feb 2019 23:03:55 +0000 (15:03 -0800)
Add "write_verilog -siminit"


Trivial merge