(no commit message)

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index d403cf02b58a41aae541594aad52c80ef7c2d3d7..1e741937a28fed286f52221693b78b5fa9f7819c 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -449,8 +449,8 @@ Note: CSRRC and other bitsetting may still be used, they are however not particu
 ## Register key-value (CAM) table <a name="regcsrtable" />
 
 *NOTE: in prior versions of SV, this table used to be writable and
-accessible via CSRs. It is now stored in the VLIW instruction format,
-and entries may be overridden temporarily by the SVPrefix P48/64 format*
+accessible via CSRs. It is now stored in the VLIW instruction format. Note that 
+this table does *not* get applied to the SVPrefix P48/64 format, only to scalar opcodes*
 
 The purpose of the Register table is three-fold:
 
@@ -513,19 +513,18 @@ As the above table is a CAM (key-value store) it may be appropriate
 
     struct vectorised fp_vec[32], int_vec[32];
 
-    for (i = 0; i < 16; i++) // 16 CSRs?
+    for (i = 0; i < len; i++) // from VLIW Format
        tb = int_vec if CSRvec[i].type == 0 else fp_vec
        idx = CSRvec[i].regkey // INT/FP src/dst reg in opcode
        tb[idx].elwidth  = CSRvec[i].elwidth
        tb[idx].regidx   = CSRvec[i].regidx  // indirection
        tb[idx].isvector = CSRvec[i].isvector // 0=scalar
-       tb[idx].packed   = CSRvec[i].packed  // SIMD or not
 
 ## Predication Table <a name="predication_csr_table"></a>
 
 *NOTE: in prior versions of SV, this table used to be writable and
-accessible via CSRs. It is now stored in the VLIW instruction format,
-and entries may be overridden by the SVPrefix format*
+accessible via CSRs. It is now stored in the VLIW instruction format. 
+The table does **not** apply to SVPrefix opcodes*
 
 The Predication Table is a key-value store indicating whether, if a
 given destination register (integer or floating-point) is referred to